1 //===- X86Disassembler.cpp - Disassembler for x86 and x86_64 ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler.
11 // It contains code to translate the data produced by the decoder into
13 // Documentation for the disassembler can be found in X86Disassembler.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86Disassembler.h"
18 #include "X86DisassemblerDecoder.h"
20 #include "llvm/MC/EDInstInfo.h"
21 #include "llvm/MC/MCDisassembler.h"
22 #include "llvm/MC/MCDisassembler.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/MemoryObject.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
30 #define GET_REGINFO_ENUM
31 #include "X86GenRegisterInfo.inc"
32 #define GET_INSTRINFO_ENUM
33 #include "X86GenInstrInfo.inc"
34 #include "X86GenEDInfo.inc"
37 using namespace llvm::X86Disassembler;
39 void x86DisassemblerDebug(const char *file,
42 dbgs() << file << ":" << line << ": " << s;
45 #define debug(s) DEBUG(x86DisassemblerDebug(__FILE__, __LINE__, s));
49 // Fill-ins to make the compiler happy. These constants are never actually
50 // assigned; they are just filler to make an automatically-generated switch
63 extern Target TheX86_32Target, TheX86_64Target;
67 static bool translateInstruction(MCInst &target,
68 InternalInstruction &source);
70 X86GenericDisassembler::X86GenericDisassembler(const MCSubtargetInfo &STI, DisassemblerMode mode) :
75 X86GenericDisassembler::~X86GenericDisassembler() {
78 EDInstInfo *X86GenericDisassembler::getEDInfo() const {
82 void X86_16Disassembler::anchor() { }
84 void X86_32Disassembler::anchor() { }
86 void X86_64Disassembler::anchor() { }
88 /// regionReader - a callback function that wraps the readByte method from
91 /// @param arg - The generic callback parameter. In this case, this should
92 /// be a pointer to a MemoryObject.
93 /// @param byte - A pointer to the byte to be read.
94 /// @param address - The address to be read.
95 static int regionReader(void* arg, uint8_t* byte, uint64_t address) {
96 MemoryObject* region = static_cast<MemoryObject*>(arg);
97 return region->readByte(address, byte);
100 /// logger - a callback function that wraps the operator<< method from
103 /// @param arg - The generic callback parameter. This should be a pointe
104 /// to a raw_ostream.
105 /// @param log - A string to be logged. logger() adds a newline.
106 static void logger(void* arg, const char* log) {
110 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg));
111 vStream << log << "\n";
115 // Public interface for the disassembler
118 MCDisassembler::DecodeStatus
119 X86GenericDisassembler::getInstruction(MCInst &instr,
121 const MemoryObject ®ion,
123 raw_ostream &vStream,
124 raw_ostream &cStream) const {
125 InternalInstruction internalInstr;
127 dlog_t loggerFn = logger;
128 if (&vStream == &nulls())
129 loggerFn = 0; // Disable logging completely if it's going to nulls().
131 int ret = decodeInstruction(&internalInstr,
140 size = internalInstr.readerCursor - address;
144 size = internalInstr.length;
145 return (!translateInstruction(instr, internalInstr)) ? Success : Fail;
150 // Private code that translates from struct InternalInstructions to MCInsts.
153 /// translateRegister - Translates an internal register to the appropriate LLVM
154 /// register, and appends it as an operand to an MCInst.
156 /// @param mcInst - The MCInst to append to.
157 /// @param reg - The Reg to append.
158 static void translateRegister(MCInst &mcInst, Reg reg) {
159 #define ENTRY(x) X86::x,
160 uint8_t llvmRegnums[] = {
166 uint8_t llvmRegnum = llvmRegnums[reg];
167 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
170 /// translateImmediate - Appends an immediate operand to an MCInst.
172 /// @param mcInst - The MCInst to append to.
173 /// @param immediate - The immediate value to append.
174 /// @param operand - The operand, as stored in the descriptor table.
175 /// @param insn - The internal instruction.
176 static void translateImmediate(MCInst &mcInst, uint64_t immediate,
177 const OperandSpecifier &operand,
178 InternalInstruction &insn) {
179 // Sign-extend the immediate if necessary.
181 OperandType type = operand.type;
183 if (type == TYPE_RELv) {
184 switch (insn.displacementSize) {
201 // By default sign-extend all X86 immediates based on their encoding.
202 else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 ||
203 type == TYPE_IMM64) {
204 uint32_t Opcode = mcInst.getOpcode();
205 switch (operand.encoding) {
209 // Special case those X86 instructions that use the imm8 as a set of
210 // bits, bit count, etc. and are not sign-extend.
211 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
212 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
213 Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
214 Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &&
215 Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri &&
216 Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri &&
217 Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri &&
218 Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri &&
219 Opcode != X86::VINSERTPSrr)
236 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
239 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
244 immediate |= ~(0xffull);
247 if(immediate & 0x8000)
248 immediate |= ~(0xffffull);
253 if(immediate & 0x80000000)
254 immediate |= ~(0xffffffffull);
258 // operand is 64 bits wide. Do nothing.
262 mcInst.addOperand(MCOperand::CreateImm(immediate));
265 /// translateRMRegister - Translates a register stored in the R/M field of the
266 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
267 /// @param mcInst - The MCInst to append to.
268 /// @param insn - The internal instruction to extract the R/M field
270 /// @return - 0 on success; -1 otherwise
271 static bool translateRMRegister(MCInst &mcInst,
272 InternalInstruction &insn) {
273 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
274 debug("A R/M register operand may not have a SIB byte");
278 switch (insn.eaBase) {
280 debug("Unexpected EA base register");
283 debug("EA_BASE_NONE for ModR/M base");
285 #define ENTRY(x) case EA_BASE_##x:
288 debug("A R/M register operand may not have a base; "
289 "the operand must be a register.");
293 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
301 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M
302 /// fields of an internal instruction (and possibly its SIB byte) to a memory
303 /// operand in LLVM's format, and appends it to an MCInst.
305 /// @param mcInst - The MCInst to append to.
306 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
308 /// @return - 0 on success; nonzero otherwise
309 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn) {
310 // Addresses in an MCInst are represented as five operands:
311 // 1. basereg (register) The R/M base, or (if there is a SIB) the
313 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
315 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
316 // the index (which is multiplied by the
318 // 4. displacement (immediate) 0, or the displacement if there is one
319 // 5. segmentreg (register) x86_registerNONE for now, but could be set
320 // if we have segment overrides
323 MCOperand scaleAmount;
325 MCOperand displacement;
326 MCOperand segmentReg;
328 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
329 if (insn.sibBase != SIB_BASE_NONE) {
330 switch (insn.sibBase) {
332 debug("Unexpected sibBase");
336 baseReg = MCOperand::CreateReg(X86::x); break;
341 baseReg = MCOperand::CreateReg(0);
344 if (insn.sibIndex != SIB_INDEX_NONE) {
345 switch (insn.sibIndex) {
347 debug("Unexpected sibIndex");
350 case SIB_INDEX_##x: \
351 indexReg = MCOperand::CreateReg(X86::x); break;
357 indexReg = MCOperand::CreateReg(0);
360 scaleAmount = MCOperand::CreateImm(insn.sibScale);
362 switch (insn.eaBase) {
364 if (insn.eaDisplacement == EA_DISP_NONE) {
365 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
368 if (insn.mode == MODE_64BIT)
369 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
371 baseReg = MCOperand::CreateReg(0);
373 indexReg = MCOperand::CreateReg(0);
376 baseReg = MCOperand::CreateReg(X86::BX);
377 indexReg = MCOperand::CreateReg(X86::SI);
380 baseReg = MCOperand::CreateReg(X86::BX);
381 indexReg = MCOperand::CreateReg(X86::DI);
384 baseReg = MCOperand::CreateReg(X86::BP);
385 indexReg = MCOperand::CreateReg(X86::SI);
388 baseReg = MCOperand::CreateReg(X86::BP);
389 indexReg = MCOperand::CreateReg(X86::DI);
392 indexReg = MCOperand::CreateReg(0);
393 switch (insn.eaBase) {
395 debug("Unexpected eaBase");
397 // Here, we will use the fill-ins defined above. However,
398 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
399 // sib and sib64 were handled in the top-level if, so they're only
400 // placeholders to keep the compiler happy.
403 baseReg = MCOperand::CreateReg(X86::x); break;
406 #define ENTRY(x) case EA_REG_##x:
409 debug("A R/M memory operand may not be a register; "
410 "the base field must be a base.");
415 scaleAmount = MCOperand::CreateImm(1);
418 displacement = MCOperand::CreateImm(insn.displacement);
420 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
421 0, // SEG_OVERRIDE_NONE
430 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
432 mcInst.addOperand(baseReg);
433 mcInst.addOperand(scaleAmount);
434 mcInst.addOperand(indexReg);
435 mcInst.addOperand(displacement);
436 mcInst.addOperand(segmentReg);
440 /// translateRM - Translates an operand stored in the R/M (and possibly SIB)
441 /// byte of an instruction to LLVM form, and appends it to an MCInst.
443 /// @param mcInst - The MCInst to append to.
444 /// @param operand - The operand, as stored in the descriptor table.
445 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
447 /// @return - 0 on success; nonzero otherwise
448 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
449 InternalInstruction &insn) {
450 switch (operand.type) {
452 debug("Unexpected type for a R/M operand");
468 case TYPE_CONTROLREG:
469 return translateRMRegister(mcInst, insn);
489 return translateRMMemory(mcInst, insn);
493 /// translateFPRegister - Translates a stack position on the FPU stack to its
494 /// LLVM form, and appends it to an MCInst.
496 /// @param mcInst - The MCInst to append to.
497 /// @param stackPos - The stack position to translate.
498 /// @return - 0 on success; nonzero otherwise.
499 static bool translateFPRegister(MCInst &mcInst,
502 debug("Invalid FP stack position");
506 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
511 /// translateOperand - Translates an operand stored in an internal instruction
512 /// to LLVM's format and appends it to an MCInst.
514 /// @param mcInst - The MCInst to append to.
515 /// @param operand - The operand, as stored in the descriptor table.
516 /// @param insn - The internal instruction.
517 /// @return - false on success; true otherwise.
518 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
519 InternalInstruction &insn) {
520 switch (operand.encoding) {
522 debug("Unhandled operand encoding during translation");
525 translateRegister(mcInst, insn.reg);
528 return translateRM(mcInst, operand, insn);
535 debug("Translation of code offsets isn't supported.");
543 translateImmediate(mcInst,
544 insn.immediates[insn.numImmediatesTranslated++],
552 translateRegister(mcInst, insn.opcodeRegister);
555 return translateFPRegister(mcInst, insn.opcodeModifier);
557 translateRegister(mcInst, insn.opcodeRegister);
560 translateRegister(mcInst, insn.vvvv);
563 return translateOperand(mcInst,
564 insn.spec->operands[operand.type - TYPE_DUP0],
569 /// translateInstruction - Translates an internal instruction and all its
570 /// operands to an MCInst.
572 /// @param mcInst - The MCInst to populate with the instruction's data.
573 /// @param insn - The internal instruction.
574 /// @return - false on success; true otherwise.
575 static bool translateInstruction(MCInst &mcInst,
576 InternalInstruction &insn) {
578 debug("Instruction has no specification");
582 mcInst.setOpcode(insn.instructionID);
586 insn.numImmediatesTranslated = 0;
588 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
589 if (insn.spec->operands[index].encoding != ENCODING_NONE) {
590 if (translateOperand(mcInst, insn.spec->operands[index], insn)) {
599 static MCDisassembler *createX86_32Disassembler(const Target &T, const MCSubtargetInfo &STI) {
600 return new X86Disassembler::X86_32Disassembler(STI);
603 static MCDisassembler *createX86_64Disassembler(const Target &T, const MCSubtargetInfo &STI) {
604 return new X86Disassembler::X86_64Disassembler(STI);
607 extern "C" void LLVMInitializeX86Disassembler() {
608 // Register the disassembler.
609 TargetRegistry::RegisterMCDisassembler(TheX86_32Target,
610 createX86_32Disassembler);
611 TargetRegistry::RegisterMCDisassembler(TheX86_64Target,
612 createX86_64Disassembler);