1 //===- X86Disassembler.cpp - Disassembler for x86 and x86_64 ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler.
11 // It contains code to translate the data produced by the decoder into
13 // Documentation for the disassembler can be found in X86Disassembler.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86Disassembler.h"
18 #include "X86DisassemblerDecoder.h"
20 #include "llvm/MC/EDInstInfo.h"
21 #include "llvm/MC/MCDisassembler.h"
22 #include "llvm/MC/MCDisassembler.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/Target/TargetRegistry.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/MemoryObject.h"
27 #include "llvm/Support/raw_ostream.h"
29 #include "X86GenRegisterNames.inc"
30 #include "X86GenEDInfo.inc"
33 using namespace llvm::X86Disassembler;
35 void x86DisassemblerDebug(const char *file,
38 dbgs() << file << ":" << line << ": " << s;
41 #define debug(s) DEBUG(x86DisassemblerDebug(__FILE__, __LINE__, s));
45 // Fill-ins to make the compiler happy. These constants are never actually
46 // assigned; they are just filler to make an automatically-generated switch
59 extern Target TheX86_32Target, TheX86_64Target;
63 static bool translateInstruction(MCInst &target,
64 InternalInstruction &source);
66 X86GenericDisassembler::X86GenericDisassembler(DisassemblerMode mode) :
71 X86GenericDisassembler::~X86GenericDisassembler() {
74 EDInstInfo *X86GenericDisassembler::getEDInfo() const {
78 /// regionReader - a callback function that wraps the readByte method from
81 /// @param arg - The generic callback parameter. In this case, this should
82 /// be a pointer to a MemoryObject.
83 /// @param byte - A pointer to the byte to be read.
84 /// @param address - The address to be read.
85 static int regionReader(void* arg, uint8_t* byte, uint64_t address) {
86 MemoryObject* region = static_cast<MemoryObject*>(arg);
87 return region->readByte(address, byte);
90 /// logger - a callback function that wraps the operator<< method from
93 /// @param arg - The generic callback parameter. This should be a pointe
95 /// @param log - A string to be logged. logger() adds a newline.
96 static void logger(void* arg, const char* log) {
100 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg));
101 vStream << log << "\n";
105 // Public interface for the disassembler
108 bool X86GenericDisassembler::getInstruction(MCInst &instr,
110 const MemoryObject ®ion,
112 raw_ostream &vStream) const {
113 InternalInstruction internalInstr;
115 int ret = decodeInstruction(&internalInstr,
124 size = internalInstr.readerCursor - address;
128 size = internalInstr.length;
129 return !translateInstruction(instr, internalInstr);
134 // Private code that translates from struct InternalInstructions to MCInsts.
137 /// translateRegister - Translates an internal register to the appropriate LLVM
138 /// register, and appends it as an operand to an MCInst.
140 /// @param mcInst - The MCInst to append to.
141 /// @param reg - The Reg to append.
142 static void translateRegister(MCInst &mcInst, Reg reg) {
143 #define ENTRY(x) X86::x,
144 uint8_t llvmRegnums[] = {
150 uint8_t llvmRegnum = llvmRegnums[reg];
151 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
154 /// translateImmediate - Appends an immediate operand to an MCInst.
156 /// @param mcInst - The MCInst to append to.
157 /// @param immediate - The immediate value to append.
158 /// @param operand - The operand, as stored in the descriptor table.
159 /// @param insn - The internal instruction.
160 static void translateImmediate(MCInst &mcInst, uint64_t immediate,
161 const OperandSpecifier &operand,
162 InternalInstruction &insn) {
163 // Sign-extend the immediate if necessary.
165 OperandType type = operand.type;
167 if (type == TYPE_RELv) {
168 switch (insn.displacementSize) {
190 immediate |= ~(0xffull);
193 if(immediate & 0x8000)
194 immediate |= ~(0xffffull);
199 if(immediate & 0x80000000)
200 immediate |= ~(0xffffffffull);
204 // operand is 64 bits wide. Do nothing.
208 mcInst.addOperand(MCOperand::CreateImm(immediate));
211 /// translateRMRegister - Translates a register stored in the R/M field of the
212 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
213 /// @param mcInst - The MCInst to append to.
214 /// @param insn - The internal instruction to extract the R/M field
216 /// @return - 0 on success; -1 otherwise
217 static bool translateRMRegister(MCInst &mcInst,
218 InternalInstruction &insn) {
219 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
220 debug("A R/M register operand may not have a SIB byte");
224 switch (insn.eaBase) {
226 debug("Unexpected EA base register");
229 debug("EA_BASE_NONE for ModR/M base");
231 #define ENTRY(x) case EA_BASE_##x:
234 debug("A R/M register operand may not have a base; "
235 "the operand must be a register.");
239 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
247 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M
248 /// fields of an internal instruction (and possibly its SIB byte) to a memory
249 /// operand in LLVM's format, and appends it to an MCInst.
251 /// @param mcInst - The MCInst to append to.
252 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
254 /// @return - 0 on success; nonzero otherwise
255 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn) {
256 // Addresses in an MCInst are represented as five operands:
257 // 1. basereg (register) The R/M base, or (if there is a SIB) the
259 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
261 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
262 // the index (which is multiplied by the
264 // 4. displacement (immediate) 0, or the displacement if there is one
265 // 5. segmentreg (register) x86_registerNONE for now, but could be set
266 // if we have segment overrides
269 MCOperand scaleAmount;
271 MCOperand displacement;
272 MCOperand segmentReg;
274 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
275 if (insn.sibBase != SIB_BASE_NONE) {
276 switch (insn.sibBase) {
278 debug("Unexpected sibBase");
282 baseReg = MCOperand::CreateReg(X86::x); break;
287 baseReg = MCOperand::CreateReg(0);
290 if (insn.sibIndex != SIB_INDEX_NONE) {
291 switch (insn.sibIndex) {
293 debug("Unexpected sibIndex");
296 case SIB_INDEX_##x: \
297 indexReg = MCOperand::CreateReg(X86::x); break;
303 indexReg = MCOperand::CreateReg(0);
306 scaleAmount = MCOperand::CreateImm(insn.sibScale);
308 switch (insn.eaBase) {
310 if (insn.eaDisplacement == EA_DISP_NONE) {
311 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
314 if (insn.mode == MODE_64BIT)
315 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
317 baseReg = MCOperand::CreateReg(0);
319 indexReg = MCOperand::CreateReg(0);
322 baseReg = MCOperand::CreateReg(X86::BX);
323 indexReg = MCOperand::CreateReg(X86::SI);
326 baseReg = MCOperand::CreateReg(X86::BX);
327 indexReg = MCOperand::CreateReg(X86::DI);
330 baseReg = MCOperand::CreateReg(X86::BP);
331 indexReg = MCOperand::CreateReg(X86::SI);
334 baseReg = MCOperand::CreateReg(X86::BP);
335 indexReg = MCOperand::CreateReg(X86::DI);
338 indexReg = MCOperand::CreateReg(0);
339 switch (insn.eaBase) {
341 debug("Unexpected eaBase");
343 // Here, we will use the fill-ins defined above. However,
344 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
345 // sib and sib64 were handled in the top-level if, so they're only
346 // placeholders to keep the compiler happy.
349 baseReg = MCOperand::CreateReg(X86::x); break;
352 #define ENTRY(x) case EA_REG_##x:
355 debug("A R/M memory operand may not be a register; "
356 "the base field must be a base.");
361 scaleAmount = MCOperand::CreateImm(1);
364 displacement = MCOperand::CreateImm(insn.displacement);
366 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
367 0, // SEG_OVERRIDE_NONE
376 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
378 mcInst.addOperand(baseReg);
379 mcInst.addOperand(scaleAmount);
380 mcInst.addOperand(indexReg);
381 mcInst.addOperand(displacement);
382 mcInst.addOperand(segmentReg);
386 /// translateRM - Translates an operand stored in the R/M (and possibly SIB)
387 /// byte of an instruction to LLVM form, and appends it to an MCInst.
389 /// @param mcInst - The MCInst to append to.
390 /// @param operand - The operand, as stored in the descriptor table.
391 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
393 /// @return - 0 on success; nonzero otherwise
394 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
395 InternalInstruction &insn) {
396 switch (operand.type) {
398 debug("Unexpected type for a R/M operand");
413 case TYPE_CONTROLREG:
414 return translateRMRegister(mcInst, insn);
433 return translateRMMemory(mcInst, insn);
437 /// translateFPRegister - Translates a stack position on the FPU stack to its
438 /// LLVM form, and appends it to an MCInst.
440 /// @param mcInst - The MCInst to append to.
441 /// @param stackPos - The stack position to translate.
442 /// @return - 0 on success; nonzero otherwise.
443 static bool translateFPRegister(MCInst &mcInst,
446 debug("Invalid FP stack position");
450 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
455 /// translateOperand - Translates an operand stored in an internal instruction
456 /// to LLVM's format and appends it to an MCInst.
458 /// @param mcInst - The MCInst to append to.
459 /// @param operand - The operand, as stored in the descriptor table.
460 /// @param insn - The internal instruction.
461 /// @return - false on success; true otherwise.
462 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
463 InternalInstruction &insn) {
464 switch (operand.encoding) {
466 debug("Unhandled operand encoding during translation");
469 translateRegister(mcInst, insn.reg);
472 return translateRM(mcInst, operand, insn);
479 debug("Translation of code offsets isn't supported.");
487 translateImmediate(mcInst,
488 insn.immediates[insn.numImmediatesTranslated++],
496 translateRegister(mcInst, insn.opcodeRegister);
499 return translateFPRegister(mcInst, insn.opcodeModifier);
501 translateRegister(mcInst, insn.opcodeRegister);
504 return translateOperand(mcInst,
505 insn.spec->operands[operand.type - TYPE_DUP0],
510 /// translateInstruction - Translates an internal instruction and all its
511 /// operands to an MCInst.
513 /// @param mcInst - The MCInst to populate with the instruction's data.
514 /// @param insn - The internal instruction.
515 /// @return - false on success; true otherwise.
516 static bool translateInstruction(MCInst &mcInst,
517 InternalInstruction &insn) {
519 debug("Instruction has no specification");
523 mcInst.setOpcode(insn.instructionID);
527 insn.numImmediatesTranslated = 0;
529 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
530 if (insn.spec->operands[index].encoding != ENCODING_NONE) {
531 if (translateOperand(mcInst, insn.spec->operands[index], insn)) {
540 static MCDisassembler *createX86_32Disassembler(const Target &T) {
541 return new X86Disassembler::X86_32Disassembler;
544 static MCDisassembler *createX86_64Disassembler(const Target &T) {
545 return new X86Disassembler::X86_64Disassembler;
548 extern "C" void LLVMInitializeX86Disassembler() {
549 // Register the disassembler.
550 TargetRegistry::RegisterMCDisassembler(TheX86_32Target,
551 createX86_32Disassembler);
552 TargetRegistry::RegisterMCDisassembler(TheX86_64Target,
553 createX86_64Disassembler);