1 //===- X86Disassembler.cpp - Disassembler for x86 and x86_64 ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler.
11 // It contains code to translate the data produced by the decoder into
13 // Documentation for the disassembler can be found in X86Disassembler.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86Disassembler.h"
18 #include "X86DisassemblerDecoder.h"
20 #include "llvm/MC/MCDisassembler.h"
21 #include "llvm/MC/MCDisassembler.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/Target/TargetRegistry.h"
24 #include "llvm/Support/MemoryObject.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
28 #include "X86GenRegisterNames.inc"
31 using namespace llvm::X86Disassembler;
35 // Fill-ins to make the compiler happy. These constants are never actually
36 // assigned; they are just filler to make an automatically-generated switch
49 extern Target TheX86_32Target, TheX86_64Target;
53 static void translateInstruction(MCInst &target,
54 InternalInstruction &source);
56 X86GenericDisassembler::X86GenericDisassembler(DisassemblerMode mode) :
61 X86GenericDisassembler::~X86GenericDisassembler() {
64 /// regionReader - a callback function that wraps the readByte method from
67 /// @param arg - The generic callback parameter. In this case, this should
68 /// be a pointer to a MemoryObject.
69 /// @param byte - A pointer to the byte to be read.
70 /// @param address - The address to be read.
71 static int regionReader(void* arg, uint8_t* byte, uint64_t address) {
72 MemoryObject* region = static_cast<MemoryObject*>(arg);
73 return region->readByte(address, byte);
76 /// logger - a callback function that wraps the operator<< method from
79 /// @param arg - The generic callback parameter. This should be a pointe
81 /// @param log - A string to be logged. logger() adds a newline.
82 static void logger(void* arg, const char* log) {
86 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg));
87 vStream << log << "\n";
91 // Public interface for the disassembler
94 bool X86GenericDisassembler::getInstruction(MCInst &instr,
96 const MemoryObject ®ion,
98 raw_ostream &vStream) const {
99 InternalInstruction internalInstr;
101 int ret = decodeInstruction(&internalInstr,
110 size = internalInstr.readerCursor - address;
114 size = internalInstr.length;
115 translateInstruction(instr, internalInstr);
121 // Private code that translates from struct InternalInstructions to MCInsts.
124 /// translateRegister - Translates an internal register to the appropriate LLVM
125 /// register, and appends it as an operand to an MCInst.
127 /// @param mcInst - The MCInst to append to.
128 /// @param reg - The Reg to append.
129 static void translateRegister(MCInst &mcInst, Reg reg) {
130 #define ENTRY(x) X86::x,
131 uint8_t llvmRegnums[] = {
137 uint8_t llvmRegnum = llvmRegnums[reg];
138 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
141 /// translateImmediate - Appends an immediate operand to an MCInst.
143 /// @param mcInst - The MCInst to append to.
144 /// @param immediate - The immediate value to append.
145 static void translateImmediate(MCInst &mcInst, uint64_t immediate) {
146 mcInst.addOperand(MCOperand::CreateImm(immediate));
149 /// translateRMRegister - Translates a register stored in the R/M field of the
150 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
151 /// @param mcInst - The MCInst to append to.
152 /// @param insn - The internal instruction to extract the R/M field
154 static void translateRMRegister(MCInst &mcInst,
155 InternalInstruction &insn) {
156 assert(insn.eaBase != EA_BASE_sib && insn.eaBase != EA_BASE_sib64 &&
157 "A R/M register operand may not have a SIB byte");
159 switch (insn.eaBase) {
161 llvm_unreachable("EA_BASE_NONE for ModR/M base");
163 #define ENTRY(x) case EA_BASE_##x:
166 llvm_unreachable("A R/M register operand may not have a base; "
167 "the operand must be a register.");
171 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
175 llvm_unreachable("Unexpected EA base register");
179 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M
180 /// fields of an internal instruction (and possibly its SIB byte) to a memory
181 /// operand in LLVM's format, and appends it to an MCInst.
183 /// @param mcInst - The MCInst to append to.
184 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
186 /// @param sr - Whether or not to emit the segment register. The
187 /// LEA instruction does not expect a segment-register
189 static void translateRMMemory(MCInst &mcInst,
190 InternalInstruction &insn,
192 // Addresses in an MCInst are represented as five operands:
193 // 1. basereg (register) The R/M base, or (if there is a SIB) the
195 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
197 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
198 // the index (which is multiplied by the
200 // 4. displacement (immediate) 0, or the displacement if there is one
201 // 5. segmentreg (register) x86_registerNONE for now, but could be set
202 // if we have segment overrides
205 MCOperand scaleAmount;
207 MCOperand displacement;
208 MCOperand segmentReg;
210 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
211 if (insn.sibBase != SIB_BASE_NONE) {
212 switch (insn.sibBase) {
214 llvm_unreachable("Unexpected sibBase");
217 baseReg = MCOperand::CreateReg(X86::x); break;
222 baseReg = MCOperand::CreateReg(0);
225 if (insn.sibIndex != SIB_INDEX_NONE) {
226 switch (insn.sibIndex) {
228 llvm_unreachable("Unexpected sibIndex");
230 case SIB_INDEX_##x: \
231 indexReg = MCOperand::CreateReg(X86::x); break;
237 indexReg = MCOperand::CreateReg(0);
240 scaleAmount = MCOperand::CreateImm(insn.sibScale);
242 switch (insn.eaBase) {
244 assert(insn.eaDisplacement != EA_DISP_NONE &&
245 "EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
247 if (insn.mode == MODE_64BIT)
248 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
250 baseReg = MCOperand::CreateReg(0);
252 indexReg = MCOperand::CreateReg(0);
255 baseReg = MCOperand::CreateReg(X86::BX);
256 indexReg = MCOperand::CreateReg(X86::SI);
259 baseReg = MCOperand::CreateReg(X86::BX);
260 indexReg = MCOperand::CreateReg(X86::DI);
263 baseReg = MCOperand::CreateReg(X86::BP);
264 indexReg = MCOperand::CreateReg(X86::SI);
267 baseReg = MCOperand::CreateReg(X86::BP);
268 indexReg = MCOperand::CreateReg(X86::DI);
271 indexReg = MCOperand::CreateReg(0);
272 switch (insn.eaBase) {
274 llvm_unreachable("Unexpected eaBase");
276 // Here, we will use the fill-ins defined above. However,
277 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
278 // sib and sib64 were handled in the top-level if, so they're only
279 // placeholders to keep the compiler happy.
282 baseReg = MCOperand::CreateReg(X86::x); break;
285 #define ENTRY(x) case EA_REG_##x:
288 llvm_unreachable("A R/M memory operand may not be a register; "
289 "the base field must be a base.");
294 scaleAmount = MCOperand::CreateImm(1);
297 displacement = MCOperand::CreateImm(insn.displacement);
299 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
300 0, // SEG_OVERRIDE_NONE
309 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
311 mcInst.addOperand(baseReg);
312 mcInst.addOperand(scaleAmount);
313 mcInst.addOperand(indexReg);
314 mcInst.addOperand(displacement);
317 mcInst.addOperand(segmentReg);
320 /// translateRM - Translates an operand stored in the R/M (and possibly SIB)
321 /// byte of an instruction to LLVM form, and appends it to an MCInst.
323 /// @param mcInst - The MCInst to append to.
324 /// @param operand - The operand, as stored in the descriptor table.
325 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
327 static void translateRM(MCInst &mcInst,
328 OperandSpecifier &operand,
329 InternalInstruction &insn) {
330 switch (operand.type) {
332 llvm_unreachable("Unexpected type for a R/M operand");
348 translateRMRegister(mcInst, insn);
367 translateRMMemory(mcInst, insn, true);
370 translateRMMemory(mcInst, insn, false);
375 /// translateFPRegister - Translates a stack position on the FPU stack to its
376 /// LLVM form, and appends it to an MCInst.
378 /// @param mcInst - The MCInst to append to.
379 /// @param stackPos - The stack position to translate.
380 static void translateFPRegister(MCInst &mcInst,
382 assert(stackPos < 8 && "Invalid FP stack position");
384 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
387 /// translateOperand - Translates an operand stored in an internal instruction
388 /// to LLVM's format and appends it to an MCInst.
390 /// @param mcInst - The MCInst to append to.
391 /// @param operand - The operand, as stored in the descriptor table.
392 /// @param insn - The internal instruction.
393 static void translateOperand(MCInst &mcInst,
394 OperandSpecifier &operand,
395 InternalInstruction &insn) {
396 switch (operand.encoding) {
398 llvm_unreachable("Unhandled operand encoding during translation");
400 translateRegister(mcInst, insn.reg);
403 translateRM(mcInst, operand, insn);
411 llvm_unreachable("Translation of code offsets isn't supported.");
418 translateImmediate(mcInst,
419 insn.immediates[insn.numImmediatesTranslated++]);
425 translateRegister(mcInst, insn.opcodeRegister);
428 translateFPRegister(mcInst, insn.opcodeModifier);
431 translateRegister(mcInst, insn.opcodeRegister);
434 translateOperand(mcInst,
435 insn.spec->operands[operand.type - TYPE_DUP0],
441 /// translateInstruction - Translates an internal instruction and all its
442 /// operands to an MCInst.
444 /// @param mcInst - The MCInst to populate with the instruction's data.
445 /// @param insn - The internal instruction.
446 static void translateInstruction(MCInst &mcInst,
447 InternalInstruction &insn) {
450 mcInst.setOpcode(insn.instructionID);
454 insn.numImmediatesTranslated = 0;
456 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
457 if (insn.spec->operands[index].encoding != ENCODING_NONE)
458 translateOperand(mcInst, insn.spec->operands[index], insn);
462 static const MCDisassembler *createX86_32Disassembler(const Target &T) {
463 return new X86Disassembler::X86_32Disassembler;
466 static const MCDisassembler *createX86_64Disassembler(const Target &T) {
467 return new X86Disassembler::X86_64Disassembler;
470 extern "C" void LLVMInitializeX86Disassembler() {
471 // Register the disassembler.
472 TargetRegistry::RegisterMCDisassembler(TheX86_32Target,
473 createX86_32Disassembler);
474 TargetRegistry::RegisterMCDisassembler(TheX86_64Target,
475 createX86_64Disassembler);