1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler.
11 // It contains code to translate the data produced by the decoder into
13 // Documentation for the disassembler can be found in X86Disassembler.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86Disassembler.h"
18 #include "X86DisassemblerDecoder.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCDisassembler.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/MemoryObject.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
30 #define GET_REGINFO_ENUM
31 #include "X86GenRegisterInfo.inc"
32 #define GET_INSTRINFO_ENUM
33 #include "X86GenInstrInfo.inc"
36 using namespace llvm::X86Disassembler;
38 void x86DisassemblerDebug(const char *file,
41 dbgs() << file << ":" << line << ": " << s;
44 const char *x86DisassemblerGetInstrName(unsigned Opcode, const void *mii) {
45 const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii);
46 return MII->getName(Opcode);
49 #define debug(s) DEBUG(x86DisassemblerDebug(__FILE__, __LINE__, s));
53 // Fill-ins to make the compiler happy. These constants are never actually
54 // assigned; they are just filler to make an automatically-generated switch
67 extern Target TheX86_32Target, TheX86_64Target;
71 static bool translateInstruction(MCInst &target,
72 InternalInstruction &source,
73 const MCDisassembler *Dis);
75 X86GenericDisassembler::X86GenericDisassembler(const MCSubtargetInfo &STI,
76 DisassemblerMode mode,
77 const MCInstrInfo *MII)
78 : MCDisassembler(STI), MII(MII), fMode(mode) {}
80 X86GenericDisassembler::~X86GenericDisassembler() {
84 /// regionReader - a callback function that wraps the readByte method from
87 /// @param arg - The generic callback parameter. In this case, this should
88 /// be a pointer to a MemoryObject.
89 /// @param byte - A pointer to the byte to be read.
90 /// @param address - The address to be read.
91 static int regionReader(const void* arg, uint8_t* byte, uint64_t address) {
92 const MemoryObject* region = static_cast<const MemoryObject*>(arg);
93 return region->readByte(address, byte);
96 /// logger - a callback function that wraps the operator<< method from
99 /// @param arg - The generic callback parameter. This should be a pointe
100 /// to a raw_ostream.
101 /// @param log - A string to be logged. logger() adds a newline.
102 static void logger(void* arg, const char* log) {
106 raw_ostream &vStream = *(static_cast<raw_ostream*>(arg));
107 vStream << log << "\n";
111 // Public interface for the disassembler
114 MCDisassembler::DecodeStatus
115 X86GenericDisassembler::getInstruction(MCInst &instr,
117 const MemoryObject ®ion,
119 raw_ostream &vStream,
120 raw_ostream &cStream) const {
121 CommentStream = &cStream;
123 InternalInstruction internalInstr;
125 dlog_t loggerFn = logger;
126 if (&vStream == &nulls())
127 loggerFn = 0; // Disable logging completely if it's going to nulls().
129 int ret = decodeInstruction(&internalInstr,
131 (const void*)®ion,
139 size = internalInstr.readerCursor - address;
143 size = internalInstr.length;
144 return (!translateInstruction(instr, internalInstr, this)) ?
150 // Private code that translates from struct InternalInstructions to MCInsts.
153 /// translateRegister - Translates an internal register to the appropriate LLVM
154 /// register, and appends it as an operand to an MCInst.
156 /// @param mcInst - The MCInst to append to.
157 /// @param reg - The Reg to append.
158 static void translateRegister(MCInst &mcInst, Reg reg) {
159 #define ENTRY(x) X86::x,
160 uint8_t llvmRegnums[] = {
166 uint8_t llvmRegnum = llvmRegnums[reg];
167 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
170 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
171 /// immediate Value in the MCInst.
173 /// @param Value - The immediate Value, has had any PC adjustment made by
175 /// @param isBranch - If the instruction is a branch instruction
176 /// @param Address - The starting address of the instruction
177 /// @param Offset - The byte offset to this immediate in the instruction
178 /// @param Width - The byte width of this immediate in the instruction
180 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
181 /// called then that function is called to get any symbolic information for the
182 /// immediate in the instruction using the Address, Offset and Width. If that
183 /// returns non-zero then the symbolic information it returns is used to create
184 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
185 /// returns zero and isBranch is true then a symbol look up for immediate Value
186 /// is done and if a symbol is found an MCExpr is created with that, else
187 /// an MCExpr with the immediate Value is created. This function returns true
188 /// if it adds an operand to the MCInst and false otherwise.
189 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
190 uint64_t Address, uint64_t Offset,
191 uint64_t Width, MCInst &MI,
192 const MCDisassembler *Dis) {
193 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
197 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
198 /// referenced by a load instruction with the base register that is the rip.
199 /// These can often be addresses in a literal pool. The Address of the
200 /// instruction and its immediate Value are used to determine the address
201 /// being referenced in the literal pool entry. The SymbolLookUp call back will
202 /// return a pointer to a literal 'C' string if the referenced address is an
203 /// address into a section with 'C' string literals.
204 static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value,
205 const void *Decoder) {
206 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
207 Dis->tryAddingPcLoadReferenceComment(Value, Address);
210 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
211 0, // SEG_OVERRIDE_NONE
220 /// translateImmediate - Appends an immediate operand to an MCInst.
222 /// @param mcInst - The MCInst to append to.
223 /// @param immediate - The immediate value to append.
224 /// @param operand - The operand, as stored in the descriptor table.
225 /// @param insn - The internal instruction.
226 static void translateImmediate(MCInst &mcInst, uint64_t immediate,
227 const OperandSpecifier &operand,
228 InternalInstruction &insn,
229 const MCDisassembler *Dis) {
230 // Sign-extend the immediate if necessary.
232 OperandType type = (OperandType)operand.type;
234 bool isBranch = false;
236 if (type == TYPE_RELv) {
238 pcrel = insn.startLocation +
239 insn.immediateOffset + insn.immediateSize;
240 switch (insn.displacementSize) {
245 immediate |= ~(0xffull);
248 if(immediate & 0x8000)
249 immediate |= ~(0xffffull);
252 if(immediate & 0x80000000)
253 immediate |= ~(0xffffffffull);
259 // By default sign-extend all X86 immediates based on their encoding.
260 else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 ||
261 type == TYPE_IMM64) {
262 uint32_t Opcode = mcInst.getOpcode();
263 switch (operand.encoding) {
267 // Special case those X86 instructions that use the imm8 as a set of
268 // bits, bit count, etc. and are not sign-extend.
269 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
270 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
271 Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
272 Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &&
273 Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri &&
274 Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri &&
275 Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri &&
276 Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri &&
277 Opcode != X86::VINSERTPSrr)
279 immediate |= ~(0xffull);
282 if(immediate & 0x8000)
283 immediate |= ~(0xffffull);
286 if(immediate & 0x80000000)
287 immediate |= ~(0xffffffffull);
298 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
301 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
304 mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)));
308 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
310 immediate |= ~(0xffull);
315 pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
316 if(immediate & 0x80000000)
317 immediate |= ~(0xffffffffull);
320 // operand is 64 bits wide. Do nothing.
324 if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation,
325 insn.immediateOffset, insn.immediateSize,
327 mcInst.addOperand(MCOperand::CreateImm(immediate));
329 if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 ||
330 type == TYPE_MOFFS32 || type == TYPE_MOFFS64) {
331 MCOperand segmentReg;
332 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
333 mcInst.addOperand(segmentReg);
337 /// translateRMRegister - Translates a register stored in the R/M field of the
338 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
339 /// @param mcInst - The MCInst to append to.
340 /// @param insn - The internal instruction to extract the R/M field
342 /// @return - 0 on success; -1 otherwise
343 static bool translateRMRegister(MCInst &mcInst,
344 InternalInstruction &insn) {
345 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
346 debug("A R/M register operand may not have a SIB byte");
350 switch (insn.eaBase) {
352 debug("Unexpected EA base register");
355 debug("EA_BASE_NONE for ModR/M base");
357 #define ENTRY(x) case EA_BASE_##x:
360 debug("A R/M register operand may not have a base; "
361 "the operand must be a register.");
365 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
373 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M
374 /// fields of an internal instruction (and possibly its SIB byte) to a memory
375 /// operand in LLVM's format, and appends it to an MCInst.
377 /// @param mcInst - The MCInst to append to.
378 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
380 /// @return - 0 on success; nonzero otherwise
381 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
382 const MCDisassembler *Dis) {
383 // Addresses in an MCInst are represented as five operands:
384 // 1. basereg (register) The R/M base, or (if there is a SIB) the
386 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
388 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
389 // the index (which is multiplied by the
391 // 4. displacement (immediate) 0, or the displacement if there is one
392 // 5. segmentreg (register) x86_registerNONE for now, but could be set
393 // if we have segment overrides
396 MCOperand scaleAmount;
398 MCOperand displacement;
399 MCOperand segmentReg;
402 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
403 if (insn.sibBase != SIB_BASE_NONE) {
404 switch (insn.sibBase) {
406 debug("Unexpected sibBase");
410 baseReg = MCOperand::CreateReg(X86::x); break;
415 baseReg = MCOperand::CreateReg(0);
418 // Check whether we are handling VSIB addressing mode for GATHER.
419 // If sibIndex was set to SIB_INDEX_NONE, index offset is 4 and
420 // we should use SIB_INDEX_XMM4|YMM4 for VSIB.
421 // I don't see a way to get the correct IndexReg in readSIB:
422 // We can tell whether it is VSIB or SIB after instruction ID is decoded,
423 // but instruction ID may not be decoded yet when calling readSIB.
424 uint32_t Opcode = mcInst.getOpcode();
425 bool IndexIs128 = (Opcode == X86::VGATHERDPDrm ||
426 Opcode == X86::VGATHERDPDYrm ||
427 Opcode == X86::VGATHERQPDrm ||
428 Opcode == X86::VGATHERDPSrm ||
429 Opcode == X86::VGATHERQPSrm ||
430 Opcode == X86::VPGATHERDQrm ||
431 Opcode == X86::VPGATHERDQYrm ||
432 Opcode == X86::VPGATHERQQrm ||
433 Opcode == X86::VPGATHERDDrm ||
434 Opcode == X86::VPGATHERQDrm);
435 bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm ||
436 Opcode == X86::VGATHERDPSYrm ||
437 Opcode == X86::VGATHERQPSYrm ||
438 Opcode == X86::VGATHERDPDZrm ||
439 Opcode == X86::VPGATHERDQZrm ||
440 Opcode == X86::VPGATHERQQYrm ||
441 Opcode == X86::VPGATHERDDYrm ||
442 Opcode == X86::VPGATHERQDYrm);
443 bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm ||
444 Opcode == X86::VGATHERDPSZrm ||
445 Opcode == X86::VGATHERQPSZrm ||
446 Opcode == X86::VPGATHERQQZrm ||
447 Opcode == X86::VPGATHERDDZrm ||
448 Opcode == X86::VPGATHERQDZrm);
449 if (IndexIs128 || IndexIs256 || IndexIs512) {
450 unsigned IndexOffset = insn.sibIndex -
451 (insn.addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX);
452 SIBIndex IndexBase = IndexIs512 ? SIB_INDEX_ZMM0 :
453 IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0;
454 insn.sibIndex = (SIBIndex)(IndexBase +
455 (insn.sibIndex == SIB_INDEX_NONE ? 4 : IndexOffset));
458 if (insn.sibIndex != SIB_INDEX_NONE) {
459 switch (insn.sibIndex) {
461 debug("Unexpected sibIndex");
464 case SIB_INDEX_##x: \
465 indexReg = MCOperand::CreateReg(X86::x); break;
474 indexReg = MCOperand::CreateReg(0);
477 scaleAmount = MCOperand::CreateImm(insn.sibScale);
479 switch (insn.eaBase) {
481 if (insn.eaDisplacement == EA_DISP_NONE) {
482 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
485 if (insn.mode == MODE_64BIT){
486 pcrel = insn.startLocation +
487 insn.displacementOffset + insn.displacementSize;
488 tryAddingPcLoadReferenceComment(insn.startLocation +
489 insn.displacementOffset,
490 insn.displacement + pcrel, Dis);
491 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
494 baseReg = MCOperand::CreateReg(0);
496 indexReg = MCOperand::CreateReg(0);
499 baseReg = MCOperand::CreateReg(X86::BX);
500 indexReg = MCOperand::CreateReg(X86::SI);
503 baseReg = MCOperand::CreateReg(X86::BX);
504 indexReg = MCOperand::CreateReg(X86::DI);
507 baseReg = MCOperand::CreateReg(X86::BP);
508 indexReg = MCOperand::CreateReg(X86::SI);
511 baseReg = MCOperand::CreateReg(X86::BP);
512 indexReg = MCOperand::CreateReg(X86::DI);
515 indexReg = MCOperand::CreateReg(0);
516 switch (insn.eaBase) {
518 debug("Unexpected eaBase");
520 // Here, we will use the fill-ins defined above. However,
521 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
522 // sib and sib64 were handled in the top-level if, so they're only
523 // placeholders to keep the compiler happy.
526 baseReg = MCOperand::CreateReg(X86::x); break;
529 #define ENTRY(x) case EA_REG_##x:
532 debug("A R/M memory operand may not be a register; "
533 "the base field must be a base.");
538 scaleAmount = MCOperand::CreateImm(1);
541 displacement = MCOperand::CreateImm(insn.displacement);
543 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
545 mcInst.addOperand(baseReg);
546 mcInst.addOperand(scaleAmount);
547 mcInst.addOperand(indexReg);
548 if(!tryAddingSymbolicOperand(insn.displacement + pcrel, false,
549 insn.startLocation, insn.displacementOffset,
550 insn.displacementSize, mcInst, Dis))
551 mcInst.addOperand(displacement);
552 mcInst.addOperand(segmentReg);
556 /// translateRM - Translates an operand stored in the R/M (and possibly SIB)
557 /// byte of an instruction to LLVM form, and appends it to an MCInst.
559 /// @param mcInst - The MCInst to append to.
560 /// @param operand - The operand, as stored in the descriptor table.
561 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
563 /// @return - 0 on success; nonzero otherwise
564 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
565 InternalInstruction &insn, const MCDisassembler *Dis) {
566 switch (operand.type) {
568 debug("Unexpected type for a R/M operand");
588 case TYPE_CONTROLREG:
589 return translateRMRegister(mcInst, insn);
609 return translateRMMemory(mcInst, insn, Dis);
613 /// translateFPRegister - Translates a stack position on the FPU stack to its
614 /// LLVM form, and appends it to an MCInst.
616 /// @param mcInst - The MCInst to append to.
617 /// @param stackPos - The stack position to translate.
618 static void translateFPRegister(MCInst &mcInst,
620 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
623 /// translateMaskRegister - Translates a 3-bit mask register number to
624 /// LLVM form, and appends it to an MCInst.
626 /// @param mcInst - The MCInst to append to.
627 /// @param maskRegNum - Number of mask register from 0 to 7.
628 /// @return - false on success; true otherwise.
629 static bool translateMaskRegister(MCInst &mcInst,
630 uint8_t maskRegNum) {
631 if (maskRegNum >= 8) {
632 debug("Invalid mask register number");
636 mcInst.addOperand(MCOperand::CreateReg(X86::K0 + maskRegNum));
640 /// translateOperand - Translates an operand stored in an internal instruction
641 /// to LLVM's format and appends it to an MCInst.
643 /// @param mcInst - The MCInst to append to.
644 /// @param operand - The operand, as stored in the descriptor table.
645 /// @param insn - The internal instruction.
646 /// @return - false on success; true otherwise.
647 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
648 InternalInstruction &insn,
649 const MCDisassembler *Dis) {
650 switch (operand.encoding) {
652 debug("Unhandled operand encoding during translation");
655 translateRegister(mcInst, insn.reg);
657 case ENCODING_WRITEMASK:
658 return translateMaskRegister(mcInst, insn.writemask);
660 return translateRM(mcInst, operand, insn, Dis);
667 debug("Translation of code offsets isn't supported.");
675 translateImmediate(mcInst,
676 insn.immediates[insn.numImmediatesTranslated++],
686 translateRegister(mcInst, insn.opcodeRegister);
689 translateFPRegister(mcInst, insn.modRM & 7);
692 translateRegister(mcInst, insn.vvvv);
695 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],
700 /// translateInstruction - Translates an internal instruction and all its
701 /// operands to an MCInst.
703 /// @param mcInst - The MCInst to populate with the instruction's data.
704 /// @param insn - The internal instruction.
705 /// @return - false on success; true otherwise.
706 static bool translateInstruction(MCInst &mcInst,
707 InternalInstruction &insn,
708 const MCDisassembler *Dis) {
710 debug("Instruction has no specification");
714 mcInst.setOpcode(insn.instructionID);
715 // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3
716 // prefix bytes should be disassembled as xrelease and xacquire then set the
717 // opcode to those instead of the rep and repne opcodes.
718 if (insn.xAcquireRelease) {
719 if(mcInst.getOpcode() == X86::REP_PREFIX)
720 mcInst.setOpcode(X86::XRELEASE_PREFIX);
721 else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
722 mcInst.setOpcode(X86::XACQUIRE_PREFIX);
727 insn.numImmediatesTranslated = 0;
729 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
730 if (insn.operands[index].encoding != ENCODING_NONE) {
731 if (translateOperand(mcInst, insn.operands[index], insn, Dis)) {
740 static MCDisassembler *createX86_32Disassembler(const Target &T,
741 const MCSubtargetInfo &STI) {
742 return new X86Disassembler::X86GenericDisassembler(STI, MODE_32BIT,
743 T.createMCInstrInfo());
746 static MCDisassembler *createX86_64Disassembler(const Target &T,
747 const MCSubtargetInfo &STI) {
748 return new X86Disassembler::X86GenericDisassembler(STI, MODE_64BIT,
749 T.createMCInstrInfo());
752 extern "C" void LLVMInitializeX86Disassembler() {
753 // Register the disassembler.
754 TargetRegistry::RegisterMCDisassembler(TheX86_32Target,
755 createX86_32Disassembler);
756 TargetRegistry::RegisterMCDisassembler(TheX86_64Target,
757 createX86_64Disassembler);