1 /*===-- X86DisassemblerDecoder.c - Disassembler decoder ------------*- C -*-===*
3 * The LLVM Compiler Infrastructure
5 * This file is distributed under the University of Illinois Open Source
6 * License. See LICENSE.TXT for details.
8 *===----------------------------------------------------------------------===*
10 * This file is part of the X86 Disassembler.
11 * It contains the implementation of the instruction decoder.
12 * Documentation for the disassembler can be found in X86Disassembler.h.
14 *===----------------------------------------------------------------------===*/
16 #include <stdarg.h> /* for va_*() */
17 #include <stdio.h> /* for vsnprintf() */
18 #include <stdlib.h> /* for exit() */
19 #include <string.h> /* for memset() */
21 #include "X86DisassemblerDecoder.h"
23 #include "X86GenDisassemblerTables.inc"
31 #define debug(s) do { x86DisassemblerDebug(__FILE__, __LINE__, s); } while (0)
33 #define debug(s) do { } while (0)
38 * contextForAttrs - Client for the instruction context table. Takes a set of
39 * attributes and returns the appropriate decode context.
41 * @param attrMask - Attributes, from the enumeration attributeBits.
42 * @return - The InstructionContext to use when looking up an
43 * an instruction with these attributes.
45 static InstructionContext contextForAttrs(uint8_t attrMask) {
46 return CONTEXTS_SYM[attrMask];
50 * modRMRequired - Reads the appropriate instruction table to determine whether
51 * the ModR/M byte is required to decode a particular instruction.
53 * @param type - The opcode type (i.e., how many bytes it has).
54 * @param insnContext - The context for the instruction, as returned by
56 * @param opcode - The last byte of the instruction's opcode, not counting
57 * ModR/M extensions and escapes.
58 * @return - TRUE if the ModR/M byte is required, FALSE otherwise.
60 static int modRMRequired(OpcodeType type,
61 InstructionContext insnContext,
63 const struct ContextDecision* decision = 0;
67 decision = &ONEBYTE_SYM;
70 decision = &TWOBYTE_SYM;
73 decision = &THREEBYTE38_SYM;
76 decision = &THREEBYTE3A_SYM;
79 decision = &THREEBYTEA6_SYM;
82 decision = &THREEBYTEA7_SYM;
86 return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
87 modrm_type != MODRM_ONEENTRY;
91 * decode - Reads the appropriate instruction table to obtain the unique ID of
94 * @param type - See modRMRequired().
95 * @param insnContext - See modRMRequired().
96 * @param opcode - See modRMRequired().
97 * @param modRM - The ModR/M byte if required, or any value if not.
98 * @return - The UID of the instruction, or 0 on failure.
100 static InstrUID decode(OpcodeType type,
101 InstructionContext insnContext,
104 const struct ModRMDecision* dec = 0;
108 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
111 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
114 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
117 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
120 dec = &THREEBYTEA6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
123 dec = &THREEBYTEA7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
127 switch (dec->modrm_type) {
129 debug("Corrupt table! Unknown modrm_type");
132 return modRMTable[dec->instructionIDs];
134 if (modFromModRM(modRM) == 0x3)
135 return modRMTable[dec->instructionIDs+1];
136 return modRMTable[dec->instructionIDs];
138 if (modFromModRM(modRM) == 0x3)
139 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)+8];
140 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
141 case MODRM_SPLITMISC:
142 if (modFromModRM(modRM) == 0x3)
143 return modRMTable[dec->instructionIDs+(modRM & 0x3f)+8];
144 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
146 return modRMTable[dec->instructionIDs+modRM];
151 * specifierForUID - Given a UID, returns the name and operand specification for
154 * @param uid - The unique ID for the instruction. This should be returned by
155 * decode(); specifierForUID will not check bounds.
156 * @return - A pointer to the specification for that instruction.
158 static const struct InstructionSpecifier *specifierForUID(InstrUID uid) {
159 return &INSTRUCTIONS_SYM[uid];
163 * consumeByte - Uses the reader function provided by the user to consume one
164 * byte from the instruction's memory and advance the cursor.
166 * @param insn - The instruction with the reader function to use. The cursor
167 * for this instruction is advanced.
168 * @param byte - A pointer to a pre-allocated memory buffer to be populated
169 * with the data read.
170 * @return - 0 if the read was successful; nonzero otherwise.
172 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) {
173 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor);
176 ++(insn->readerCursor);
182 * lookAtByte - Like consumeByte, but does not advance the cursor.
184 * @param insn - See consumeByte().
185 * @param byte - See consumeByte().
186 * @return - See consumeByte().
188 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) {
189 return insn->reader(insn->readerArg, byte, insn->readerCursor);
192 static void unconsumeByte(struct InternalInstruction* insn) {
193 insn->readerCursor--;
196 #define CONSUME_FUNC(name, type) \
197 static int name(struct InternalInstruction* insn, type* ptr) { \
200 for (offset = 0; offset < sizeof(type); ++offset) { \
202 int ret = insn->reader(insn->readerArg, \
204 insn->readerCursor + offset); \
207 combined = combined | ((uint64_t)byte << (offset * 8)); \
210 insn->readerCursor += sizeof(type); \
215 * consume* - Use the reader function provided by the user to consume data
216 * values of various sizes from the instruction's memory and advance the
217 * cursor appropriately. These readers perform endian conversion.
219 * @param insn - See consumeByte().
220 * @param ptr - A pointer to a pre-allocated memory of appropriate size to
221 * be populated with the data read.
222 * @return - See consumeByte().
224 CONSUME_FUNC(consumeInt8, int8_t)
225 CONSUME_FUNC(consumeInt16, int16_t)
226 CONSUME_FUNC(consumeInt32, int32_t)
227 CONSUME_FUNC(consumeUInt16, uint16_t)
228 CONSUME_FUNC(consumeUInt32, uint32_t)
229 CONSUME_FUNC(consumeUInt64, uint64_t)
232 * dbgprintf - Uses the logging function provided by the user to log a single
233 * message, typically without a carriage-return.
235 * @param insn - The instruction containing the logging function.
236 * @param format - See printf().
237 * @param ... - See printf().
239 static void dbgprintf(struct InternalInstruction* insn,
248 va_start(ap, format);
249 (void)vsnprintf(buffer, sizeof(buffer), format, ap);
252 insn->dlog(insn->dlogArg, buffer);
258 * setPrefixPresent - Marks that a particular prefix is present at a particular
261 * @param insn - The instruction to be marked as having the prefix.
262 * @param prefix - The prefix that is present.
263 * @param location - The location where the prefix is located (in the address
264 * space of the instruction's reader).
266 static void setPrefixPresent(struct InternalInstruction* insn,
270 insn->prefixPresent[prefix] = 1;
271 insn->prefixLocations[prefix] = location;
275 * isPrefixAtLocation - Queries an instruction to determine whether a prefix is
276 * present at a given location.
278 * @param insn - The instruction to be queried.
279 * @param prefix - The prefix.
280 * @param location - The location to query.
281 * @return - Whether the prefix is at that location.
283 static BOOL isPrefixAtLocation(struct InternalInstruction* insn,
287 if (insn->prefixPresent[prefix] == 1 &&
288 insn->prefixLocations[prefix] == location)
295 * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the
296 * instruction as having them. Also sets the instruction's default operand,
297 * address, and other relevant data sizes to report operands correctly.
299 * @param insn - The instruction whose prefixes are to be read.
300 * @return - 0 if the instruction could be read until the end of the prefix
301 * bytes, and no prefixes conflicted; nonzero otherwise.
303 static int readPrefixes(struct InternalInstruction* insn) {
304 BOOL isPrefix = TRUE;
305 BOOL prefixGroups[4] = { FALSE };
306 uint64_t prefixLocation;
309 BOOL hasAdSize = FALSE;
310 BOOL hasOpSize = FALSE;
312 dbgprintf(insn, "readPrefixes()");
315 prefixLocation = insn->readerCursor;
317 if (consumeByte(insn, &byte))
321 * If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
322 * break and let it be disassembled as a normal "instruction".
324 if (insn->readerCursor - 1 == insn->startLocation
325 && (byte == 0xf0 || byte == 0xf2 || byte == 0xf3)) {
329 if (lookAtByte(insn, &nextByte))
332 * If the byte is 0xf2 or 0xf3, and any of the following conditions are
334 * - it is followed by a LOCK (0xf0) prefix
335 * - it is followed by an xchg instruction
336 * then it should be disassembled as a xacquire/xrelease not repne/rep.
338 if ((byte == 0xf2 || byte == 0xf3) &&
339 ((nextByte == 0xf0) |
340 ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90)))
341 insn->xAcquireRelease = TRUE;
343 * Also if the byte is 0xf3, and the following condition is met:
344 * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
345 * "mov mem, imm" (opcode 0xc6/0xc7) instructions.
346 * then it should be disassembled as an xrelease not rep.
349 (nextByte == 0x88 || nextByte == 0x89 ||
350 nextByte == 0xc6 || nextByte == 0xc7))
351 insn->xAcquireRelease = TRUE;
352 if (insn->mode == MODE_64BIT && (nextByte & 0xf0) == 0x40) {
353 if (consumeByte(insn, &nextByte))
355 if (lookAtByte(insn, &nextByte))
359 if (nextByte != 0x0f && nextByte != 0x90)
364 case 0xf0: /* LOCK */
365 case 0xf2: /* REPNE/REPNZ */
366 case 0xf3: /* REP or REPE/REPZ */
368 dbgprintf(insn, "Redundant Group 1 prefix");
369 prefixGroups[0] = TRUE;
370 setPrefixPresent(insn, byte, prefixLocation);
372 case 0x2e: /* CS segment override -OR- Branch not taken */
373 case 0x36: /* SS segment override -OR- Branch taken */
374 case 0x3e: /* DS segment override */
375 case 0x26: /* ES segment override */
376 case 0x64: /* FS segment override */
377 case 0x65: /* GS segment override */
380 insn->segmentOverride = SEG_OVERRIDE_CS;
383 insn->segmentOverride = SEG_OVERRIDE_SS;
386 insn->segmentOverride = SEG_OVERRIDE_DS;
389 insn->segmentOverride = SEG_OVERRIDE_ES;
392 insn->segmentOverride = SEG_OVERRIDE_FS;
395 insn->segmentOverride = SEG_OVERRIDE_GS;
398 debug("Unhandled override");
402 dbgprintf(insn, "Redundant Group 2 prefix");
403 prefixGroups[1] = TRUE;
404 setPrefixPresent(insn, byte, prefixLocation);
406 case 0x66: /* Operand-size override */
408 dbgprintf(insn, "Redundant Group 3 prefix");
409 prefixGroups[2] = TRUE;
411 setPrefixPresent(insn, byte, prefixLocation);
413 case 0x67: /* Address-size override */
415 dbgprintf(insn, "Redundant Group 4 prefix");
416 prefixGroups[3] = TRUE;
418 setPrefixPresent(insn, byte, prefixLocation);
420 default: /* Not a prefix byte */
426 dbgprintf(insn, "Found prefix 0x%hhx", byte);
434 if (lookAtByte(insn, &byte1)) {
435 dbgprintf(insn, "Couldn't read second byte of VEX");
439 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
441 insn->necessaryPrefixLocation = insn->readerCursor - 1;
445 insn->necessaryPrefixLocation = insn->readerCursor - 1;
448 if (insn->vexSize == 3) {
449 insn->vexPrefix[0] = byte;
450 consumeByte(insn, &insn->vexPrefix[1]);
451 consumeByte(insn, &insn->vexPrefix[2]);
453 /* We simulate the REX prefix for simplicity's sake */
455 if (insn->mode == MODE_64BIT) {
456 insn->rexPrefix = 0x40
457 | (wFromVEX3of3(insn->vexPrefix[2]) << 3)
458 | (rFromVEX2of3(insn->vexPrefix[1]) << 2)
459 | (xFromVEX2of3(insn->vexPrefix[1]) << 1)
460 | (bFromVEX2of3(insn->vexPrefix[1]) << 0);
463 switch (ppFromVEX3of3(insn->vexPrefix[2]))
472 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx", insn->vexPrefix[0], insn->vexPrefix[1], insn->vexPrefix[2]);
475 else if (byte == 0xc5) {
478 if (lookAtByte(insn, &byte1)) {
479 dbgprintf(insn, "Couldn't read second byte of VEX");
483 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
490 if (insn->vexSize == 2) {
491 insn->vexPrefix[0] = byte;
492 consumeByte(insn, &insn->vexPrefix[1]);
494 if (insn->mode == MODE_64BIT) {
495 insn->rexPrefix = 0x40
496 | (rFromVEX2of2(insn->vexPrefix[1]) << 2);
499 switch (ppFromVEX2of2(insn->vexPrefix[1]))
508 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx", insn->vexPrefix[0], insn->vexPrefix[1]);
512 if (insn->mode == MODE_64BIT) {
513 if ((byte & 0xf0) == 0x40) {
516 if (lookAtByte(insn, &opcodeByte) || ((opcodeByte & 0xf0) == 0x40)) {
517 dbgprintf(insn, "Redundant REX prefix");
521 insn->rexPrefix = byte;
522 insn->necessaryPrefixLocation = insn->readerCursor - 2;
524 dbgprintf(insn, "Found REX prefix 0x%hhx", byte);
527 insn->necessaryPrefixLocation = insn->readerCursor - 1;
531 insn->necessaryPrefixLocation = insn->readerCursor - 1;
535 if (insn->mode == MODE_16BIT) {
536 insn->registerSize = (hasOpSize ? 4 : 2);
537 insn->addressSize = (hasAdSize ? 4 : 2);
538 insn->displacementSize = (hasAdSize ? 4 : 2);
539 insn->immediateSize = (hasOpSize ? 4 : 2);
540 } else if (insn->mode == MODE_32BIT) {
541 insn->registerSize = (hasOpSize ? 2 : 4);
542 insn->addressSize = (hasAdSize ? 2 : 4);
543 insn->displacementSize = (hasAdSize ? 2 : 4);
544 insn->immediateSize = (hasOpSize ? 2 : 4);
545 } else if (insn->mode == MODE_64BIT) {
546 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
547 insn->registerSize = 8;
548 insn->addressSize = (hasAdSize ? 4 : 8);
549 insn->displacementSize = 4;
550 insn->immediateSize = 4;
551 } else if (insn->rexPrefix) {
552 insn->registerSize = (hasOpSize ? 2 : 4);
553 insn->addressSize = (hasAdSize ? 4 : 8);
554 insn->displacementSize = (hasOpSize ? 2 : 4);
555 insn->immediateSize = (hasOpSize ? 2 : 4);
557 insn->registerSize = (hasOpSize ? 2 : 4);
558 insn->addressSize = (hasAdSize ? 4 : 8);
559 insn->displacementSize = (hasOpSize ? 2 : 4);
560 insn->immediateSize = (hasOpSize ? 2 : 4);
568 * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of
569 * extended or escape opcodes).
571 * @param insn - The instruction whose opcode is to be read.
572 * @return - 0 if the opcode could be read successfully; nonzero otherwise.
574 static int readOpcode(struct InternalInstruction* insn) {
575 /* Determine the length of the primary opcode */
579 dbgprintf(insn, "readOpcode()");
581 insn->opcodeType = ONEBYTE;
583 if (insn->vexSize == 3)
585 switch (mmmmmFromVEX2of3(insn->vexPrefix[1]))
588 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)", mmmmmFromVEX2of3(insn->vexPrefix[1]));
593 insn->twoByteEscape = 0x0f;
594 insn->opcodeType = TWOBYTE;
595 return consumeByte(insn, &insn->opcode);
597 insn->twoByteEscape = 0x0f;
598 insn->threeByteEscape = 0x38;
599 insn->opcodeType = THREEBYTE_38;
600 return consumeByte(insn, &insn->opcode);
602 insn->twoByteEscape = 0x0f;
603 insn->threeByteEscape = 0x3a;
604 insn->opcodeType = THREEBYTE_3A;
605 return consumeByte(insn, &insn->opcode);
608 else if (insn->vexSize == 2)
610 insn->twoByteEscape = 0x0f;
611 insn->opcodeType = TWOBYTE;
612 return consumeByte(insn, &insn->opcode);
615 if (consumeByte(insn, ¤t))
618 if (current == 0x0f) {
619 dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current);
621 insn->twoByteEscape = current;
623 if (consumeByte(insn, ¤t))
626 if (current == 0x38) {
627 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
629 insn->threeByteEscape = current;
631 if (consumeByte(insn, ¤t))
634 insn->opcodeType = THREEBYTE_38;
635 } else if (current == 0x3a) {
636 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
638 insn->threeByteEscape = current;
640 if (consumeByte(insn, ¤t))
643 insn->opcodeType = THREEBYTE_3A;
644 } else if (current == 0xa6) {
645 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
647 insn->threeByteEscape = current;
649 if (consumeByte(insn, ¤t))
652 insn->opcodeType = THREEBYTE_A6;
653 } else if (current == 0xa7) {
654 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
656 insn->threeByteEscape = current;
658 if (consumeByte(insn, ¤t))
661 insn->opcodeType = THREEBYTE_A7;
663 dbgprintf(insn, "Didn't find a three-byte escape prefix");
665 insn->opcodeType = TWOBYTE;
670 * At this point we have consumed the full opcode.
671 * Anything we consume from here on must be unconsumed.
674 insn->opcode = current;
679 static int readModRM(struct InternalInstruction* insn);
682 * getIDWithAttrMask - Determines the ID of an instruction, consuming
683 * the ModR/M byte as appropriate for extended and escape opcodes,
684 * and using a supplied attribute mask.
686 * @param instructionID - A pointer whose target is filled in with the ID of the
688 * @param insn - The instruction whose ID is to be determined.
689 * @param attrMask - The attribute mask to search.
690 * @return - 0 if the ModR/M could be read when needed or was not
691 * needed; nonzero otherwise.
693 static int getIDWithAttrMask(uint16_t* instructionID,
694 struct InternalInstruction* insn,
696 BOOL hasModRMExtension;
698 uint8_t instructionClass;
700 instructionClass = contextForAttrs(attrMask);
702 hasModRMExtension = modRMRequired(insn->opcodeType,
706 if (hasModRMExtension) {
710 *instructionID = decode(insn->opcodeType,
715 *instructionID = decode(insn->opcodeType,
725 * is16BitEquivalent - Determines whether two instruction names refer to
726 * equivalent instructions but one is 16-bit whereas the other is not.
728 * @param orig - The instruction that is not 16-bit
729 * @param equiv - The instruction that is 16-bit
731 static BOOL is16BitEquivalent(const char* orig, const char* equiv) {
735 if (orig[i] == '\0' && equiv[i] == '\0')
737 if (orig[i] == '\0' || equiv[i] == '\0')
739 if (orig[i] != equiv[i]) {
740 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
742 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
744 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
752 * getID - Determines the ID of an instruction, consuming the ModR/M byte as
753 * appropriate for extended and escape opcodes. Determines the attributes and
754 * context for the instruction before doing so.
756 * @param insn - The instruction whose ID is to be determined.
757 * @return - 0 if the ModR/M could be read when needed or was not needed;
760 static int getID(struct InternalInstruction* insn, const void *miiArg) {
762 uint16_t instructionID;
764 dbgprintf(insn, "getID()");
766 attrMask = ATTR_NONE;
768 if (insn->mode == MODE_64BIT)
769 attrMask |= ATTR_64BIT;
772 attrMask |= ATTR_VEX;
774 if (insn->vexSize == 3) {
775 switch (ppFromVEX3of3(insn->vexPrefix[2])) {
777 attrMask |= ATTR_OPSIZE;
787 if (lFromVEX3of3(insn->vexPrefix[2]))
788 attrMask |= ATTR_VEXL;
790 else if (insn->vexSize == 2) {
791 switch (ppFromVEX2of2(insn->vexPrefix[1])) {
793 attrMask |= ATTR_OPSIZE;
803 if (lFromVEX2of2(insn->vexPrefix[1]))
804 attrMask |= ATTR_VEXL;
811 if (isPrefixAtLocation(insn, 0x66, insn->necessaryPrefixLocation))
812 attrMask |= ATTR_OPSIZE;
813 else if (isPrefixAtLocation(insn, 0x67, insn->necessaryPrefixLocation))
814 attrMask |= ATTR_ADSIZE;
815 else if (isPrefixAtLocation(insn, 0xf3, insn->necessaryPrefixLocation))
817 else if (isPrefixAtLocation(insn, 0xf2, insn->necessaryPrefixLocation))
821 if (insn->rexPrefix & 0x08)
822 attrMask |= ATTR_REXW;
824 if (getIDWithAttrMask(&instructionID, insn, attrMask))
827 /* The following clauses compensate for limitations of the tables. */
829 if ((attrMask & ATTR_VEXL) && (attrMask & ATTR_REXW) &&
830 !(attrMask & ATTR_OPSIZE)) {
832 * Some VEX instructions ignore the L-bit, but use the W-bit. Normally L-bit
833 * has precedence since there are no L-bit with W-bit entries in the tables.
834 * So if the L-bit isn't significant we should use the W-bit instead.
835 * We only need to do this if the instruction doesn't specify OpSize since
836 * there is a VEX_L_W_OPSIZE table.
839 const struct InstructionSpecifier *spec;
840 uint16_t instructionIDWithWBit;
841 const struct InstructionSpecifier *specWithWBit;
843 spec = specifierForUID(instructionID);
845 if (getIDWithAttrMask(&instructionIDWithWBit,
847 (attrMask & (~ATTR_VEXL)) | ATTR_REXW)) {
848 insn->instructionID = instructionID;
853 specWithWBit = specifierForUID(instructionIDWithWBit);
855 if (instructionID != instructionIDWithWBit) {
856 insn->instructionID = instructionIDWithWBit;
857 insn->spec = specWithWBit;
859 insn->instructionID = instructionID;
865 if (insn->prefixPresent[0x66] && !(attrMask & ATTR_OPSIZE)) {
867 * The instruction tables make no distinction between instructions that
868 * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
869 * particular spot (i.e., many MMX operations). In general we're
870 * conservative, but in the specific case where OpSize is present but not
871 * in the right place we check if there's a 16-bit operation.
874 const struct InstructionSpecifier *spec;
875 uint16_t instructionIDWithOpsize;
876 const char *specName, *specWithOpSizeName;
878 spec = specifierForUID(instructionID);
880 if (getIDWithAttrMask(&instructionIDWithOpsize,
882 attrMask | ATTR_OPSIZE)) {
884 * ModRM required with OpSize but not present; give up and return version
888 insn->instructionID = instructionID;
893 specName = x86DisassemblerGetInstrName(instructionID, miiArg);
895 x86DisassemblerGetInstrName(instructionIDWithOpsize, miiArg);
897 if (is16BitEquivalent(specName, specWithOpSizeName)) {
898 insn->instructionID = instructionIDWithOpsize;
899 insn->spec = specifierForUID(instructionIDWithOpsize);
901 insn->instructionID = instructionID;
907 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
908 insn->rexPrefix & 0x01) {
910 * NOOP shouldn't decode as NOOP if REX.b is set. Instead
911 * it should decode as XCHG %r8, %eax.
914 const struct InstructionSpecifier *spec;
915 uint16_t instructionIDWithNewOpcode;
916 const struct InstructionSpecifier *specWithNewOpcode;
918 spec = specifierForUID(instructionID);
920 /* Borrow opcode from one of the other XCHGar opcodes */
923 if (getIDWithAttrMask(&instructionIDWithNewOpcode,
928 insn->instructionID = instructionID;
933 specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode);
938 insn->instructionID = instructionIDWithNewOpcode;
939 insn->spec = specWithNewOpcode;
944 insn->instructionID = instructionID;
945 insn->spec = specifierForUID(insn->instructionID);
951 * readSIB - Consumes the SIB byte to determine addressing information for an
954 * @param insn - The instruction whose SIB byte is to be read.
955 * @return - 0 if the SIB byte was successfully read; nonzero otherwise.
957 static int readSIB(struct InternalInstruction* insn) {
958 SIBIndex sibIndexBase = 0;
959 SIBBase sibBaseBase = 0;
962 dbgprintf(insn, "readSIB()");
964 if (insn->consumedSIB)
967 insn->consumedSIB = TRUE;
969 switch (insn->addressSize) {
971 dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode");
975 sibIndexBase = SIB_INDEX_EAX;
976 sibBaseBase = SIB_BASE_EAX;
979 sibIndexBase = SIB_INDEX_RAX;
980 sibBaseBase = SIB_BASE_RAX;
984 if (consumeByte(insn, &insn->sib))
987 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3);
991 insn->sibIndex = SIB_INDEX_NONE;
994 insn->sibIndex = (SIBIndex)(sibIndexBase + index);
995 if (insn->sibIndex == SIB_INDEX_sib ||
996 insn->sibIndex == SIB_INDEX_sib64)
997 insn->sibIndex = SIB_INDEX_NONE;
1001 switch (scaleFromSIB(insn->sib)) {
1016 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3);
1020 switch (modFromModRM(insn->modRM)) {
1022 insn->eaDisplacement = EA_DISP_32;
1023 insn->sibBase = SIB_BASE_NONE;
1026 insn->eaDisplacement = EA_DISP_8;
1027 insn->sibBase = (insn->addressSize == 4 ?
1028 SIB_BASE_EBP : SIB_BASE_RBP);
1031 insn->eaDisplacement = EA_DISP_32;
1032 insn->sibBase = (insn->addressSize == 4 ?
1033 SIB_BASE_EBP : SIB_BASE_RBP);
1036 debug("Cannot have Mod = 0b11 and a SIB byte");
1041 insn->sibBase = (SIBBase)(sibBaseBase + base);
1049 * readDisplacement - Consumes the displacement of an instruction.
1051 * @param insn - The instruction whose displacement is to be read.
1052 * @return - 0 if the displacement byte was successfully read; nonzero
1055 static int readDisplacement(struct InternalInstruction* insn) {
1060 dbgprintf(insn, "readDisplacement()");
1062 if (insn->consumedDisplacement)
1065 insn->consumedDisplacement = TRUE;
1066 insn->displacementOffset = insn->readerCursor - insn->startLocation;
1068 switch (insn->eaDisplacement) {
1070 insn->consumedDisplacement = FALSE;
1073 if (consumeInt8(insn, &d8))
1075 insn->displacement = d8;
1078 if (consumeInt16(insn, &d16))
1080 insn->displacement = d16;
1083 if (consumeInt32(insn, &d32))
1085 insn->displacement = d32;
1089 insn->consumedDisplacement = TRUE;
1094 * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and
1095 * displacement) for an instruction and interprets it.
1097 * @param insn - The instruction whose addressing information is to be read.
1098 * @return - 0 if the information was successfully read; nonzero otherwise.
1100 static int readModRM(struct InternalInstruction* insn) {
1101 uint8_t mod, rm, reg;
1103 dbgprintf(insn, "readModRM()");
1105 if (insn->consumedModRM)
1108 if (consumeByte(insn, &insn->modRM))
1110 insn->consumedModRM = TRUE;
1112 mod = modFromModRM(insn->modRM);
1113 rm = rmFromModRM(insn->modRM);
1114 reg = regFromModRM(insn->modRM);
1117 * This goes by insn->registerSize to pick the correct register, which messes
1118 * up if we're using (say) XMM or 8-bit register operands. That gets fixed in
1121 switch (insn->registerSize) {
1123 insn->regBase = MODRM_REG_AX;
1124 insn->eaRegBase = EA_REG_AX;
1127 insn->regBase = MODRM_REG_EAX;
1128 insn->eaRegBase = EA_REG_EAX;
1131 insn->regBase = MODRM_REG_RAX;
1132 insn->eaRegBase = EA_REG_RAX;
1136 reg |= rFromREX(insn->rexPrefix) << 3;
1137 rm |= bFromREX(insn->rexPrefix) << 3;
1139 insn->reg = (Reg)(insn->regBase + reg);
1141 switch (insn->addressSize) {
1143 insn->eaBaseBase = EA_BASE_BX_SI;
1148 insn->eaBase = EA_BASE_NONE;
1149 insn->eaDisplacement = EA_DISP_16;
1150 if (readDisplacement(insn))
1153 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1154 insn->eaDisplacement = EA_DISP_NONE;
1158 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1159 insn->eaDisplacement = EA_DISP_8;
1160 if (readDisplacement(insn))
1164 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1165 insn->eaDisplacement = EA_DISP_16;
1166 if (readDisplacement(insn))
1170 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1171 if (readDisplacement(insn))
1178 insn->eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
1182 insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */
1185 case 0xc: /* in case REXW.b is set */
1186 insn->eaBase = (insn->addressSize == 4 ?
1187 EA_BASE_sib : EA_BASE_sib64);
1189 if (readDisplacement(insn))
1193 insn->eaBase = EA_BASE_NONE;
1194 insn->eaDisplacement = EA_DISP_32;
1195 if (readDisplacement(insn))
1199 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1205 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
1208 case 0xc: /* in case REXW.b is set */
1209 insn->eaBase = EA_BASE_sib;
1211 if (readDisplacement(insn))
1215 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1216 if (readDisplacement(insn))
1222 insn->eaDisplacement = EA_DISP_NONE;
1223 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1227 } /* switch (insn->addressSize) */
1232 #define GENERIC_FIXUP_FUNC(name, base, prefix) \
1233 static uint8_t name(struct InternalInstruction *insn, \
1240 debug("Unhandled register type"); \
1244 return base + index; \
1246 if (insn->rexPrefix && \
1247 index >= 4 && index <= 7) { \
1248 return prefix##_SPL + (index - 4); \
1250 return prefix##_AL + index; \
1253 return prefix##_AX + index; \
1255 return prefix##_EAX + index; \
1257 return prefix##_RAX + index; \
1259 return prefix##_YMM0 + index; \
1264 return prefix##_XMM0 + index; \
1270 return prefix##_MM0 + index; \
1271 case TYPE_SEGMENTREG: \
1274 return prefix##_ES + index; \
1275 case TYPE_DEBUGREG: \
1278 return prefix##_DR0 + index; \
1279 case TYPE_CONTROLREG: \
1282 return prefix##_CR0 + index; \
1287 * fixup*Value - Consults an operand type to determine the meaning of the
1288 * reg or R/M field. If the operand is an XMM operand, for example, an
1289 * operand would be XMM0 instead of AX, which readModRM() would otherwise
1290 * misinterpret it as.
1292 * @param insn - The instruction containing the operand.
1293 * @param type - The operand type.
1294 * @param index - The existing value of the field as reported by readModRM().
1295 * @param valid - The address of a uint8_t. The target is set to 1 if the
1296 * field is valid for the register class; 0 if not.
1297 * @return - The proper value.
1299 GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG)
1300 GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
1303 * fixupReg - Consults an operand specifier to determine which of the
1304 * fixup*Value functions to use in correcting readModRM()'ss interpretation.
1306 * @param insn - See fixup*Value().
1307 * @param op - The operand specifier.
1308 * @return - 0 if fixup was successful; -1 if the register returned was
1309 * invalid for its class.
1311 static int fixupReg(struct InternalInstruction *insn,
1312 const struct OperandSpecifier *op) {
1315 dbgprintf(insn, "fixupReg()");
1317 switch ((OperandEncoding)op->encoding) {
1319 debug("Expected a REG or R/M encoding in fixupReg");
1322 insn->vvvv = (Reg)fixupRegValue(insn,
1323 (OperandType)op->type,
1330 insn->reg = (Reg)fixupRegValue(insn,
1331 (OperandType)op->type,
1332 insn->reg - insn->regBase,
1338 if (insn->eaBase >= insn->eaRegBase) {
1339 insn->eaBase = (EABase)fixupRMValue(insn,
1340 (OperandType)op->type,
1341 insn->eaBase - insn->eaRegBase,
1353 * readOpcodeModifier - Reads an operand from the opcode field of an
1354 * instruction. Handles AddRegFrm instructions.
1356 * @param insn - The instruction whose opcode field is to be read.
1357 * @param inModRM - Indicates that the opcode field is to be read from the
1358 * ModR/M extension; useful for escape opcodes
1359 * @return - 0 on success; nonzero otherwise.
1361 static int readOpcodeModifier(struct InternalInstruction* insn) {
1362 dbgprintf(insn, "readOpcodeModifier()");
1364 if (insn->consumedOpcodeModifier)
1367 insn->consumedOpcodeModifier = TRUE;
1369 switch (insn->spec->modifierType) {
1371 debug("Unknown modifier type.");
1374 debug("No modifier but an operand expects one.");
1376 case MODIFIER_OPCODE:
1377 insn->opcodeModifier = insn->opcode - insn->spec->modifierBase;
1379 case MODIFIER_MODRM:
1380 insn->opcodeModifier = insn->modRM - insn->spec->modifierBase;
1386 * readOpcodeRegister - Reads an operand from the opcode field of an
1387 * instruction and interprets it appropriately given the operand width.
1388 * Handles AddRegFrm instructions.
1390 * @param insn - See readOpcodeModifier().
1391 * @param size - The width (in bytes) of the register being specified.
1392 * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1394 * @return - 0 on success; nonzero otherwise.
1396 static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
1397 dbgprintf(insn, "readOpcodeRegister()");
1399 if (readOpcodeModifier(insn))
1403 size = insn->registerSize;
1407 insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3)
1408 | insn->opcodeModifier));
1409 if (insn->rexPrefix &&
1410 insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1411 insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1412 insn->opcodeRegister = (Reg)(MODRM_REG_SPL
1413 + (insn->opcodeRegister - MODRM_REG_AL - 4));
1418 insn->opcodeRegister = (Reg)(MODRM_REG_AX
1419 + ((bFromREX(insn->rexPrefix) << 3)
1420 | insn->opcodeModifier));
1423 insn->opcodeRegister = (Reg)(MODRM_REG_EAX
1424 + ((bFromREX(insn->rexPrefix) << 3)
1425 | insn->opcodeModifier));
1428 insn->opcodeRegister = (Reg)(MODRM_REG_RAX
1429 + ((bFromREX(insn->rexPrefix) << 3)
1430 | insn->opcodeModifier));
1438 * readImmediate - Consumes an immediate operand from an instruction, given the
1439 * desired operand size.
1441 * @param insn - The instruction whose operand is to be read.
1442 * @param size - The width (in bytes) of the operand.
1443 * @return - 0 if the immediate was successfully consumed; nonzero
1446 static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
1452 dbgprintf(insn, "readImmediate()");
1454 if (insn->numImmediatesConsumed == 2) {
1455 debug("Already consumed two immediates");
1460 size = insn->immediateSize;
1462 insn->immediateSize = size;
1463 insn->immediateOffset = insn->readerCursor - insn->startLocation;
1467 if (consumeByte(insn, &imm8))
1469 insn->immediates[insn->numImmediatesConsumed] = imm8;
1472 if (consumeUInt16(insn, &imm16))
1474 insn->immediates[insn->numImmediatesConsumed] = imm16;
1477 if (consumeUInt32(insn, &imm32))
1479 insn->immediates[insn->numImmediatesConsumed] = imm32;
1482 if (consumeUInt64(insn, &imm64))
1484 insn->immediates[insn->numImmediatesConsumed] = imm64;
1488 insn->numImmediatesConsumed++;
1494 * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix.
1496 * @param insn - The instruction whose operand is to be read.
1497 * @return - 0 if the vvvv was successfully consumed; nonzero
1500 static int readVVVV(struct InternalInstruction* insn) {
1501 dbgprintf(insn, "readVVVV()");
1503 if (insn->vexSize == 3)
1504 insn->vvvv = vvvvFromVEX3of3(insn->vexPrefix[2]);
1505 else if (insn->vexSize == 2)
1506 insn->vvvv = vvvvFromVEX2of2(insn->vexPrefix[1]);
1510 if (insn->mode != MODE_64BIT)
1517 * readOperands - Consults the specifier for an instruction and consumes all
1518 * operands for that instruction, interpreting them as it goes.
1520 * @param insn - The instruction whose operands are to be read and interpreted.
1521 * @return - 0 if all operands could be read; nonzero otherwise.
1523 static int readOperands(struct InternalInstruction* insn) {
1525 int hasVVVV, needVVVV;
1528 dbgprintf(insn, "readOperands()");
1530 /* If non-zero vvvv specified, need to make sure one of the operands
1532 hasVVVV = !readVVVV(insn);
1533 needVVVV = hasVVVV && (insn->vvvv != 0);
1535 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
1536 switch (x86OperandSets[insn->spec->operands][index].encoding) {
1541 if (readModRM(insn))
1543 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1552 dbgprintf(insn, "We currently don't hande code-offset encodings");
1556 /* Saw a register immediate so don't read again and instead split the
1557 previous immediate. FIXME: This is a hack. */
1558 insn->immediates[insn->numImmediatesConsumed] =
1559 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1560 ++insn->numImmediatesConsumed;
1563 if (readImmediate(insn, 1))
1565 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM3 &&
1566 insn->immediates[insn->numImmediatesConsumed - 1] > 7)
1568 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM5 &&
1569 insn->immediates[insn->numImmediatesConsumed - 1] > 31)
1571 if (x86OperandSets[insn->spec->operands][index].type == TYPE_XMM128 ||
1572 x86OperandSets[insn->spec->operands][index].type == TYPE_XMM256)
1576 if (readImmediate(insn, 2))
1580 if (readImmediate(insn, 4))
1584 if (readImmediate(insn, 8))
1588 if (readImmediate(insn, insn->immediateSize))
1592 if (readImmediate(insn, insn->addressSize))
1596 if (readOpcodeRegister(insn, 1))
1600 if (readOpcodeRegister(insn, 2))
1604 if (readOpcodeRegister(insn, 4))
1608 if (readOpcodeRegister(insn, 8))
1612 if (readOpcodeRegister(insn, 0))
1616 if (readOpcodeModifier(insn))
1620 needVVVV = 0; /* Mark that we have found a VVVV operand. */
1623 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1629 dbgprintf(insn, "Encountered an operand with an unknown encoding.");
1634 /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */
1635 if (needVVVV) return -1;
1641 * decodeInstruction - Reads and interprets a full instruction provided by the
1644 * @param insn - A pointer to the instruction to be populated. Must be
1646 * @param reader - The function to be used to read the instruction's bytes.
1647 * @param readerArg - A generic argument to be passed to the reader to store
1648 * any internal state.
1649 * @param logger - If non-NULL, the function to be used to write log messages
1651 * @param loggerArg - A generic argument to be passed to the logger to store
1652 * any internal state.
1653 * @param startLoc - The address (in the reader's address space) of the first
1654 * byte in the instruction.
1655 * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to
1656 * decode the instruction in.
1657 * @return - 0 if the instruction's memory could be read; nonzero if
1660 int decodeInstruction(struct InternalInstruction* insn,
1661 byteReader_t reader,
1662 const void* readerArg,
1667 DisassemblerMode mode) {
1668 memset(insn, 0, sizeof(struct InternalInstruction));
1670 insn->reader = reader;
1671 insn->readerArg = readerArg;
1672 insn->dlog = logger;
1673 insn->dlogArg = loggerArg;
1674 insn->startLocation = startLoc;
1675 insn->readerCursor = startLoc;
1677 insn->numImmediatesConsumed = 0;
1679 if (readPrefixes(insn) ||
1681 getID(insn, miiArg) ||
1682 insn->instructionID == 0 ||
1686 insn->operands = &x86OperandSets[insn->spec->operands][0];
1688 insn->length = insn->readerCursor - insn->startLocation;
1690 dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu",
1691 startLoc, insn->readerCursor, insn->length);
1693 if (insn->length > 15)
1694 dbgprintf(insn, "Instruction exceeds 15-byte limit");