1 /*===-- X86DisassemblerDecoder.c - Disassembler decoder ------------*- C -*-===*
3 * The LLVM Compiler Infrastructure
5 * This file is distributed under the University of Illinois Open Source
6 * License. See LICENSE.TXT for details.
8 *===----------------------------------------------------------------------===*
10 * This file is part of the X86 Disassembler.
11 * It contains the implementation of the instruction decoder.
12 * Documentation for the disassembler can be found in X86Disassembler.h.
14 *===----------------------------------------------------------------------===*/
16 #include <stdarg.h> /* for va_*() */
17 #include <stdio.h> /* for vsnprintf() */
18 #include <stdlib.h> /* for exit() */
19 #include <string.h> /* for memset() */
21 #include "X86DisassemblerDecoder.h"
23 #include "X86GenDisassemblerTables.inc"
31 #define debug(s) do { x86DisassemblerDebug(__FILE__, __LINE__, s); } while (0)
33 #define debug(s) do { } while (0)
38 * contextForAttrs - Client for the instruction context table. Takes a set of
39 * attributes and returns the appropriate decode context.
41 * @param attrMask - Attributes, from the enumeration attributeBits.
42 * @return - The InstructionContext to use when looking up an
43 * an instruction with these attributes.
45 static InstructionContext contextForAttrs(uint8_t attrMask) {
46 return CONTEXTS_SYM[attrMask];
50 * modRMRequired - Reads the appropriate instruction table to determine whether
51 * the ModR/M byte is required to decode a particular instruction.
53 * @param type - The opcode type (i.e., how many bytes it has).
54 * @param insnContext - The context for the instruction, as returned by
56 * @param opcode - The last byte of the instruction's opcode, not counting
57 * ModR/M extensions and escapes.
58 * @return - TRUE if the ModR/M byte is required, FALSE otherwise.
60 static int modRMRequired(OpcodeType type,
61 InstructionContext insnContext,
63 const struct ContextDecision* decision = 0;
67 decision = &ONEBYTE_SYM;
70 decision = &TWOBYTE_SYM;
73 decision = &THREEBYTE38_SYM;
76 decision = &THREEBYTE3A_SYM;
79 decision = &THREEBYTEA6_SYM;
82 decision = &THREEBYTEA7_SYM;
86 return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
87 modrm_type != MODRM_ONEENTRY;
91 * decode - Reads the appropriate instruction table to obtain the unique ID of
94 * @param type - See modRMRequired().
95 * @param insnContext - See modRMRequired().
96 * @param opcode - See modRMRequired().
97 * @param modRM - The ModR/M byte if required, or any value if not.
98 * @return - The UID of the instruction, or 0 on failure.
100 static InstrUID decode(OpcodeType type,
101 InstructionContext insnContext,
104 const struct ModRMDecision* dec = 0;
108 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
111 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
114 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
117 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
120 dec = &THREEBYTEA6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
123 dec = &THREEBYTEA7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
127 switch (dec->modrm_type) {
129 debug("Corrupt table! Unknown modrm_type");
132 return modRMTable[dec->instructionIDs];
134 if (modFromModRM(modRM) == 0x3)
135 return modRMTable[dec->instructionIDs+1];
136 return modRMTable[dec->instructionIDs];
138 if (modFromModRM(modRM) == 0x3)
139 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)+8];
140 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
141 case MODRM_SPLITMISC:
142 if (modFromModRM(modRM) == 0x3)
143 return modRMTable[dec->instructionIDs+(modRM & 0x3f)+8];
144 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
146 return modRMTable[dec->instructionIDs+modRM];
151 * specifierForUID - Given a UID, returns the name and operand specification for
154 * @param uid - The unique ID for the instruction. This should be returned by
155 * decode(); specifierForUID will not check bounds.
156 * @return - A pointer to the specification for that instruction.
158 static const struct InstructionSpecifier *specifierForUID(InstrUID uid) {
159 return &INSTRUCTIONS_SYM[uid];
163 * consumeByte - Uses the reader function provided by the user to consume one
164 * byte from the instruction's memory and advance the cursor.
166 * @param insn - The instruction with the reader function to use. The cursor
167 * for this instruction is advanced.
168 * @param byte - A pointer to a pre-allocated memory buffer to be populated
169 * with the data read.
170 * @return - 0 if the read was successful; nonzero otherwise.
172 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) {
173 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor);
176 ++(insn->readerCursor);
182 * lookAtByte - Like consumeByte, but does not advance the cursor.
184 * @param insn - See consumeByte().
185 * @param byte - See consumeByte().
186 * @return - See consumeByte().
188 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) {
189 return insn->reader(insn->readerArg, byte, insn->readerCursor);
192 static void unconsumeByte(struct InternalInstruction* insn) {
193 insn->readerCursor--;
196 #define CONSUME_FUNC(name, type) \
197 static int name(struct InternalInstruction* insn, type* ptr) { \
200 for (offset = 0; offset < sizeof(type); ++offset) { \
202 int ret = insn->reader(insn->readerArg, \
204 insn->readerCursor + offset); \
207 combined = combined | ((uint64_t)byte << (offset * 8)); \
210 insn->readerCursor += sizeof(type); \
215 * consume* - Use the reader function provided by the user to consume data
216 * values of various sizes from the instruction's memory and advance the
217 * cursor appropriately. These readers perform endian conversion.
219 * @param insn - See consumeByte().
220 * @param ptr - A pointer to a pre-allocated memory of appropriate size to
221 * be populated with the data read.
222 * @return - See consumeByte().
224 CONSUME_FUNC(consumeInt8, int8_t)
225 CONSUME_FUNC(consumeInt16, int16_t)
226 CONSUME_FUNC(consumeInt32, int32_t)
227 CONSUME_FUNC(consumeUInt16, uint16_t)
228 CONSUME_FUNC(consumeUInt32, uint32_t)
229 CONSUME_FUNC(consumeUInt64, uint64_t)
232 * dbgprintf - Uses the logging function provided by the user to log a single
233 * message, typically without a carriage-return.
235 * @param insn - The instruction containing the logging function.
236 * @param format - See printf().
237 * @param ... - See printf().
239 static void dbgprintf(struct InternalInstruction* insn,
248 va_start(ap, format);
249 (void)vsnprintf(buffer, sizeof(buffer), format, ap);
252 insn->dlog(insn->dlogArg, buffer);
258 * setPrefixPresent - Marks that a particular prefix is present at a particular
261 * @param insn - The instruction to be marked as having the prefix.
262 * @param prefix - The prefix that is present.
263 * @param location - The location where the prefix is located (in the address
264 * space of the instruction's reader).
266 static void setPrefixPresent(struct InternalInstruction* insn,
270 insn->prefixPresent[prefix] = 1;
271 insn->prefixLocations[prefix] = location;
275 * isPrefixAtLocation - Queries an instruction to determine whether a prefix is
276 * present at a given location.
278 * @param insn - The instruction to be queried.
279 * @param prefix - The prefix.
280 * @param location - The location to query.
281 * @return - Whether the prefix is at that location.
283 static BOOL isPrefixAtLocation(struct InternalInstruction* insn,
287 if (insn->prefixPresent[prefix] == 1 &&
288 insn->prefixLocations[prefix] == location)
295 * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the
296 * instruction as having them. Also sets the instruction's default operand,
297 * address, and other relevant data sizes to report operands correctly.
299 * @param insn - The instruction whose prefixes are to be read.
300 * @return - 0 if the instruction could be read until the end of the prefix
301 * bytes, and no prefixes conflicted; nonzero otherwise.
303 static int readPrefixes(struct InternalInstruction* insn) {
304 BOOL isPrefix = TRUE;
305 BOOL prefixGroups[4] = { FALSE };
306 uint64_t prefixLocation;
309 BOOL hasAdSize = FALSE;
310 BOOL hasOpSize = FALSE;
312 dbgprintf(insn, "readPrefixes()");
315 prefixLocation = insn->readerCursor;
317 if (consumeByte(insn, &byte))
321 * If the first byte is a LOCK prefix break and let it be disassembled
322 * as a lock "instruction", by creating an <MCInst #xxxx LOCK_PREFIX>.
323 * FIXME there is currently no way to get the disassembler to print the
324 * lock prefix if it is not the first byte.
326 if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0)
330 case 0xf0: /* LOCK */
331 case 0xf2: /* REPNE/REPNZ */
332 case 0xf3: /* REP or REPE/REPZ */
334 dbgprintf(insn, "Redundant Group 1 prefix");
335 prefixGroups[0] = TRUE;
336 setPrefixPresent(insn, byte, prefixLocation);
338 case 0x2e: /* CS segment override -OR- Branch not taken */
339 case 0x36: /* SS segment override -OR- Branch taken */
340 case 0x3e: /* DS segment override */
341 case 0x26: /* ES segment override */
342 case 0x64: /* FS segment override */
343 case 0x65: /* GS segment override */
346 insn->segmentOverride = SEG_OVERRIDE_CS;
349 insn->segmentOverride = SEG_OVERRIDE_SS;
352 insn->segmentOverride = SEG_OVERRIDE_DS;
355 insn->segmentOverride = SEG_OVERRIDE_ES;
358 insn->segmentOverride = SEG_OVERRIDE_FS;
361 insn->segmentOverride = SEG_OVERRIDE_GS;
364 debug("Unhandled override");
368 dbgprintf(insn, "Redundant Group 2 prefix");
369 prefixGroups[1] = TRUE;
370 setPrefixPresent(insn, byte, prefixLocation);
372 case 0x66: /* Operand-size override */
374 dbgprintf(insn, "Redundant Group 3 prefix");
375 prefixGroups[2] = TRUE;
377 setPrefixPresent(insn, byte, prefixLocation);
379 case 0x67: /* Address-size override */
381 dbgprintf(insn, "Redundant Group 4 prefix");
382 prefixGroups[3] = TRUE;
384 setPrefixPresent(insn, byte, prefixLocation);
386 default: /* Not a prefix byte */
392 dbgprintf(insn, "Found prefix 0x%hhx", byte);
400 if (lookAtByte(insn, &byte1)) {
401 dbgprintf(insn, "Couldn't read second byte of VEX");
405 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
407 insn->necessaryPrefixLocation = insn->readerCursor - 1;
411 insn->necessaryPrefixLocation = insn->readerCursor - 1;
414 if (insn->vexSize == 3) {
415 insn->vexPrefix[0] = byte;
416 consumeByte(insn, &insn->vexPrefix[1]);
417 consumeByte(insn, &insn->vexPrefix[2]);
419 /* We simulate the REX prefix for simplicity's sake */
421 if (insn->mode == MODE_64BIT) {
422 insn->rexPrefix = 0x40
423 | (wFromVEX3of3(insn->vexPrefix[2]) << 3)
424 | (rFromVEX2of3(insn->vexPrefix[1]) << 2)
425 | (xFromVEX2of3(insn->vexPrefix[1]) << 1)
426 | (bFromVEX2of3(insn->vexPrefix[1]) << 0);
429 switch (ppFromVEX3of3(insn->vexPrefix[2]))
438 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx", insn->vexPrefix[0], insn->vexPrefix[1], insn->vexPrefix[2]);
441 else if (byte == 0xc5) {
444 if (lookAtByte(insn, &byte1)) {
445 dbgprintf(insn, "Couldn't read second byte of VEX");
449 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
456 if (insn->vexSize == 2) {
457 insn->vexPrefix[0] = byte;
458 consumeByte(insn, &insn->vexPrefix[1]);
460 if (insn->mode == MODE_64BIT) {
461 insn->rexPrefix = 0x40
462 | (rFromVEX2of2(insn->vexPrefix[1]) << 2);
465 switch (ppFromVEX2of2(insn->vexPrefix[1]))
474 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx", insn->vexPrefix[0], insn->vexPrefix[1]);
478 if (insn->mode == MODE_64BIT) {
479 if ((byte & 0xf0) == 0x40) {
482 if (lookAtByte(insn, &opcodeByte) || ((opcodeByte & 0xf0) == 0x40)) {
483 dbgprintf(insn, "Redundant REX prefix");
487 insn->rexPrefix = byte;
488 insn->necessaryPrefixLocation = insn->readerCursor - 2;
490 dbgprintf(insn, "Found REX prefix 0x%hhx", byte);
493 insn->necessaryPrefixLocation = insn->readerCursor - 1;
497 insn->necessaryPrefixLocation = insn->readerCursor - 1;
501 if (insn->mode == MODE_16BIT) {
502 insn->registerSize = (hasOpSize ? 4 : 2);
503 insn->addressSize = (hasAdSize ? 4 : 2);
504 insn->displacementSize = (hasAdSize ? 4 : 2);
505 insn->immediateSize = (hasOpSize ? 4 : 2);
506 } else if (insn->mode == MODE_32BIT) {
507 insn->registerSize = (hasOpSize ? 2 : 4);
508 insn->addressSize = (hasAdSize ? 2 : 4);
509 insn->displacementSize = (hasAdSize ? 2 : 4);
510 insn->immediateSize = (hasOpSize ? 2 : 4);
511 } else if (insn->mode == MODE_64BIT) {
512 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
513 insn->registerSize = 8;
514 insn->addressSize = (hasAdSize ? 4 : 8);
515 insn->displacementSize = 4;
516 insn->immediateSize = 4;
517 } else if (insn->rexPrefix) {
518 insn->registerSize = (hasOpSize ? 2 : 4);
519 insn->addressSize = (hasAdSize ? 4 : 8);
520 insn->displacementSize = (hasOpSize ? 2 : 4);
521 insn->immediateSize = (hasOpSize ? 2 : 4);
523 insn->registerSize = (hasOpSize ? 2 : 4);
524 insn->addressSize = (hasAdSize ? 4 : 8);
525 insn->displacementSize = (hasOpSize ? 2 : 4);
526 insn->immediateSize = (hasOpSize ? 2 : 4);
534 * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of
535 * extended or escape opcodes).
537 * @param insn - The instruction whose opcode is to be read.
538 * @return - 0 if the opcode could be read successfully; nonzero otherwise.
540 static int readOpcode(struct InternalInstruction* insn) {
541 /* Determine the length of the primary opcode */
545 dbgprintf(insn, "readOpcode()");
547 insn->opcodeType = ONEBYTE;
549 if (insn->vexSize == 3)
551 switch (mmmmmFromVEX2of3(insn->vexPrefix[1]))
554 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)", mmmmmFromVEX2of3(insn->vexPrefix[1]));
559 insn->twoByteEscape = 0x0f;
560 insn->opcodeType = TWOBYTE;
561 return consumeByte(insn, &insn->opcode);
563 insn->twoByteEscape = 0x0f;
564 insn->threeByteEscape = 0x38;
565 insn->opcodeType = THREEBYTE_38;
566 return consumeByte(insn, &insn->opcode);
568 insn->twoByteEscape = 0x0f;
569 insn->threeByteEscape = 0x3a;
570 insn->opcodeType = THREEBYTE_3A;
571 return consumeByte(insn, &insn->opcode);
574 else if (insn->vexSize == 2)
576 insn->twoByteEscape = 0x0f;
577 insn->opcodeType = TWOBYTE;
578 return consumeByte(insn, &insn->opcode);
581 if (consumeByte(insn, ¤t))
584 if (current == 0x0f) {
585 dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current);
587 insn->twoByteEscape = current;
589 if (consumeByte(insn, ¤t))
592 if (current == 0x38) {
593 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
595 insn->threeByteEscape = current;
597 if (consumeByte(insn, ¤t))
600 insn->opcodeType = THREEBYTE_38;
601 } else if (current == 0x3a) {
602 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
604 insn->threeByteEscape = current;
606 if (consumeByte(insn, ¤t))
609 insn->opcodeType = THREEBYTE_3A;
610 } else if (current == 0xa6) {
611 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
613 insn->threeByteEscape = current;
615 if (consumeByte(insn, ¤t))
618 insn->opcodeType = THREEBYTE_A6;
619 } else if (current == 0xa7) {
620 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
622 insn->threeByteEscape = current;
624 if (consumeByte(insn, ¤t))
627 insn->opcodeType = THREEBYTE_A7;
629 dbgprintf(insn, "Didn't find a three-byte escape prefix");
631 insn->opcodeType = TWOBYTE;
636 * At this point we have consumed the full opcode.
637 * Anything we consume from here on must be unconsumed.
640 insn->opcode = current;
645 static int readModRM(struct InternalInstruction* insn);
648 * getIDWithAttrMask - Determines the ID of an instruction, consuming
649 * the ModR/M byte as appropriate for extended and escape opcodes,
650 * and using a supplied attribute mask.
652 * @param instructionID - A pointer whose target is filled in with the ID of the
654 * @param insn - The instruction whose ID is to be determined.
655 * @param attrMask - The attribute mask to search.
656 * @return - 0 if the ModR/M could be read when needed or was not
657 * needed; nonzero otherwise.
659 static int getIDWithAttrMask(uint16_t* instructionID,
660 struct InternalInstruction* insn,
662 BOOL hasModRMExtension;
664 uint8_t instructionClass;
666 instructionClass = contextForAttrs(attrMask);
668 hasModRMExtension = modRMRequired(insn->opcodeType,
672 if (hasModRMExtension) {
676 *instructionID = decode(insn->opcodeType,
681 *instructionID = decode(insn->opcodeType,
691 * is16BitEquivalent - Determines whether two instruction names refer to
692 * equivalent instructions but one is 16-bit whereas the other is not.
694 * @param orig - The instruction that is not 16-bit
695 * @param equiv - The instruction that is 16-bit
697 static BOOL is16BitEquivalent(const char* orig, const char* equiv) {
701 if (orig[i] == '\0' && equiv[i] == '\0')
703 if (orig[i] == '\0' || equiv[i] == '\0')
705 if (orig[i] != equiv[i]) {
706 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
708 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
710 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
718 * getID - Determines the ID of an instruction, consuming the ModR/M byte as
719 * appropriate for extended and escape opcodes. Determines the attributes and
720 * context for the instruction before doing so.
722 * @param insn - The instruction whose ID is to be determined.
723 * @return - 0 if the ModR/M could be read when needed or was not needed;
726 static int getID(struct InternalInstruction* insn, const void *miiArg) {
728 uint16_t instructionID;
730 dbgprintf(insn, "getID()");
732 attrMask = ATTR_NONE;
734 if (insn->mode == MODE_64BIT)
735 attrMask |= ATTR_64BIT;
738 attrMask |= ATTR_VEX;
740 if (insn->vexSize == 3) {
741 switch (ppFromVEX3of3(insn->vexPrefix[2])) {
743 attrMask |= ATTR_OPSIZE;
753 if (lFromVEX3of3(insn->vexPrefix[2]))
754 attrMask |= ATTR_VEXL;
756 else if (insn->vexSize == 2) {
757 switch (ppFromVEX2of2(insn->vexPrefix[1])) {
759 attrMask |= ATTR_OPSIZE;
769 if (lFromVEX2of2(insn->vexPrefix[1]))
770 attrMask |= ATTR_VEXL;
777 if (isPrefixAtLocation(insn, 0x66, insn->necessaryPrefixLocation))
778 attrMask |= ATTR_OPSIZE;
779 else if (isPrefixAtLocation(insn, 0x67, insn->necessaryPrefixLocation))
780 attrMask |= ATTR_ADSIZE;
781 else if (isPrefixAtLocation(insn, 0xf3, insn->necessaryPrefixLocation))
783 else if (isPrefixAtLocation(insn, 0xf2, insn->necessaryPrefixLocation))
787 if (insn->rexPrefix & 0x08)
788 attrMask |= ATTR_REXW;
790 if (getIDWithAttrMask(&instructionID, insn, attrMask))
793 /* The following clauses compensate for limitations of the tables. */
795 if ((attrMask & ATTR_VEXL) && (attrMask & ATTR_REXW) &&
796 !(attrMask & ATTR_OPSIZE)) {
798 * Some VEX instructions ignore the L-bit, but use the W-bit. Normally L-bit
799 * has precedence since there are no L-bit with W-bit entries in the tables.
800 * So if the L-bit isn't significant we should use the W-bit instead.
801 * We only need to do this if the instruction doesn't specify OpSize since
802 * there is a VEX_L_W_OPSIZE table.
805 const struct InstructionSpecifier *spec;
806 uint16_t instructionIDWithWBit;
807 const struct InstructionSpecifier *specWithWBit;
809 spec = specifierForUID(instructionID);
811 if (getIDWithAttrMask(&instructionIDWithWBit,
813 (attrMask & (~ATTR_VEXL)) | ATTR_REXW)) {
814 insn->instructionID = instructionID;
819 specWithWBit = specifierForUID(instructionIDWithWBit);
821 if (instructionID != instructionIDWithWBit) {
822 insn->instructionID = instructionIDWithWBit;
823 insn->spec = specWithWBit;
825 insn->instructionID = instructionID;
831 if (insn->prefixPresent[0x66] && !(attrMask & ATTR_OPSIZE)) {
833 * The instruction tables make no distinction between instructions that
834 * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
835 * particular spot (i.e., many MMX operations). In general we're
836 * conservative, but in the specific case where OpSize is present but not
837 * in the right place we check if there's a 16-bit operation.
840 const struct InstructionSpecifier *spec;
841 uint16_t instructionIDWithOpsize;
842 const char *specName, *specWithOpSizeName;
844 spec = specifierForUID(instructionID);
846 if (getIDWithAttrMask(&instructionIDWithOpsize,
848 attrMask | ATTR_OPSIZE)) {
850 * ModRM required with OpSize but not present; give up and return version
854 insn->instructionID = instructionID;
859 specName = x86DisassemblerGetInstrName(instructionID, miiArg);
861 x86DisassemblerGetInstrName(instructionIDWithOpsize, miiArg);
863 if (is16BitEquivalent(specName, specWithOpSizeName)) {
864 insn->instructionID = instructionIDWithOpsize;
865 insn->spec = specifierForUID(instructionIDWithOpsize);
867 insn->instructionID = instructionID;
873 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
874 insn->rexPrefix & 0x01) {
876 * NOOP shouldn't decode as NOOP if REX.b is set. Instead
877 * it should decode as XCHG %r8, %eax.
880 const struct InstructionSpecifier *spec;
881 uint16_t instructionIDWithNewOpcode;
882 const struct InstructionSpecifier *specWithNewOpcode;
884 spec = specifierForUID(instructionID);
886 /* Borrow opcode from one of the other XCHGar opcodes */
889 if (getIDWithAttrMask(&instructionIDWithNewOpcode,
894 insn->instructionID = instructionID;
899 specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode);
904 insn->instructionID = instructionIDWithNewOpcode;
905 insn->spec = specWithNewOpcode;
910 insn->instructionID = instructionID;
911 insn->spec = specifierForUID(insn->instructionID);
917 * readSIB - Consumes the SIB byte to determine addressing information for an
920 * @param insn - The instruction whose SIB byte is to be read.
921 * @return - 0 if the SIB byte was successfully read; nonzero otherwise.
923 static int readSIB(struct InternalInstruction* insn) {
924 SIBIndex sibIndexBase = 0;
925 SIBBase sibBaseBase = 0;
928 dbgprintf(insn, "readSIB()");
930 if (insn->consumedSIB)
933 insn->consumedSIB = TRUE;
935 switch (insn->addressSize) {
937 dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode");
941 sibIndexBase = SIB_INDEX_EAX;
942 sibBaseBase = SIB_BASE_EAX;
945 sibIndexBase = SIB_INDEX_RAX;
946 sibBaseBase = SIB_BASE_RAX;
950 if (consumeByte(insn, &insn->sib))
953 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3);
957 insn->sibIndex = SIB_INDEX_NONE;
960 insn->sibIndex = (SIBIndex)(sibIndexBase + index);
961 if (insn->sibIndex == SIB_INDEX_sib ||
962 insn->sibIndex == SIB_INDEX_sib64)
963 insn->sibIndex = SIB_INDEX_NONE;
967 switch (scaleFromSIB(insn->sib)) {
982 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3);
986 switch (modFromModRM(insn->modRM)) {
988 insn->eaDisplacement = EA_DISP_32;
989 insn->sibBase = SIB_BASE_NONE;
992 insn->eaDisplacement = EA_DISP_8;
993 insn->sibBase = (insn->addressSize == 4 ?
994 SIB_BASE_EBP : SIB_BASE_RBP);
997 insn->eaDisplacement = EA_DISP_32;
998 insn->sibBase = (insn->addressSize == 4 ?
999 SIB_BASE_EBP : SIB_BASE_RBP);
1002 debug("Cannot have Mod = 0b11 and a SIB byte");
1007 insn->sibBase = (SIBBase)(sibBaseBase + base);
1015 * readDisplacement - Consumes the displacement of an instruction.
1017 * @param insn - The instruction whose displacement is to be read.
1018 * @return - 0 if the displacement byte was successfully read; nonzero
1021 static int readDisplacement(struct InternalInstruction* insn) {
1026 dbgprintf(insn, "readDisplacement()");
1028 if (insn->consumedDisplacement)
1031 insn->consumedDisplacement = TRUE;
1032 insn->displacementOffset = insn->readerCursor - insn->startLocation;
1034 switch (insn->eaDisplacement) {
1036 insn->consumedDisplacement = FALSE;
1039 if (consumeInt8(insn, &d8))
1041 insn->displacement = d8;
1044 if (consumeInt16(insn, &d16))
1046 insn->displacement = d16;
1049 if (consumeInt32(insn, &d32))
1051 insn->displacement = d32;
1055 insn->consumedDisplacement = TRUE;
1060 * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and
1061 * displacement) for an instruction and interprets it.
1063 * @param insn - The instruction whose addressing information is to be read.
1064 * @return - 0 if the information was successfully read; nonzero otherwise.
1066 static int readModRM(struct InternalInstruction* insn) {
1067 uint8_t mod, rm, reg;
1069 dbgprintf(insn, "readModRM()");
1071 if (insn->consumedModRM)
1074 if (consumeByte(insn, &insn->modRM))
1076 insn->consumedModRM = TRUE;
1078 mod = modFromModRM(insn->modRM);
1079 rm = rmFromModRM(insn->modRM);
1080 reg = regFromModRM(insn->modRM);
1083 * This goes by insn->registerSize to pick the correct register, which messes
1084 * up if we're using (say) XMM or 8-bit register operands. That gets fixed in
1087 switch (insn->registerSize) {
1089 insn->regBase = MODRM_REG_AX;
1090 insn->eaRegBase = EA_REG_AX;
1093 insn->regBase = MODRM_REG_EAX;
1094 insn->eaRegBase = EA_REG_EAX;
1097 insn->regBase = MODRM_REG_RAX;
1098 insn->eaRegBase = EA_REG_RAX;
1102 reg |= rFromREX(insn->rexPrefix) << 3;
1103 rm |= bFromREX(insn->rexPrefix) << 3;
1105 insn->reg = (Reg)(insn->regBase + reg);
1107 switch (insn->addressSize) {
1109 insn->eaBaseBase = EA_BASE_BX_SI;
1114 insn->eaBase = EA_BASE_NONE;
1115 insn->eaDisplacement = EA_DISP_16;
1116 if (readDisplacement(insn))
1119 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1120 insn->eaDisplacement = EA_DISP_NONE;
1124 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1125 insn->eaDisplacement = EA_DISP_8;
1126 if (readDisplacement(insn))
1130 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1131 insn->eaDisplacement = EA_DISP_16;
1132 if (readDisplacement(insn))
1136 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1137 if (readDisplacement(insn))
1144 insn->eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
1148 insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */
1151 case 0xc: /* in case REXW.b is set */
1152 insn->eaBase = (insn->addressSize == 4 ?
1153 EA_BASE_sib : EA_BASE_sib64);
1155 if (readDisplacement(insn))
1159 insn->eaBase = EA_BASE_NONE;
1160 insn->eaDisplacement = EA_DISP_32;
1161 if (readDisplacement(insn))
1165 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1171 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
1174 case 0xc: /* in case REXW.b is set */
1175 insn->eaBase = EA_BASE_sib;
1177 if (readDisplacement(insn))
1181 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1182 if (readDisplacement(insn))
1188 insn->eaDisplacement = EA_DISP_NONE;
1189 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1193 } /* switch (insn->addressSize) */
1198 #define GENERIC_FIXUP_FUNC(name, base, prefix) \
1199 static uint8_t name(struct InternalInstruction *insn, \
1206 debug("Unhandled register type"); \
1210 return base + index; \
1212 if (insn->rexPrefix && \
1213 index >= 4 && index <= 7) { \
1214 return prefix##_SPL + (index - 4); \
1216 return prefix##_AL + index; \
1219 return prefix##_AX + index; \
1221 return prefix##_EAX + index; \
1223 return prefix##_RAX + index; \
1225 return prefix##_YMM0 + index; \
1230 return prefix##_XMM0 + index; \
1236 return prefix##_MM0 + index; \
1237 case TYPE_SEGMENTREG: \
1240 return prefix##_ES + index; \
1241 case TYPE_DEBUGREG: \
1244 return prefix##_DR0 + index; \
1245 case TYPE_CONTROLREG: \
1248 return prefix##_CR0 + index; \
1253 * fixup*Value - Consults an operand type to determine the meaning of the
1254 * reg or R/M field. If the operand is an XMM operand, for example, an
1255 * operand would be XMM0 instead of AX, which readModRM() would otherwise
1256 * misinterpret it as.
1258 * @param insn - The instruction containing the operand.
1259 * @param type - The operand type.
1260 * @param index - The existing value of the field as reported by readModRM().
1261 * @param valid - The address of a uint8_t. The target is set to 1 if the
1262 * field is valid for the register class; 0 if not.
1263 * @return - The proper value.
1265 GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG)
1266 GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
1269 * fixupReg - Consults an operand specifier to determine which of the
1270 * fixup*Value functions to use in correcting readModRM()'ss interpretation.
1272 * @param insn - See fixup*Value().
1273 * @param op - The operand specifier.
1274 * @return - 0 if fixup was successful; -1 if the register returned was
1275 * invalid for its class.
1277 static int fixupReg(struct InternalInstruction *insn,
1278 const struct OperandSpecifier *op) {
1281 dbgprintf(insn, "fixupReg()");
1283 switch ((OperandEncoding)op->encoding) {
1285 debug("Expected a REG or R/M encoding in fixupReg");
1288 insn->vvvv = (Reg)fixupRegValue(insn,
1289 (OperandType)op->type,
1296 insn->reg = (Reg)fixupRegValue(insn,
1297 (OperandType)op->type,
1298 insn->reg - insn->regBase,
1304 if (insn->eaBase >= insn->eaRegBase) {
1305 insn->eaBase = (EABase)fixupRMValue(insn,
1306 (OperandType)op->type,
1307 insn->eaBase - insn->eaRegBase,
1319 * readOpcodeModifier - Reads an operand from the opcode field of an
1320 * instruction. Handles AddRegFrm instructions.
1322 * @param insn - The instruction whose opcode field is to be read.
1323 * @param inModRM - Indicates that the opcode field is to be read from the
1324 * ModR/M extension; useful for escape opcodes
1325 * @return - 0 on success; nonzero otherwise.
1327 static int readOpcodeModifier(struct InternalInstruction* insn) {
1328 dbgprintf(insn, "readOpcodeModifier()");
1330 if (insn->consumedOpcodeModifier)
1333 insn->consumedOpcodeModifier = TRUE;
1335 switch (insn->spec->modifierType) {
1337 debug("Unknown modifier type.");
1340 debug("No modifier but an operand expects one.");
1342 case MODIFIER_OPCODE:
1343 insn->opcodeModifier = insn->opcode - insn->spec->modifierBase;
1345 case MODIFIER_MODRM:
1346 insn->opcodeModifier = insn->modRM - insn->spec->modifierBase;
1352 * readOpcodeRegister - Reads an operand from the opcode field of an
1353 * instruction and interprets it appropriately given the operand width.
1354 * Handles AddRegFrm instructions.
1356 * @param insn - See readOpcodeModifier().
1357 * @param size - The width (in bytes) of the register being specified.
1358 * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1360 * @return - 0 on success; nonzero otherwise.
1362 static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
1363 dbgprintf(insn, "readOpcodeRegister()");
1365 if (readOpcodeModifier(insn))
1369 size = insn->registerSize;
1373 insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3)
1374 | insn->opcodeModifier));
1375 if (insn->rexPrefix &&
1376 insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1377 insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1378 insn->opcodeRegister = (Reg)(MODRM_REG_SPL
1379 + (insn->opcodeRegister - MODRM_REG_AL - 4));
1384 insn->opcodeRegister = (Reg)(MODRM_REG_AX
1385 + ((bFromREX(insn->rexPrefix) << 3)
1386 | insn->opcodeModifier));
1389 insn->opcodeRegister = (Reg)(MODRM_REG_EAX
1390 + ((bFromREX(insn->rexPrefix) << 3)
1391 | insn->opcodeModifier));
1394 insn->opcodeRegister = (Reg)(MODRM_REG_RAX
1395 + ((bFromREX(insn->rexPrefix) << 3)
1396 | insn->opcodeModifier));
1404 * readImmediate - Consumes an immediate operand from an instruction, given the
1405 * desired operand size.
1407 * @param insn - The instruction whose operand is to be read.
1408 * @param size - The width (in bytes) of the operand.
1409 * @return - 0 if the immediate was successfully consumed; nonzero
1412 static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
1418 dbgprintf(insn, "readImmediate()");
1420 if (insn->numImmediatesConsumed == 2) {
1421 debug("Already consumed two immediates");
1426 size = insn->immediateSize;
1428 insn->immediateSize = size;
1429 insn->immediateOffset = insn->readerCursor - insn->startLocation;
1433 if (consumeByte(insn, &imm8))
1435 insn->immediates[insn->numImmediatesConsumed] = imm8;
1438 if (consumeUInt16(insn, &imm16))
1440 insn->immediates[insn->numImmediatesConsumed] = imm16;
1443 if (consumeUInt32(insn, &imm32))
1445 insn->immediates[insn->numImmediatesConsumed] = imm32;
1448 if (consumeUInt64(insn, &imm64))
1450 insn->immediates[insn->numImmediatesConsumed] = imm64;
1454 insn->numImmediatesConsumed++;
1460 * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix.
1462 * @param insn - The instruction whose operand is to be read.
1463 * @return - 0 if the vvvv was successfully consumed; nonzero
1466 static int readVVVV(struct InternalInstruction* insn) {
1467 dbgprintf(insn, "readVVVV()");
1469 if (insn->vexSize == 3)
1470 insn->vvvv = vvvvFromVEX3of3(insn->vexPrefix[2]);
1471 else if (insn->vexSize == 2)
1472 insn->vvvv = vvvvFromVEX2of2(insn->vexPrefix[1]);
1476 if (insn->mode != MODE_64BIT)
1483 * readOperands - Consults the specifier for an instruction and consumes all
1484 * operands for that instruction, interpreting them as it goes.
1486 * @param insn - The instruction whose operands are to be read and interpreted.
1487 * @return - 0 if all operands could be read; nonzero otherwise.
1489 static int readOperands(struct InternalInstruction* insn) {
1491 int hasVVVV, needVVVV;
1494 dbgprintf(insn, "readOperands()");
1496 /* If non-zero vvvv specified, need to make sure one of the operands
1498 hasVVVV = !readVVVV(insn);
1499 needVVVV = hasVVVV && (insn->vvvv != 0);
1501 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
1502 switch (x86OperandSets[insn->spec->operands][index].encoding) {
1507 if (readModRM(insn))
1509 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1518 dbgprintf(insn, "We currently don't hande code-offset encodings");
1522 /* Saw a register immediate so don't read again and instead split the
1523 previous immediate. FIXME: This is a hack. */
1524 insn->immediates[insn->numImmediatesConsumed] =
1525 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1526 ++insn->numImmediatesConsumed;
1529 if (readImmediate(insn, 1))
1531 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM3 &&
1532 insn->immediates[insn->numImmediatesConsumed - 1] > 7)
1534 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM5 &&
1535 insn->immediates[insn->numImmediatesConsumed - 1] > 31)
1537 if (x86OperandSets[insn->spec->operands][index].type == TYPE_XMM128 ||
1538 x86OperandSets[insn->spec->operands][index].type == TYPE_XMM256)
1542 if (readImmediate(insn, 2))
1546 if (readImmediate(insn, 4))
1550 if (readImmediate(insn, 8))
1554 if (readImmediate(insn, insn->immediateSize))
1558 if (readImmediate(insn, insn->addressSize))
1562 if (readOpcodeRegister(insn, 1))
1566 if (readOpcodeRegister(insn, 2))
1570 if (readOpcodeRegister(insn, 4))
1574 if (readOpcodeRegister(insn, 8))
1578 if (readOpcodeRegister(insn, 0))
1582 if (readOpcodeModifier(insn))
1586 needVVVV = 0; /* Mark that we have found a VVVV operand. */
1589 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1595 dbgprintf(insn, "Encountered an operand with an unknown encoding.");
1600 /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */
1601 if (needVVVV) return -1;
1607 * decodeInstruction - Reads and interprets a full instruction provided by the
1610 * @param insn - A pointer to the instruction to be populated. Must be
1612 * @param reader - The function to be used to read the instruction's bytes.
1613 * @param readerArg - A generic argument to be passed to the reader to store
1614 * any internal state.
1615 * @param logger - If non-NULL, the function to be used to write log messages
1617 * @param loggerArg - A generic argument to be passed to the logger to store
1618 * any internal state.
1619 * @param startLoc - The address (in the reader's address space) of the first
1620 * byte in the instruction.
1621 * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to
1622 * decode the instruction in.
1623 * @return - 0 if the instruction's memory could be read; nonzero if
1626 int decodeInstruction(struct InternalInstruction* insn,
1627 byteReader_t reader,
1628 const void* readerArg,
1633 DisassemblerMode mode) {
1634 memset(insn, 0, sizeof(struct InternalInstruction));
1636 insn->reader = reader;
1637 insn->readerArg = readerArg;
1638 insn->dlog = logger;
1639 insn->dlogArg = loggerArg;
1640 insn->startLocation = startLoc;
1641 insn->readerCursor = startLoc;
1643 insn->numImmediatesConsumed = 0;
1645 if (readPrefixes(insn) ||
1647 getID(insn, miiArg) ||
1648 insn->instructionID == 0 ||
1652 insn->operands = &x86OperandSets[insn->spec->operands][0];
1654 insn->length = insn->readerCursor - insn->startLocation;
1656 dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu",
1657 startLoc, insn->readerCursor, insn->length);
1659 if (insn->length > 15)
1660 dbgprintf(insn, "Instruction exceeds 15-byte limit");