1 /*===-- X86DisassemblerDecoder.c - Disassembler decoder ------------*- C -*-===*
3 * The LLVM Compiler Infrastructure
5 * This file is distributed under the University of Illinois Open Source
6 * License. See LICENSE.TXT for details.
8 *===----------------------------------------------------------------------===*
10 * This file is part of the X86 Disassembler.
11 * It contains the implementation of the instruction decoder.
12 * Documentation for the disassembler can be found in X86Disassembler.h.
14 *===----------------------------------------------------------------------===*/
16 #include <stdarg.h> /* for va_*() */
17 #include <stdio.h> /* for vsnprintf() */
18 #include <stdlib.h> /* for exit() */
19 #include <string.h> /* for memset() */
21 #include "X86DisassemblerDecoder.h"
23 #include "X86GenDisassemblerTables.inc"
29 #define debug(s) do { x86DisassemblerDebug(__FILE__, __LINE__, s); } while (0)
31 #define debug(s) do { } while (0)
36 * contextForAttrs - Client for the instruction context table. Takes a set of
37 * attributes and returns the appropriate decode context.
39 * @param attrMask - Attributes, from the enumeration attributeBits.
40 * @return - The InstructionContext to use when looking up an
41 * an instruction with these attributes.
43 static InstructionContext contextForAttrs(uint16_t attrMask) {
44 return CONTEXTS_SYM[attrMask];
48 * modRMRequired - Reads the appropriate instruction table to determine whether
49 * the ModR/M byte is required to decode a particular instruction.
51 * @param type - The opcode type (i.e., how many bytes it has).
52 * @param insnContext - The context for the instruction, as returned by
54 * @param opcode - The last byte of the instruction's opcode, not counting
55 * ModR/M extensions and escapes.
56 * @return - TRUE if the ModR/M byte is required, FALSE otherwise.
58 static int modRMRequired(OpcodeType type,
59 InstructionContext insnContext,
61 const struct ContextDecision* decision = 0;
65 decision = &ONEBYTE_SYM;
68 decision = &TWOBYTE_SYM;
71 decision = &THREEBYTE38_SYM;
74 decision = &THREEBYTE3A_SYM;
77 decision = &THREEBYTEA6_SYM;
80 decision = &THREEBYTEA7_SYM;
83 decision = &XOP8_MAP_SYM;
86 decision = &XOP9_MAP_SYM;
89 decision = &XOPA_MAP_SYM;
93 return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
94 modrm_type != MODRM_ONEENTRY;
98 * decode - Reads the appropriate instruction table to obtain the unique ID of
101 * @param type - See modRMRequired().
102 * @param insnContext - See modRMRequired().
103 * @param opcode - See modRMRequired().
104 * @param modRM - The ModR/M byte if required, or any value if not.
105 * @return - The UID of the instruction, or 0 on failure.
107 static InstrUID decode(OpcodeType type,
108 InstructionContext insnContext,
111 const struct ModRMDecision* dec = 0;
115 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
118 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
121 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
124 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
127 dec = &THREEBYTEA6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
130 dec = &THREEBYTEA7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
133 dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
136 dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
139 dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
143 switch (dec->modrm_type) {
145 debug("Corrupt table! Unknown modrm_type");
148 return modRMTable[dec->instructionIDs];
150 if (modFromModRM(modRM) == 0x3)
151 return modRMTable[dec->instructionIDs+1];
152 return modRMTable[dec->instructionIDs];
154 if (modFromModRM(modRM) == 0x3)
155 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)+8];
156 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
157 case MODRM_SPLITMISC:
158 if (modFromModRM(modRM) == 0x3)
159 return modRMTable[dec->instructionIDs+(modRM & 0x3f)+8];
160 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
162 return modRMTable[dec->instructionIDs+modRM];
167 * specifierForUID - Given a UID, returns the name and operand specification for
170 * @param uid - The unique ID for the instruction. This should be returned by
171 * decode(); specifierForUID will not check bounds.
172 * @return - A pointer to the specification for that instruction.
174 static const struct InstructionSpecifier *specifierForUID(InstrUID uid) {
175 return &INSTRUCTIONS_SYM[uid];
179 * consumeByte - Uses the reader function provided by the user to consume one
180 * byte from the instruction's memory and advance the cursor.
182 * @param insn - The instruction with the reader function to use. The cursor
183 * for this instruction is advanced.
184 * @param byte - A pointer to a pre-allocated memory buffer to be populated
185 * with the data read.
186 * @return - 0 if the read was successful; nonzero otherwise.
188 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) {
189 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor);
192 ++(insn->readerCursor);
198 * lookAtByte - Like consumeByte, but does not advance the cursor.
200 * @param insn - See consumeByte().
201 * @param byte - See consumeByte().
202 * @return - See consumeByte().
204 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) {
205 return insn->reader(insn->readerArg, byte, insn->readerCursor);
208 static void unconsumeByte(struct InternalInstruction* insn) {
209 insn->readerCursor--;
212 #define CONSUME_FUNC(name, type) \
213 static int name(struct InternalInstruction* insn, type* ptr) { \
216 for (offset = 0; offset < sizeof(type); ++offset) { \
218 int ret = insn->reader(insn->readerArg, \
220 insn->readerCursor + offset); \
223 combined = combined | ((uint64_t)byte << (offset * 8)); \
226 insn->readerCursor += sizeof(type); \
231 * consume* - Use the reader function provided by the user to consume data
232 * values of various sizes from the instruction's memory and advance the
233 * cursor appropriately. These readers perform endian conversion.
235 * @param insn - See consumeByte().
236 * @param ptr - A pointer to a pre-allocated memory of appropriate size to
237 * be populated with the data read.
238 * @return - See consumeByte().
240 CONSUME_FUNC(consumeInt8, int8_t)
241 CONSUME_FUNC(consumeInt16, int16_t)
242 CONSUME_FUNC(consumeInt32, int32_t)
243 CONSUME_FUNC(consumeUInt16, uint16_t)
244 CONSUME_FUNC(consumeUInt32, uint32_t)
245 CONSUME_FUNC(consumeUInt64, uint64_t)
248 * dbgprintf - Uses the logging function provided by the user to log a single
249 * message, typically without a carriage-return.
251 * @param insn - The instruction containing the logging function.
252 * @param format - See printf().
253 * @param ... - See printf().
255 static void dbgprintf(struct InternalInstruction* insn,
264 va_start(ap, format);
265 (void)vsnprintf(buffer, sizeof(buffer), format, ap);
268 insn->dlog(insn->dlogArg, buffer);
274 * setPrefixPresent - Marks that a particular prefix is present at a particular
277 * @param insn - The instruction to be marked as having the prefix.
278 * @param prefix - The prefix that is present.
279 * @param location - The location where the prefix is located (in the address
280 * space of the instruction's reader).
282 static void setPrefixPresent(struct InternalInstruction* insn,
286 insn->prefixPresent[prefix] = 1;
287 insn->prefixLocations[prefix] = location;
291 * isPrefixAtLocation - Queries an instruction to determine whether a prefix is
292 * present at a given location.
294 * @param insn - The instruction to be queried.
295 * @param prefix - The prefix.
296 * @param location - The location to query.
297 * @return - Whether the prefix is at that location.
299 static BOOL isPrefixAtLocation(struct InternalInstruction* insn,
303 if (insn->prefixPresent[prefix] == 1 &&
304 insn->prefixLocations[prefix] == location)
311 * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the
312 * instruction as having them. Also sets the instruction's default operand,
313 * address, and other relevant data sizes to report operands correctly.
315 * @param insn - The instruction whose prefixes are to be read.
316 * @return - 0 if the instruction could be read until the end of the prefix
317 * bytes, and no prefixes conflicted; nonzero otherwise.
319 static int readPrefixes(struct InternalInstruction* insn) {
320 BOOL isPrefix = TRUE;
321 BOOL prefixGroups[4] = { FALSE };
322 uint64_t prefixLocation;
326 BOOL hasAdSize = FALSE;
327 BOOL hasOpSize = FALSE;
329 dbgprintf(insn, "readPrefixes()");
332 prefixLocation = insn->readerCursor;
334 /* If we fail reading prefixes, just stop here and let the opcode reader deal with it */
335 if (consumeByte(insn, &byte))
339 * If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
340 * break and let it be disassembled as a normal "instruction".
342 if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0)
345 if (insn->readerCursor - 1 == insn->startLocation
346 && (byte == 0xf2 || byte == 0xf3)
347 && !lookAtByte(insn, &nextByte))
350 * If the byte is 0xf2 or 0xf3, and any of the following conditions are
352 * - it is followed by a LOCK (0xf0) prefix
353 * - it is followed by an xchg instruction
354 * then it should be disassembled as a xacquire/xrelease not repne/rep.
356 if ((byte == 0xf2 || byte == 0xf3) &&
357 ((nextByte == 0xf0) |
358 ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90)))
359 insn->xAcquireRelease = TRUE;
361 * Also if the byte is 0xf3, and the following condition is met:
362 * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
363 * "mov mem, imm" (opcode 0xc6/0xc7) instructions.
364 * then it should be disassembled as an xrelease not rep.
367 (nextByte == 0x88 || nextByte == 0x89 ||
368 nextByte == 0xc6 || nextByte == 0xc7))
369 insn->xAcquireRelease = TRUE;
370 if (insn->mode == MODE_64BIT && (nextByte & 0xf0) == 0x40) {
371 if (consumeByte(insn, &nextByte))
373 if (lookAtByte(insn, &nextByte))
377 if (nextByte != 0x0f && nextByte != 0x90)
382 case 0xf0: /* LOCK */
383 case 0xf2: /* REPNE/REPNZ */
384 case 0xf3: /* REP or REPE/REPZ */
386 dbgprintf(insn, "Redundant Group 1 prefix");
387 prefixGroups[0] = TRUE;
388 setPrefixPresent(insn, byte, prefixLocation);
390 case 0x2e: /* CS segment override -OR- Branch not taken */
391 case 0x36: /* SS segment override -OR- Branch taken */
392 case 0x3e: /* DS segment override */
393 case 0x26: /* ES segment override */
394 case 0x64: /* FS segment override */
395 case 0x65: /* GS segment override */
398 insn->segmentOverride = SEG_OVERRIDE_CS;
401 insn->segmentOverride = SEG_OVERRIDE_SS;
404 insn->segmentOverride = SEG_OVERRIDE_DS;
407 insn->segmentOverride = SEG_OVERRIDE_ES;
410 insn->segmentOverride = SEG_OVERRIDE_FS;
413 insn->segmentOverride = SEG_OVERRIDE_GS;
416 debug("Unhandled override");
420 dbgprintf(insn, "Redundant Group 2 prefix");
421 prefixGroups[1] = TRUE;
422 setPrefixPresent(insn, byte, prefixLocation);
424 case 0x66: /* Operand-size override */
426 dbgprintf(insn, "Redundant Group 3 prefix");
427 prefixGroups[2] = TRUE;
429 setPrefixPresent(insn, byte, prefixLocation);
431 case 0x67: /* Address-size override */
433 dbgprintf(insn, "Redundant Group 4 prefix");
434 prefixGroups[3] = TRUE;
436 setPrefixPresent(insn, byte, prefixLocation);
438 default: /* Not a prefix byte */
444 dbgprintf(insn, "Found prefix 0x%hhx", byte);
447 insn->vectorExtensionType = TYPE_NO_VEX_XOP;
450 uint8_t byte1, byte2;
452 if (consumeByte(insn, &byte1)) {
453 dbgprintf(insn, "Couldn't read second byte of EVEX prefix");
457 if (lookAtByte(insn, &byte2)) {
458 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
462 if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) &&
463 ((~byte1 & 0xc) == 0xc) && ((byte2 & 0x4) == 0x4)) {
464 insn->vectorExtensionType = TYPE_EVEX;
467 unconsumeByte(insn); /* unconsume byte1 */
468 unconsumeByte(insn); /* unconsume byte */
469 insn->necessaryPrefixLocation = insn->readerCursor - 2;
472 if (insn->vectorExtensionType == TYPE_EVEX) {
473 insn->vectorExtensionPrefix[0] = byte;
474 insn->vectorExtensionPrefix[1] = byte1;
475 if (consumeByte(insn, &insn->vectorExtensionPrefix[2])) {
476 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
479 if (consumeByte(insn, &insn->vectorExtensionPrefix[3])) {
480 dbgprintf(insn, "Couldn't read fourth byte of EVEX prefix");
484 /* We simulate the REX prefix for simplicity's sake */
485 if (insn->mode == MODE_64BIT) {
486 insn->rexPrefix = 0x40
487 | (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3)
488 | (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2)
489 | (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1)
490 | (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0);
493 hasOpSize = (VEX_PREFIX_66 == ppFromEVEX3of4(insn->vectorExtensionPrefix[2]));
495 dbgprintf(insn, "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
496 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
497 insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]);
500 else if (byte == 0xc4) {
503 if (lookAtByte(insn, &byte1)) {
504 dbgprintf(insn, "Couldn't read second byte of VEX");
508 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
509 insn->vectorExtensionType = TYPE_VEX_3B;
510 insn->necessaryPrefixLocation = insn->readerCursor - 1;
514 insn->necessaryPrefixLocation = insn->readerCursor - 1;
517 if (insn->vectorExtensionType == TYPE_VEX_3B) {
518 insn->vectorExtensionPrefix[0] = byte;
519 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
520 consumeByte(insn, &insn->vectorExtensionPrefix[2]);
522 /* We simulate the REX prefix for simplicity's sake */
524 if (insn->mode == MODE_64BIT) {
525 insn->rexPrefix = 0x40
526 | (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3)
527 | (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2)
528 | (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1)
529 | (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0);
532 switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2]))
541 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx",
542 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
543 insn->vectorExtensionPrefix[2]);
546 else if (byte == 0xc5) {
549 if (lookAtByte(insn, &byte1)) {
550 dbgprintf(insn, "Couldn't read second byte of VEX");
554 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
555 insn->vectorExtensionType = TYPE_VEX_2B;
561 if (insn->vectorExtensionType == TYPE_VEX_2B) {
562 insn->vectorExtensionPrefix[0] = byte;
563 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
565 if (insn->mode == MODE_64BIT) {
566 insn->rexPrefix = 0x40
567 | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2);
570 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1]))
579 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx",
580 insn->vectorExtensionPrefix[0],
581 insn->vectorExtensionPrefix[1]);
584 else if (byte == 0x8f) {
587 if (lookAtByte(insn, &byte1)) {
588 dbgprintf(insn, "Couldn't read second byte of XOP");
592 if ((byte1 & 0x38) != 0x0) { /* 0 in these 3 bits is a POP instruction. */
593 insn->vectorExtensionType = TYPE_XOP;
594 insn->necessaryPrefixLocation = insn->readerCursor - 1;
598 insn->necessaryPrefixLocation = insn->readerCursor - 1;
601 if (insn->vectorExtensionType == TYPE_XOP) {
602 insn->vectorExtensionPrefix[0] = byte;
603 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
604 consumeByte(insn, &insn->vectorExtensionPrefix[2]);
606 /* We simulate the REX prefix for simplicity's sake */
608 if (insn->mode == MODE_64BIT) {
609 insn->rexPrefix = 0x40
610 | (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3)
611 | (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2)
612 | (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1)
613 | (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0);
616 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2]))
625 dbgprintf(insn, "Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
626 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
627 insn->vectorExtensionPrefix[2]);
631 if (insn->mode == MODE_64BIT) {
632 if ((byte & 0xf0) == 0x40) {
635 if (lookAtByte(insn, &opcodeByte) || ((opcodeByte & 0xf0) == 0x40)) {
636 dbgprintf(insn, "Redundant REX prefix");
640 insn->rexPrefix = byte;
641 insn->necessaryPrefixLocation = insn->readerCursor - 2;
643 dbgprintf(insn, "Found REX prefix 0x%hhx", byte);
646 insn->necessaryPrefixLocation = insn->readerCursor - 1;
650 insn->necessaryPrefixLocation = insn->readerCursor - 1;
654 if (insn->mode == MODE_16BIT) {
655 insn->registerSize = (hasOpSize ? 4 : 2);
656 insn->addressSize = (hasAdSize ? 4 : 2);
657 insn->displacementSize = (hasAdSize ? 4 : 2);
658 insn->immediateSize = (hasOpSize ? 4 : 2);
659 } else if (insn->mode == MODE_32BIT) {
660 insn->registerSize = (hasOpSize ? 2 : 4);
661 insn->addressSize = (hasAdSize ? 2 : 4);
662 insn->displacementSize = (hasAdSize ? 2 : 4);
663 insn->immediateSize = (hasOpSize ? 2 : 4);
664 } else if (insn->mode == MODE_64BIT) {
665 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
666 insn->registerSize = 8;
667 insn->addressSize = (hasAdSize ? 4 : 8);
668 insn->displacementSize = 4;
669 insn->immediateSize = 4;
670 } else if (insn->rexPrefix) {
671 insn->registerSize = (hasOpSize ? 2 : 4);
672 insn->addressSize = (hasAdSize ? 4 : 8);
673 insn->displacementSize = (hasOpSize ? 2 : 4);
674 insn->immediateSize = (hasOpSize ? 2 : 4);
676 insn->registerSize = (hasOpSize ? 2 : 4);
677 insn->addressSize = (hasAdSize ? 4 : 8);
678 insn->displacementSize = (hasOpSize ? 2 : 4);
679 insn->immediateSize = (hasOpSize ? 2 : 4);
687 * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of
688 * extended or escape opcodes).
690 * @param insn - The instruction whose opcode is to be read.
691 * @return - 0 if the opcode could be read successfully; nonzero otherwise.
693 static int readOpcode(struct InternalInstruction* insn) {
694 /* Determine the length of the primary opcode */
698 dbgprintf(insn, "readOpcode()");
700 insn->opcodeType = ONEBYTE;
702 if (insn->vectorExtensionType == TYPE_EVEX)
704 switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) {
706 dbgprintf(insn, "Unhandled mm field for instruction (0x%hhx)",
707 mmFromEVEX2of4(insn->vectorExtensionPrefix[1]));
710 insn->opcodeType = TWOBYTE;
711 return consumeByte(insn, &insn->opcode);
713 insn->opcodeType = THREEBYTE_38;
714 return consumeByte(insn, &insn->opcode);
716 insn->opcodeType = THREEBYTE_3A;
717 return consumeByte(insn, &insn->opcode);
720 else if (insn->vectorExtensionType == TYPE_VEX_3B) {
721 switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
723 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
724 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
727 insn->opcodeType = TWOBYTE;
728 return consumeByte(insn, &insn->opcode);
730 insn->opcodeType = THREEBYTE_38;
731 return consumeByte(insn, &insn->opcode);
733 insn->opcodeType = THREEBYTE_3A;
734 return consumeByte(insn, &insn->opcode);
737 else if (insn->vectorExtensionType == TYPE_VEX_2B) {
738 insn->opcodeType = TWOBYTE;
739 return consumeByte(insn, &insn->opcode);
741 else if (insn->vectorExtensionType == TYPE_XOP) {
742 switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) {
744 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
745 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
747 case XOP_MAP_SELECT_8:
748 insn->opcodeType = XOP8_MAP;
749 return consumeByte(insn, &insn->opcode);
750 case XOP_MAP_SELECT_9:
751 insn->opcodeType = XOP9_MAP;
752 return consumeByte(insn, &insn->opcode);
753 case XOP_MAP_SELECT_A:
754 insn->opcodeType = XOPA_MAP;
755 return consumeByte(insn, &insn->opcode);
759 if (consumeByte(insn, ¤t))
762 if (current == 0x0f) {
763 dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current);
765 if (consumeByte(insn, ¤t))
768 if (current == 0x38) {
769 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
771 if (consumeByte(insn, ¤t))
774 insn->opcodeType = THREEBYTE_38;
775 } else if (current == 0x3a) {
776 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
778 if (consumeByte(insn, ¤t))
781 insn->opcodeType = THREEBYTE_3A;
782 } else if (current == 0xa6) {
783 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
785 if (consumeByte(insn, ¤t))
788 insn->opcodeType = THREEBYTE_A6;
789 } else if (current == 0xa7) {
790 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
792 if (consumeByte(insn, ¤t))
795 insn->opcodeType = THREEBYTE_A7;
797 dbgprintf(insn, "Didn't find a three-byte escape prefix");
799 insn->opcodeType = TWOBYTE;
804 * At this point we have consumed the full opcode.
805 * Anything we consume from here on must be unconsumed.
808 insn->opcode = current;
813 static int readModRM(struct InternalInstruction* insn);
816 * getIDWithAttrMask - Determines the ID of an instruction, consuming
817 * the ModR/M byte as appropriate for extended and escape opcodes,
818 * and using a supplied attribute mask.
820 * @param instructionID - A pointer whose target is filled in with the ID of the
822 * @param insn - The instruction whose ID is to be determined.
823 * @param attrMask - The attribute mask to search.
824 * @return - 0 if the ModR/M could be read when needed or was not
825 * needed; nonzero otherwise.
827 static int getIDWithAttrMask(uint16_t* instructionID,
828 struct InternalInstruction* insn,
830 BOOL hasModRMExtension;
832 uint16_t instructionClass;
834 instructionClass = contextForAttrs(attrMask);
836 hasModRMExtension = modRMRequired(insn->opcodeType,
840 if (hasModRMExtension) {
844 *instructionID = decode(insn->opcodeType,
849 *instructionID = decode(insn->opcodeType,
859 * is16BitEquivalent - Determines whether two instruction names refer to
860 * equivalent instructions but one is 16-bit whereas the other is not.
862 * @param orig - The instruction that is not 16-bit
863 * @param equiv - The instruction that is 16-bit
865 static BOOL is16BitEquivalent(const char* orig, const char* equiv) {
869 if (orig[i] == '\0' && equiv[i] == '\0')
871 if (orig[i] == '\0' || equiv[i] == '\0')
873 if (orig[i] != equiv[i]) {
874 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
876 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
878 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
886 * getID - Determines the ID of an instruction, consuming the ModR/M byte as
887 * appropriate for extended and escape opcodes. Determines the attributes and
888 * context for the instruction before doing so.
890 * @param insn - The instruction whose ID is to be determined.
891 * @return - 0 if the ModR/M could be read when needed or was not needed;
894 static int getID(struct InternalInstruction* insn, const void *miiArg) {
896 uint16_t instructionID;
898 dbgprintf(insn, "getID()");
900 attrMask = ATTR_NONE;
902 if (insn->mode == MODE_64BIT)
903 attrMask |= ATTR_64BIT;
905 if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) {
906 attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX;
908 if (insn->vectorExtensionType == TYPE_EVEX) {
909 switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) {
911 attrMask |= ATTR_OPSIZE;
921 if (zFromEVEX4of4(insn->vectorExtensionPrefix[3]))
922 attrMask |= ATTR_EVEXKZ;
923 if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
924 attrMask |= ATTR_EVEXB;
925 if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]))
926 attrMask |= ATTR_EVEXK;
927 if (lFromEVEX4of4(insn->vectorExtensionPrefix[3]))
928 attrMask |= ATTR_EVEXL;
929 if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]))
930 attrMask |= ATTR_EVEXL2;
932 else if (insn->vectorExtensionType == TYPE_VEX_3B) {
933 switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) {
935 attrMask |= ATTR_OPSIZE;
945 if (lFromVEX3of3(insn->vectorExtensionPrefix[2]))
946 attrMask |= ATTR_VEXL;
948 else if (insn->vectorExtensionType == TYPE_VEX_2B) {
949 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
951 attrMask |= ATTR_OPSIZE;
961 if (lFromVEX2of2(insn->vectorExtensionPrefix[1]))
962 attrMask |= ATTR_VEXL;
964 else if (insn->vectorExtensionType == TYPE_XOP) {
965 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
967 attrMask |= ATTR_OPSIZE;
977 if (lFromXOP3of3(insn->vectorExtensionPrefix[2]))
978 attrMask |= ATTR_VEXL;
985 if (isPrefixAtLocation(insn, 0x66, insn->necessaryPrefixLocation))
986 attrMask |= ATTR_OPSIZE;
987 else if (isPrefixAtLocation(insn, 0x67, insn->necessaryPrefixLocation))
988 attrMask |= ATTR_ADSIZE;
989 else if (isPrefixAtLocation(insn, 0xf3, insn->necessaryPrefixLocation))
991 else if (isPrefixAtLocation(insn, 0xf2, insn->necessaryPrefixLocation))
995 if (insn->rexPrefix & 0x08)
996 attrMask |= ATTR_REXW;
998 if (getIDWithAttrMask(&instructionID, insn, attrMask))
1001 /* The following clauses compensate for limitations of the tables. */
1003 if (insn->prefixPresent[0x66] && !(attrMask & ATTR_OPSIZE)) {
1005 * The instruction tables make no distinction between instructions that
1006 * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
1007 * particular spot (i.e., many MMX operations). In general we're
1008 * conservative, but in the specific case where OpSize is present but not
1009 * in the right place we check if there's a 16-bit operation.
1012 const struct InstructionSpecifier *spec;
1013 uint16_t instructionIDWithOpsize;
1014 const char *specName, *specWithOpSizeName;
1016 spec = specifierForUID(instructionID);
1018 if (getIDWithAttrMask(&instructionIDWithOpsize,
1020 attrMask | ATTR_OPSIZE)) {
1022 * ModRM required with OpSize but not present; give up and return version
1023 * without OpSize set
1026 insn->instructionID = instructionID;
1031 specName = x86DisassemblerGetInstrName(instructionID, miiArg);
1032 specWithOpSizeName =
1033 x86DisassemblerGetInstrName(instructionIDWithOpsize, miiArg);
1035 if (is16BitEquivalent(specName, specWithOpSizeName)) {
1036 insn->instructionID = instructionIDWithOpsize;
1037 insn->spec = specifierForUID(instructionIDWithOpsize);
1039 insn->instructionID = instructionID;
1045 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
1046 insn->rexPrefix & 0x01) {
1048 * NOOP shouldn't decode as NOOP if REX.b is set. Instead
1049 * it should decode as XCHG %r8, %eax.
1052 const struct InstructionSpecifier *spec;
1053 uint16_t instructionIDWithNewOpcode;
1054 const struct InstructionSpecifier *specWithNewOpcode;
1056 spec = specifierForUID(instructionID);
1058 /* Borrow opcode from one of the other XCHGar opcodes */
1059 insn->opcode = 0x91;
1061 if (getIDWithAttrMask(&instructionIDWithNewOpcode,
1064 insn->opcode = 0x90;
1066 insn->instructionID = instructionID;
1071 specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode);
1074 insn->opcode = 0x90;
1076 insn->instructionID = instructionIDWithNewOpcode;
1077 insn->spec = specWithNewOpcode;
1082 insn->instructionID = instructionID;
1083 insn->spec = specifierForUID(insn->instructionID);
1089 * readSIB - Consumes the SIB byte to determine addressing information for an
1092 * @param insn - The instruction whose SIB byte is to be read.
1093 * @return - 0 if the SIB byte was successfully read; nonzero otherwise.
1095 static int readSIB(struct InternalInstruction* insn) {
1096 SIBIndex sibIndexBase = 0;
1097 SIBBase sibBaseBase = 0;
1098 uint8_t index, base;
1100 dbgprintf(insn, "readSIB()");
1102 if (insn->consumedSIB)
1105 insn->consumedSIB = TRUE;
1107 switch (insn->addressSize) {
1109 dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode");
1113 sibIndexBase = SIB_INDEX_EAX;
1114 sibBaseBase = SIB_BASE_EAX;
1117 sibIndexBase = SIB_INDEX_RAX;
1118 sibBaseBase = SIB_BASE_RAX;
1122 if (consumeByte(insn, &insn->sib))
1125 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3);
1126 if (insn->vectorExtensionType == TYPE_EVEX)
1127 index |= v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4;
1131 insn->sibIndex = SIB_INDEX_NONE;
1134 insn->sibIndex = (SIBIndex)(sibIndexBase + index);
1135 if (insn->sibIndex == SIB_INDEX_sib ||
1136 insn->sibIndex == SIB_INDEX_sib64)
1137 insn->sibIndex = SIB_INDEX_NONE;
1141 switch (scaleFromSIB(insn->sib)) {
1156 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3);
1160 switch (modFromModRM(insn->modRM)) {
1162 insn->eaDisplacement = EA_DISP_32;
1163 insn->sibBase = SIB_BASE_NONE;
1166 insn->eaDisplacement = EA_DISP_8;
1167 insn->sibBase = (insn->addressSize == 4 ?
1168 SIB_BASE_EBP : SIB_BASE_RBP);
1171 insn->eaDisplacement = EA_DISP_32;
1172 insn->sibBase = (insn->addressSize == 4 ?
1173 SIB_BASE_EBP : SIB_BASE_RBP);
1176 debug("Cannot have Mod = 0b11 and a SIB byte");
1181 insn->sibBase = (SIBBase)(sibBaseBase + base);
1189 * readDisplacement - Consumes the displacement of an instruction.
1191 * @param insn - The instruction whose displacement is to be read.
1192 * @return - 0 if the displacement byte was successfully read; nonzero
1195 static int readDisplacement(struct InternalInstruction* insn) {
1200 dbgprintf(insn, "readDisplacement()");
1202 if (insn->consumedDisplacement)
1205 insn->consumedDisplacement = TRUE;
1206 insn->displacementOffset = insn->readerCursor - insn->startLocation;
1208 switch (insn->eaDisplacement) {
1210 insn->consumedDisplacement = FALSE;
1213 if (consumeInt8(insn, &d8))
1215 insn->displacement = d8;
1218 if (consumeInt16(insn, &d16))
1220 insn->displacement = d16;
1223 if (consumeInt32(insn, &d32))
1225 insn->displacement = d32;
1229 insn->consumedDisplacement = TRUE;
1234 * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and
1235 * displacement) for an instruction and interprets it.
1237 * @param insn - The instruction whose addressing information is to be read.
1238 * @return - 0 if the information was successfully read; nonzero otherwise.
1240 static int readModRM(struct InternalInstruction* insn) {
1241 uint8_t mod, rm, reg;
1243 dbgprintf(insn, "readModRM()");
1245 if (insn->consumedModRM)
1248 if (consumeByte(insn, &insn->modRM))
1250 insn->consumedModRM = TRUE;
1252 mod = modFromModRM(insn->modRM);
1253 rm = rmFromModRM(insn->modRM);
1254 reg = regFromModRM(insn->modRM);
1257 * This goes by insn->registerSize to pick the correct register, which messes
1258 * up if we're using (say) XMM or 8-bit register operands. That gets fixed in
1261 switch (insn->registerSize) {
1263 insn->regBase = MODRM_REG_AX;
1264 insn->eaRegBase = EA_REG_AX;
1267 insn->regBase = MODRM_REG_EAX;
1268 insn->eaRegBase = EA_REG_EAX;
1271 insn->regBase = MODRM_REG_RAX;
1272 insn->eaRegBase = EA_REG_RAX;
1276 reg |= rFromREX(insn->rexPrefix) << 3;
1277 rm |= bFromREX(insn->rexPrefix) << 3;
1278 if (insn->vectorExtensionType == TYPE_EVEX) {
1279 reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1280 rm |= xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1283 insn->reg = (Reg)(insn->regBase + reg);
1285 switch (insn->addressSize) {
1287 insn->eaBaseBase = EA_BASE_BX_SI;
1292 insn->eaBase = EA_BASE_NONE;
1293 insn->eaDisplacement = EA_DISP_16;
1294 if (readDisplacement(insn))
1297 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1298 insn->eaDisplacement = EA_DISP_NONE;
1302 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1303 insn->eaDisplacement = EA_DISP_8;
1304 if (readDisplacement(insn))
1308 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1309 insn->eaDisplacement = EA_DISP_16;
1310 if (readDisplacement(insn))
1314 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1315 if (readDisplacement(insn))
1322 insn->eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
1326 insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */
1330 case 0xc: /* in case REXW.b is set */
1331 insn->eaBase = (insn->addressSize == 4 ?
1332 EA_BASE_sib : EA_BASE_sib64);
1334 if (readDisplacement(insn))
1338 insn->eaBase = EA_BASE_NONE;
1339 insn->eaDisplacement = EA_DISP_32;
1340 if (readDisplacement(insn))
1344 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1350 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
1354 case 0xc: /* in case REXW.b is set */
1355 insn->eaBase = EA_BASE_sib;
1357 if (readDisplacement(insn))
1361 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1362 if (readDisplacement(insn))
1368 insn->eaDisplacement = EA_DISP_NONE;
1369 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1373 } /* switch (insn->addressSize) */
1378 #define GENERIC_FIXUP_FUNC(name, base, prefix) \
1379 static uint8_t name(struct InternalInstruction *insn, \
1386 debug("Unhandled register type"); \
1390 return base + index; \
1392 if (insn->rexPrefix && \
1393 index >= 4 && index <= 7) { \
1394 return prefix##_SPL + (index - 4); \
1396 return prefix##_AL + index; \
1399 return prefix##_AX + index; \
1401 return prefix##_EAX + index; \
1403 return prefix##_RAX + index; \
1405 return prefix##_ZMM0 + index; \
1407 return prefix##_YMM0 + index; \
1412 return prefix##_XMM0 + index; \
1416 return prefix##_K0 + index; \
1422 return prefix##_MM0 + index; \
1423 case TYPE_SEGMENTREG: \
1426 return prefix##_ES + index; \
1427 case TYPE_DEBUGREG: \
1430 return prefix##_DR0 + index; \
1431 case TYPE_CONTROLREG: \
1434 return prefix##_CR0 + index; \
1439 * fixup*Value - Consults an operand type to determine the meaning of the
1440 * reg or R/M field. If the operand is an XMM operand, for example, an
1441 * operand would be XMM0 instead of AX, which readModRM() would otherwise
1442 * misinterpret it as.
1444 * @param insn - The instruction containing the operand.
1445 * @param type - The operand type.
1446 * @param index - The existing value of the field as reported by readModRM().
1447 * @param valid - The address of a uint8_t. The target is set to 1 if the
1448 * field is valid for the register class; 0 if not.
1449 * @return - The proper value.
1451 GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG)
1452 GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
1455 * fixupReg - Consults an operand specifier to determine which of the
1456 * fixup*Value functions to use in correcting readModRM()'ss interpretation.
1458 * @param insn - See fixup*Value().
1459 * @param op - The operand specifier.
1460 * @return - 0 if fixup was successful; -1 if the register returned was
1461 * invalid for its class.
1463 static int fixupReg(struct InternalInstruction *insn,
1464 const struct OperandSpecifier *op) {
1467 dbgprintf(insn, "fixupReg()");
1469 switch ((OperandEncoding)op->encoding) {
1471 debug("Expected a REG or R/M encoding in fixupReg");
1474 insn->vvvv = (Reg)fixupRegValue(insn,
1475 (OperandType)op->type,
1482 insn->reg = (Reg)fixupRegValue(insn,
1483 (OperandType)op->type,
1484 insn->reg - insn->regBase,
1490 if (insn->eaBase >= insn->eaRegBase) {
1491 insn->eaBase = (EABase)fixupRMValue(insn,
1492 (OperandType)op->type,
1493 insn->eaBase - insn->eaRegBase,
1505 * readOpcodeModifier - Reads an operand from the opcode field of an
1506 * instruction. Handles AddRegFrm instructions.
1508 * @param insn - The instruction whose opcode field is to be read.
1509 * @return - 0 on success; nonzero otherwise.
1511 static int readOpcodeModifier(struct InternalInstruction* insn) {
1512 dbgprintf(insn, "readOpcodeModifier()");
1514 if (insn->consumedOpcodeModifier)
1517 insn->consumedOpcodeModifier = TRUE;
1519 switch (insn->spec->modifierType) {
1521 debug("Unknown modifier type.");
1524 debug("No modifier but an operand expects one.");
1526 case MODIFIER_OPCODE:
1527 insn->opcodeModifier = insn->opcode - insn->spec->modifierBase;
1533 * readOpcodeRegister - Reads an operand from the opcode field of an
1534 * instruction and interprets it appropriately given the operand width.
1535 * Handles AddRegFrm instructions.
1537 * @param insn - See readOpcodeModifier().
1538 * @param size - The width (in bytes) of the register being specified.
1539 * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1541 * @return - 0 on success; nonzero otherwise.
1543 static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
1544 dbgprintf(insn, "readOpcodeRegister()");
1546 if (readOpcodeModifier(insn))
1550 size = insn->registerSize;
1554 insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3)
1555 | insn->opcodeModifier));
1556 if (insn->rexPrefix &&
1557 insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1558 insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1559 insn->opcodeRegister = (Reg)(MODRM_REG_SPL
1560 + (insn->opcodeRegister - MODRM_REG_AL - 4));
1565 insn->opcodeRegister = (Reg)(MODRM_REG_AX
1566 + ((bFromREX(insn->rexPrefix) << 3)
1567 | insn->opcodeModifier));
1570 insn->opcodeRegister = (Reg)(MODRM_REG_EAX
1571 + ((bFromREX(insn->rexPrefix) << 3)
1572 | insn->opcodeModifier));
1575 insn->opcodeRegister = (Reg)(MODRM_REG_RAX
1576 + ((bFromREX(insn->rexPrefix) << 3)
1577 | insn->opcodeModifier));
1585 * readImmediate - Consumes an immediate operand from an instruction, given the
1586 * desired operand size.
1588 * @param insn - The instruction whose operand is to be read.
1589 * @param size - The width (in bytes) of the operand.
1590 * @return - 0 if the immediate was successfully consumed; nonzero
1593 static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
1599 dbgprintf(insn, "readImmediate()");
1601 if (insn->numImmediatesConsumed == 2) {
1602 debug("Already consumed two immediates");
1607 size = insn->immediateSize;
1609 insn->immediateSize = size;
1610 insn->immediateOffset = insn->readerCursor - insn->startLocation;
1614 if (consumeByte(insn, &imm8))
1616 insn->immediates[insn->numImmediatesConsumed] = imm8;
1619 if (consumeUInt16(insn, &imm16))
1621 insn->immediates[insn->numImmediatesConsumed] = imm16;
1624 if (consumeUInt32(insn, &imm32))
1626 insn->immediates[insn->numImmediatesConsumed] = imm32;
1629 if (consumeUInt64(insn, &imm64))
1631 insn->immediates[insn->numImmediatesConsumed] = imm64;
1635 insn->numImmediatesConsumed++;
1641 * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix.
1643 * @param insn - The instruction whose operand is to be read.
1644 * @return - 0 if the vvvv was successfully consumed; nonzero
1647 static int readVVVV(struct InternalInstruction* insn) {
1648 dbgprintf(insn, "readVVVV()");
1650 if (insn->vectorExtensionType == TYPE_EVEX)
1651 insn->vvvv = vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]);
1652 else if (insn->vectorExtensionType == TYPE_VEX_3B)
1653 insn->vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
1654 else if (insn->vectorExtensionType == TYPE_VEX_2B)
1655 insn->vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
1656 else if (insn->vectorExtensionType == TYPE_XOP)
1657 insn->vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
1661 if (insn->mode != MODE_64BIT)
1668 * readMaskRegister - Reads an mask register from the opcode field of an
1671 * @param insn - The instruction whose opcode field is to be read.
1672 * @return - 0 on success; nonzero otherwise.
1674 static int readMaskRegister(struct InternalInstruction* insn) {
1675 dbgprintf(insn, "readMaskRegister()");
1677 if (insn->vectorExtensionType != TYPE_EVEX)
1680 insn->writemask = aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]);
1685 * readOperands - Consults the specifier for an instruction and consumes all
1686 * operands for that instruction, interpreting them as it goes.
1688 * @param insn - The instruction whose operands are to be read and interpreted.
1689 * @return - 0 if all operands could be read; nonzero otherwise.
1691 static int readOperands(struct InternalInstruction* insn) {
1693 int hasVVVV, needVVVV;
1696 dbgprintf(insn, "readOperands()");
1698 /* If non-zero vvvv specified, need to make sure one of the operands
1700 hasVVVV = !readVVVV(insn);
1701 needVVVV = hasVVVV && (insn->vvvv != 0);
1703 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
1704 switch (x86OperandSets[insn->spec->operands][index].encoding) {
1709 if (readModRM(insn))
1711 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1720 dbgprintf(insn, "We currently don't hande code-offset encodings");
1724 /* Saw a register immediate so don't read again and instead split the
1725 previous immediate. FIXME: This is a hack. */
1726 insn->immediates[insn->numImmediatesConsumed] =
1727 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1728 ++insn->numImmediatesConsumed;
1731 if (readImmediate(insn, 1))
1733 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM3 &&
1734 insn->immediates[insn->numImmediatesConsumed - 1] > 7)
1736 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM5 &&
1737 insn->immediates[insn->numImmediatesConsumed - 1] > 31)
1739 if (x86OperandSets[insn->spec->operands][index].type == TYPE_XMM128 ||
1740 x86OperandSets[insn->spec->operands][index].type == TYPE_XMM256)
1744 if (readImmediate(insn, 2))
1748 if (readImmediate(insn, 4))
1752 if (readImmediate(insn, 8))
1756 if (readImmediate(insn, insn->immediateSize))
1760 if (readImmediate(insn, insn->addressSize))
1764 if (readOpcodeRegister(insn, 1))
1768 if (readOpcodeRegister(insn, 2))
1772 if (readOpcodeRegister(insn, 4))
1776 if (readOpcodeRegister(insn, 8))
1780 if (readOpcodeRegister(insn, 0))
1784 if (readOpcodeModifier(insn))
1788 needVVVV = 0; /* Mark that we have found a VVVV operand. */
1791 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1794 case ENCODING_WRITEMASK:
1795 if (readMaskRegister(insn))
1801 dbgprintf(insn, "Encountered an operand with an unknown encoding.");
1806 /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */
1807 if (needVVVV) return -1;
1813 * decodeInstruction - Reads and interprets a full instruction provided by the
1816 * @param insn - A pointer to the instruction to be populated. Must be
1818 * @param reader - The function to be used to read the instruction's bytes.
1819 * @param readerArg - A generic argument to be passed to the reader to store
1820 * any internal state.
1821 * @param logger - If non-NULL, the function to be used to write log messages
1823 * @param loggerArg - A generic argument to be passed to the logger to store
1824 * any internal state.
1825 * @param startLoc - The address (in the reader's address space) of the first
1826 * byte in the instruction.
1827 * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to
1828 * decode the instruction in.
1829 * @return - 0 if the instruction's memory could be read; nonzero if
1832 int decodeInstruction(struct InternalInstruction* insn,
1833 byteReader_t reader,
1834 const void* readerArg,
1839 DisassemblerMode mode) {
1840 memset(insn, 0, sizeof(struct InternalInstruction));
1842 insn->reader = reader;
1843 insn->readerArg = readerArg;
1844 insn->dlog = logger;
1845 insn->dlogArg = loggerArg;
1846 insn->startLocation = startLoc;
1847 insn->readerCursor = startLoc;
1849 insn->numImmediatesConsumed = 0;
1851 if (readPrefixes(insn) ||
1853 getID(insn, miiArg) ||
1854 insn->instructionID == 0 ||
1858 insn->operands = &x86OperandSets[insn->spec->operands][0];
1860 insn->length = insn->readerCursor - insn->startLocation;
1862 dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu",
1863 startLoc, insn->readerCursor, insn->length);
1865 if (insn->length > 15)
1866 dbgprintf(insn, "Instruction exceeds 15-byte limit");