1 //===-- X86DisassemblerDecoder.c - Disassembler decoder -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler.
11 // It contains the implementation of the instruction decoder.
12 // Documentation for the disassembler can be found in X86Disassembler.h.
14 //===----------------------------------------------------------------------===//
16 #include <stdarg.h> /* for va_*() */
17 #include <stdio.h> /* for vsnprintf() */
18 #include <stdlib.h> /* for exit() */
19 #include <string.h> /* for memset() */
21 #include "X86DisassemblerDecoder.h"
23 using namespace llvm::X86Disassembler;
25 /// Specifies whether a ModR/M byte is needed and (if so) which
26 /// instruction each possible value of the ModR/M byte corresponds to. Once
27 /// this information is known, we have narrowed down to a single instruction.
28 struct ModRMDecision {
30 uint16_t instructionIDs;
33 /// Specifies which set of ModR/M->instruction tables to look at
34 /// given a particular opcode.
35 struct OpcodeDecision {
36 ModRMDecision modRMDecisions[256];
39 /// Specifies which opcode->instruction tables to look at given
40 /// a particular context (set of attributes). Since there are many possible
41 /// contexts, the decoder first uses CONTEXTS_SYM to determine which context
42 /// applies given a specific set of attributes. Hence there are only IC_max
43 /// entries in this table, rather than 2^(ATTR_max).
44 struct ContextDecision {
45 OpcodeDecision opcodeDecisions[IC_max];
48 #include "X86GenDisassemblerTables.inc"
51 #define debug(s) do { Debug(__FILE__, __LINE__, s); } while (0)
53 #define debug(s) do { } while (0)
58 * contextForAttrs - Client for the instruction context table. Takes a set of
59 * attributes and returns the appropriate decode context.
61 * @param attrMask - Attributes, from the enumeration attributeBits.
62 * @return - The InstructionContext to use when looking up an
63 * an instruction with these attributes.
65 static InstructionContext contextForAttrs(uint16_t attrMask) {
66 return static_cast<InstructionContext>(CONTEXTS_SYM[attrMask]);
70 * modRMRequired - Reads the appropriate instruction table to determine whether
71 * the ModR/M byte is required to decode a particular instruction.
73 * @param type - The opcode type (i.e., how many bytes it has).
74 * @param insnContext - The context for the instruction, as returned by
76 * @param opcode - The last byte of the instruction's opcode, not counting
77 * ModR/M extensions and escapes.
78 * @return - true if the ModR/M byte is required, false otherwise.
80 static int modRMRequired(OpcodeType type,
81 InstructionContext insnContext,
83 const struct ContextDecision* decision = nullptr;
87 decision = &ONEBYTE_SYM;
90 decision = &TWOBYTE_SYM;
93 decision = &THREEBYTE38_SYM;
96 decision = &THREEBYTE3A_SYM;
99 decision = &XOP8_MAP_SYM;
102 decision = &XOP9_MAP_SYM;
105 decision = &XOPA_MAP_SYM;
109 return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
110 modrm_type != MODRM_ONEENTRY;
114 * decode - Reads the appropriate instruction table to obtain the unique ID of
117 * @param type - See modRMRequired().
118 * @param insnContext - See modRMRequired().
119 * @param opcode - See modRMRequired().
120 * @param modRM - The ModR/M byte if required, or any value if not.
121 * @return - The UID of the instruction, or 0 on failure.
123 static InstrUID decode(OpcodeType type,
124 InstructionContext insnContext,
127 const struct ModRMDecision* dec = nullptr;
131 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
134 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
137 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
140 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
143 dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
146 dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
149 dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
153 switch (dec->modrm_type) {
155 debug("Corrupt table! Unknown modrm_type");
158 return modRMTable[dec->instructionIDs];
160 if (modFromModRM(modRM) == 0x3)
161 return modRMTable[dec->instructionIDs+1];
162 return modRMTable[dec->instructionIDs];
164 if (modFromModRM(modRM) == 0x3)
165 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)+8];
166 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
167 case MODRM_SPLITMISC:
168 if (modFromModRM(modRM) == 0x3)
169 return modRMTable[dec->instructionIDs+(modRM & 0x3f)+8];
170 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
172 return modRMTable[dec->instructionIDs+modRM];
177 * specifierForUID - Given a UID, returns the name and operand specification for
180 * @param uid - The unique ID for the instruction. This should be returned by
181 * decode(); specifierForUID will not check bounds.
182 * @return - A pointer to the specification for that instruction.
184 static const struct InstructionSpecifier *specifierForUID(InstrUID uid) {
185 return &INSTRUCTIONS_SYM[uid];
189 * consumeByte - Uses the reader function provided by the user to consume one
190 * byte from the instruction's memory and advance the cursor.
192 * @param insn - The instruction with the reader function to use. The cursor
193 * for this instruction is advanced.
194 * @param byte - A pointer to a pre-allocated memory buffer to be populated
195 * with the data read.
196 * @return - 0 if the read was successful; nonzero otherwise.
198 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) {
199 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor);
202 ++(insn->readerCursor);
208 * lookAtByte - Like consumeByte, but does not advance the cursor.
210 * @param insn - See consumeByte().
211 * @param byte - See consumeByte().
212 * @return - See consumeByte().
214 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) {
215 return insn->reader(insn->readerArg, byte, insn->readerCursor);
218 static void unconsumeByte(struct InternalInstruction* insn) {
219 insn->readerCursor--;
222 #define CONSUME_FUNC(name, type) \
223 static int name(struct InternalInstruction* insn, type* ptr) { \
226 for (offset = 0; offset < sizeof(type); ++offset) { \
228 int ret = insn->reader(insn->readerArg, \
230 insn->readerCursor + offset); \
233 combined = combined | ((uint64_t)byte << (offset * 8)); \
236 insn->readerCursor += sizeof(type); \
241 * consume* - Use the reader function provided by the user to consume data
242 * values of various sizes from the instruction's memory and advance the
243 * cursor appropriately. These readers perform endian conversion.
245 * @param insn - See consumeByte().
246 * @param ptr - A pointer to a pre-allocated memory of appropriate size to
247 * be populated with the data read.
248 * @return - See consumeByte().
250 CONSUME_FUNC(consumeInt8, int8_t)
251 CONSUME_FUNC(consumeInt16, int16_t)
252 CONSUME_FUNC(consumeInt32, int32_t)
253 CONSUME_FUNC(consumeUInt16, uint16_t)
254 CONSUME_FUNC(consumeUInt32, uint32_t)
255 CONSUME_FUNC(consumeUInt64, uint64_t)
258 * dbgprintf - Uses the logging function provided by the user to log a single
259 * message, typically without a carriage-return.
261 * @param insn - The instruction containing the logging function.
262 * @param format - See printf().
263 * @param ... - See printf().
265 static void dbgprintf(struct InternalInstruction* insn,
274 va_start(ap, format);
275 (void)vsnprintf(buffer, sizeof(buffer), format, ap);
278 insn->dlog(insn->dlogArg, buffer);
284 * setPrefixPresent - Marks that a particular prefix is present at a particular
287 * @param insn - The instruction to be marked as having the prefix.
288 * @param prefix - The prefix that is present.
289 * @param location - The location where the prefix is located (in the address
290 * space of the instruction's reader).
292 static void setPrefixPresent(struct InternalInstruction* insn,
296 insn->prefixPresent[prefix] = 1;
297 insn->prefixLocations[prefix] = location;
301 * isPrefixAtLocation - Queries an instruction to determine whether a prefix is
302 * present at a given location.
304 * @param insn - The instruction to be queried.
305 * @param prefix - The prefix.
306 * @param location - The location to query.
307 * @return - Whether the prefix is at that location.
309 static bool isPrefixAtLocation(struct InternalInstruction* insn,
313 if (insn->prefixPresent[prefix] == 1 &&
314 insn->prefixLocations[prefix] == location)
321 * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the
322 * instruction as having them. Also sets the instruction's default operand,
323 * address, and other relevant data sizes to report operands correctly.
325 * @param insn - The instruction whose prefixes are to be read.
326 * @return - 0 if the instruction could be read until the end of the prefix
327 * bytes, and no prefixes conflicted; nonzero otherwise.
329 static int readPrefixes(struct InternalInstruction* insn) {
330 bool isPrefix = true;
331 bool prefixGroups[4] = { false };
332 uint64_t prefixLocation;
336 bool hasAdSize = false;
337 bool hasOpSize = false;
339 dbgprintf(insn, "readPrefixes()");
342 prefixLocation = insn->readerCursor;
344 /* If we fail reading prefixes, just stop here and let the opcode reader deal with it */
345 if (consumeByte(insn, &byte))
349 * If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
350 * break and let it be disassembled as a normal "instruction".
352 if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0)
355 if (insn->readerCursor - 1 == insn->startLocation
356 && (byte == 0xf2 || byte == 0xf3)
357 && !lookAtByte(insn, &nextByte))
360 * If the byte is 0xf2 or 0xf3, and any of the following conditions are
362 * - it is followed by a LOCK (0xf0) prefix
363 * - it is followed by an xchg instruction
364 * then it should be disassembled as a xacquire/xrelease not repne/rep.
366 if ((byte == 0xf2 || byte == 0xf3) &&
367 ((nextByte == 0xf0) |
368 ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90)))
369 insn->xAcquireRelease = true;
371 * Also if the byte is 0xf3, and the following condition is met:
372 * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
373 * "mov mem, imm" (opcode 0xc6/0xc7) instructions.
374 * then it should be disassembled as an xrelease not rep.
377 (nextByte == 0x88 || nextByte == 0x89 ||
378 nextByte == 0xc6 || nextByte == 0xc7))
379 insn->xAcquireRelease = true;
380 if (insn->mode == MODE_64BIT && (nextByte & 0xf0) == 0x40) {
381 if (consumeByte(insn, &nextByte))
383 if (lookAtByte(insn, &nextByte))
387 if (nextByte != 0x0f && nextByte != 0x90)
392 case 0xf0: /* LOCK */
393 case 0xf2: /* REPNE/REPNZ */
394 case 0xf3: /* REP or REPE/REPZ */
396 dbgprintf(insn, "Redundant Group 1 prefix");
397 prefixGroups[0] = true;
398 setPrefixPresent(insn, byte, prefixLocation);
400 case 0x2e: /* CS segment override -OR- Branch not taken */
401 case 0x36: /* SS segment override -OR- Branch taken */
402 case 0x3e: /* DS segment override */
403 case 0x26: /* ES segment override */
404 case 0x64: /* FS segment override */
405 case 0x65: /* GS segment override */
408 insn->segmentOverride = SEG_OVERRIDE_CS;
411 insn->segmentOverride = SEG_OVERRIDE_SS;
414 insn->segmentOverride = SEG_OVERRIDE_DS;
417 insn->segmentOverride = SEG_OVERRIDE_ES;
420 insn->segmentOverride = SEG_OVERRIDE_FS;
423 insn->segmentOverride = SEG_OVERRIDE_GS;
426 debug("Unhandled override");
430 dbgprintf(insn, "Redundant Group 2 prefix");
431 prefixGroups[1] = true;
432 setPrefixPresent(insn, byte, prefixLocation);
434 case 0x66: /* Operand-size override */
436 dbgprintf(insn, "Redundant Group 3 prefix");
437 prefixGroups[2] = true;
439 setPrefixPresent(insn, byte, prefixLocation);
441 case 0x67: /* Address-size override */
443 dbgprintf(insn, "Redundant Group 4 prefix");
444 prefixGroups[3] = true;
446 setPrefixPresent(insn, byte, prefixLocation);
448 default: /* Not a prefix byte */
454 dbgprintf(insn, "Found prefix 0x%hhx", byte);
457 insn->vectorExtensionType = TYPE_NO_VEX_XOP;
460 uint8_t byte1, byte2;
462 if (consumeByte(insn, &byte1)) {
463 dbgprintf(insn, "Couldn't read second byte of EVEX prefix");
467 if (lookAtByte(insn, &byte2)) {
468 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
472 if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) &&
473 ((~byte1 & 0xc) == 0xc) && ((byte2 & 0x4) == 0x4)) {
474 insn->vectorExtensionType = TYPE_EVEX;
477 unconsumeByte(insn); /* unconsume byte1 */
478 unconsumeByte(insn); /* unconsume byte */
479 insn->necessaryPrefixLocation = insn->readerCursor - 2;
482 if (insn->vectorExtensionType == TYPE_EVEX) {
483 insn->vectorExtensionPrefix[0] = byte;
484 insn->vectorExtensionPrefix[1] = byte1;
485 if (consumeByte(insn, &insn->vectorExtensionPrefix[2])) {
486 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
489 if (consumeByte(insn, &insn->vectorExtensionPrefix[3])) {
490 dbgprintf(insn, "Couldn't read fourth byte of EVEX prefix");
494 /* We simulate the REX prefix for simplicity's sake */
495 if (insn->mode == MODE_64BIT) {
496 insn->rexPrefix = 0x40
497 | (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3)
498 | (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2)
499 | (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1)
500 | (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0);
503 dbgprintf(insn, "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
504 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
505 insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]);
508 else if (byte == 0xc4) {
511 if (lookAtByte(insn, &byte1)) {
512 dbgprintf(insn, "Couldn't read second byte of VEX");
516 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
517 insn->vectorExtensionType = TYPE_VEX_3B;
518 insn->necessaryPrefixLocation = insn->readerCursor - 1;
522 insn->necessaryPrefixLocation = insn->readerCursor - 1;
525 if (insn->vectorExtensionType == TYPE_VEX_3B) {
526 insn->vectorExtensionPrefix[0] = byte;
527 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
528 consumeByte(insn, &insn->vectorExtensionPrefix[2]);
530 /* We simulate the REX prefix for simplicity's sake */
532 if (insn->mode == MODE_64BIT) {
533 insn->rexPrefix = 0x40
534 | (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3)
535 | (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2)
536 | (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1)
537 | (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0);
540 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx",
541 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
542 insn->vectorExtensionPrefix[2]);
545 else if (byte == 0xc5) {
548 if (lookAtByte(insn, &byte1)) {
549 dbgprintf(insn, "Couldn't read second byte of VEX");
553 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
554 insn->vectorExtensionType = TYPE_VEX_2B;
560 if (insn->vectorExtensionType == TYPE_VEX_2B) {
561 insn->vectorExtensionPrefix[0] = byte;
562 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
564 if (insn->mode == MODE_64BIT) {
565 insn->rexPrefix = 0x40
566 | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2);
569 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1]))
578 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx",
579 insn->vectorExtensionPrefix[0],
580 insn->vectorExtensionPrefix[1]);
583 else if (byte == 0x8f) {
586 if (lookAtByte(insn, &byte1)) {
587 dbgprintf(insn, "Couldn't read second byte of XOP");
591 if ((byte1 & 0x38) != 0x0) { /* 0 in these 3 bits is a POP instruction. */
592 insn->vectorExtensionType = TYPE_XOP;
593 insn->necessaryPrefixLocation = insn->readerCursor - 1;
597 insn->necessaryPrefixLocation = insn->readerCursor - 1;
600 if (insn->vectorExtensionType == TYPE_XOP) {
601 insn->vectorExtensionPrefix[0] = byte;
602 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
603 consumeByte(insn, &insn->vectorExtensionPrefix[2]);
605 /* We simulate the REX prefix for simplicity's sake */
607 if (insn->mode == MODE_64BIT) {
608 insn->rexPrefix = 0x40
609 | (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3)
610 | (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2)
611 | (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1)
612 | (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0);
615 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2]))
624 dbgprintf(insn, "Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
625 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
626 insn->vectorExtensionPrefix[2]);
630 if (insn->mode == MODE_64BIT) {
631 if ((byte & 0xf0) == 0x40) {
634 if (lookAtByte(insn, &opcodeByte) || ((opcodeByte & 0xf0) == 0x40)) {
635 dbgprintf(insn, "Redundant REX prefix");
639 insn->rexPrefix = byte;
640 insn->necessaryPrefixLocation = insn->readerCursor - 2;
642 dbgprintf(insn, "Found REX prefix 0x%hhx", byte);
645 insn->necessaryPrefixLocation = insn->readerCursor - 1;
649 insn->necessaryPrefixLocation = insn->readerCursor - 1;
653 if (insn->mode == MODE_16BIT) {
654 insn->registerSize = (hasOpSize ? 4 : 2);
655 insn->addressSize = (hasAdSize ? 4 : 2);
656 insn->displacementSize = (hasAdSize ? 4 : 2);
657 insn->immediateSize = (hasOpSize ? 4 : 2);
658 } else if (insn->mode == MODE_32BIT) {
659 insn->registerSize = (hasOpSize ? 2 : 4);
660 insn->addressSize = (hasAdSize ? 2 : 4);
661 insn->displacementSize = (hasAdSize ? 2 : 4);
662 insn->immediateSize = (hasOpSize ? 2 : 4);
663 } else if (insn->mode == MODE_64BIT) {
664 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
665 insn->registerSize = 8;
666 insn->addressSize = (hasAdSize ? 4 : 8);
667 insn->displacementSize = 4;
668 insn->immediateSize = 4;
669 } else if (insn->rexPrefix) {
670 insn->registerSize = (hasOpSize ? 2 : 4);
671 insn->addressSize = (hasAdSize ? 4 : 8);
672 insn->displacementSize = (hasOpSize ? 2 : 4);
673 insn->immediateSize = (hasOpSize ? 2 : 4);
675 insn->registerSize = (hasOpSize ? 2 : 4);
676 insn->addressSize = (hasAdSize ? 4 : 8);
677 insn->displacementSize = (hasOpSize ? 2 : 4);
678 insn->immediateSize = (hasOpSize ? 2 : 4);
686 * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of
687 * extended or escape opcodes).
689 * @param insn - The instruction whose opcode is to be read.
690 * @return - 0 if the opcode could be read successfully; nonzero otherwise.
692 static int readOpcode(struct InternalInstruction* insn) {
693 /* Determine the length of the primary opcode */
697 dbgprintf(insn, "readOpcode()");
699 insn->opcodeType = ONEBYTE;
701 if (insn->vectorExtensionType == TYPE_EVEX)
703 switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) {
705 dbgprintf(insn, "Unhandled mm field for instruction (0x%hhx)",
706 mmFromEVEX2of4(insn->vectorExtensionPrefix[1]));
709 insn->opcodeType = TWOBYTE;
710 return consumeByte(insn, &insn->opcode);
712 insn->opcodeType = THREEBYTE_38;
713 return consumeByte(insn, &insn->opcode);
715 insn->opcodeType = THREEBYTE_3A;
716 return consumeByte(insn, &insn->opcode);
719 else if (insn->vectorExtensionType == TYPE_VEX_3B) {
720 switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
722 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
723 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
726 insn->opcodeType = TWOBYTE;
727 return consumeByte(insn, &insn->opcode);
729 insn->opcodeType = THREEBYTE_38;
730 return consumeByte(insn, &insn->opcode);
732 insn->opcodeType = THREEBYTE_3A;
733 return consumeByte(insn, &insn->opcode);
736 else if (insn->vectorExtensionType == TYPE_VEX_2B) {
737 insn->opcodeType = TWOBYTE;
738 return consumeByte(insn, &insn->opcode);
740 else if (insn->vectorExtensionType == TYPE_XOP) {
741 switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) {
743 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
744 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
746 case XOP_MAP_SELECT_8:
747 insn->opcodeType = XOP8_MAP;
748 return consumeByte(insn, &insn->opcode);
749 case XOP_MAP_SELECT_9:
750 insn->opcodeType = XOP9_MAP;
751 return consumeByte(insn, &insn->opcode);
752 case XOP_MAP_SELECT_A:
753 insn->opcodeType = XOPA_MAP;
754 return consumeByte(insn, &insn->opcode);
758 if (consumeByte(insn, ¤t))
761 if (current == 0x0f) {
762 dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current);
764 if (consumeByte(insn, ¤t))
767 if (current == 0x38) {
768 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
770 if (consumeByte(insn, ¤t))
773 insn->opcodeType = THREEBYTE_38;
774 } else if (current == 0x3a) {
775 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
777 if (consumeByte(insn, ¤t))
780 insn->opcodeType = THREEBYTE_3A;
782 dbgprintf(insn, "Didn't find a three-byte escape prefix");
784 insn->opcodeType = TWOBYTE;
789 * At this point we have consumed the full opcode.
790 * Anything we consume from here on must be unconsumed.
793 insn->opcode = current;
798 static int readModRM(struct InternalInstruction* insn);
801 * getIDWithAttrMask - Determines the ID of an instruction, consuming
802 * the ModR/M byte as appropriate for extended and escape opcodes,
803 * and using a supplied attribute mask.
805 * @param instructionID - A pointer whose target is filled in with the ID of the
807 * @param insn - The instruction whose ID is to be determined.
808 * @param attrMask - The attribute mask to search.
809 * @return - 0 if the ModR/M could be read when needed or was not
810 * needed; nonzero otherwise.
812 static int getIDWithAttrMask(uint16_t* instructionID,
813 struct InternalInstruction* insn,
815 bool hasModRMExtension;
817 InstructionContext instructionClass = contextForAttrs(attrMask);
819 hasModRMExtension = modRMRequired(insn->opcodeType,
823 if (hasModRMExtension) {
827 *instructionID = decode(insn->opcodeType,
832 *instructionID = decode(insn->opcodeType,
842 * is16BitEquivalent - Determines whether two instruction names refer to
843 * equivalent instructions but one is 16-bit whereas the other is not.
845 * @param orig - The instruction that is not 16-bit
846 * @param equiv - The instruction that is 16-bit
848 static bool is16BitEquivalent(const char* orig, const char* equiv) {
852 if (orig[i] == '\0' && equiv[i] == '\0')
854 if (orig[i] == '\0' || equiv[i] == '\0')
856 if (orig[i] != equiv[i]) {
857 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
859 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
861 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
869 * getID - Determines the ID of an instruction, consuming the ModR/M byte as
870 * appropriate for extended and escape opcodes. Determines the attributes and
871 * context for the instruction before doing so.
873 * @param insn - The instruction whose ID is to be determined.
874 * @return - 0 if the ModR/M could be read when needed or was not needed;
877 static int getID(struct InternalInstruction* insn, const void *miiArg) {
879 uint16_t instructionID;
881 dbgprintf(insn, "getID()");
883 attrMask = ATTR_NONE;
885 if (insn->mode == MODE_64BIT)
886 attrMask |= ATTR_64BIT;
888 if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) {
889 attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX;
891 if (insn->vectorExtensionType == TYPE_EVEX) {
892 switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) {
894 attrMask |= ATTR_OPSIZE;
904 if (zFromEVEX4of4(insn->vectorExtensionPrefix[3]))
905 attrMask |= ATTR_EVEXKZ;
906 if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
907 attrMask |= ATTR_EVEXB;
908 if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]))
909 attrMask |= ATTR_EVEXK;
910 if (lFromEVEX4of4(insn->vectorExtensionPrefix[3]))
911 attrMask |= ATTR_EVEXL;
912 if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]))
913 attrMask |= ATTR_EVEXL2;
915 else if (insn->vectorExtensionType == TYPE_VEX_3B) {
916 switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) {
918 attrMask |= ATTR_OPSIZE;
928 if (lFromVEX3of3(insn->vectorExtensionPrefix[2]))
929 attrMask |= ATTR_VEXL;
931 else if (insn->vectorExtensionType == TYPE_VEX_2B) {
932 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
934 attrMask |= ATTR_OPSIZE;
944 if (lFromVEX2of2(insn->vectorExtensionPrefix[1]))
945 attrMask |= ATTR_VEXL;
947 else if (insn->vectorExtensionType == TYPE_XOP) {
948 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
950 attrMask |= ATTR_OPSIZE;
960 if (lFromXOP3of3(insn->vectorExtensionPrefix[2]))
961 attrMask |= ATTR_VEXL;
968 if (insn->mode != MODE_16BIT && isPrefixAtLocation(insn, 0x66, insn->necessaryPrefixLocation))
969 attrMask |= ATTR_OPSIZE;
970 else if (isPrefixAtLocation(insn, 0x67, insn->necessaryPrefixLocation))
971 attrMask |= ATTR_ADSIZE;
972 else if (isPrefixAtLocation(insn, 0xf3, insn->necessaryPrefixLocation))
974 else if (isPrefixAtLocation(insn, 0xf2, insn->necessaryPrefixLocation))
978 if (insn->rexPrefix & 0x08)
979 attrMask |= ATTR_REXW;
981 if (getIDWithAttrMask(&instructionID, insn, attrMask))
985 * JCXZ/JECXZ need special handling for 16-bit mode because the meaning
986 * of the AdSize prefix is inverted w.r.t. 32-bit mode.
988 if (insn->mode == MODE_16BIT && insn->opcode == 0xE3) {
989 const struct InstructionSpecifier *spec;
990 spec = specifierForUID(instructionID);
993 * Check for Ii8PCRel instructions. We could alternatively do a
994 * string-compare on the names, but this is probably cheaper.
996 if (x86OperandSets[spec->operands][0].type == TYPE_REL8) {
997 attrMask ^= ATTR_ADSIZE;
998 if (getIDWithAttrMask(&instructionID, insn, attrMask))
1003 /* The following clauses compensate for limitations of the tables. */
1005 if ((insn->mode == MODE_16BIT || insn->prefixPresent[0x66]) &&
1006 !(attrMask & ATTR_OPSIZE)) {
1008 * The instruction tables make no distinction between instructions that
1009 * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
1010 * particular spot (i.e., many MMX operations). In general we're
1011 * conservative, but in the specific case where OpSize is present but not
1012 * in the right place we check if there's a 16-bit operation.
1015 const struct InstructionSpecifier *spec;
1016 uint16_t instructionIDWithOpsize;
1017 const char *specName, *specWithOpSizeName;
1019 spec = specifierForUID(instructionID);
1021 if (getIDWithAttrMask(&instructionIDWithOpsize,
1023 attrMask | ATTR_OPSIZE)) {
1025 * ModRM required with OpSize but not present; give up and return version
1026 * without OpSize set
1029 insn->instructionID = instructionID;
1034 specName = GetInstrName(instructionID, miiArg);
1035 specWithOpSizeName = GetInstrName(instructionIDWithOpsize, miiArg);
1037 if (is16BitEquivalent(specName, specWithOpSizeName) &&
1038 (insn->mode == MODE_16BIT) ^ insn->prefixPresent[0x66]) {
1039 insn->instructionID = instructionIDWithOpsize;
1040 insn->spec = specifierForUID(instructionIDWithOpsize);
1042 insn->instructionID = instructionID;
1048 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
1049 insn->rexPrefix & 0x01) {
1051 * NOOP shouldn't decode as NOOP if REX.b is set. Instead
1052 * it should decode as XCHG %r8, %eax.
1055 const struct InstructionSpecifier *spec;
1056 uint16_t instructionIDWithNewOpcode;
1057 const struct InstructionSpecifier *specWithNewOpcode;
1059 spec = specifierForUID(instructionID);
1061 /* Borrow opcode from one of the other XCHGar opcodes */
1062 insn->opcode = 0x91;
1064 if (getIDWithAttrMask(&instructionIDWithNewOpcode,
1067 insn->opcode = 0x90;
1069 insn->instructionID = instructionID;
1074 specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode);
1077 insn->opcode = 0x90;
1079 insn->instructionID = instructionIDWithNewOpcode;
1080 insn->spec = specWithNewOpcode;
1085 insn->instructionID = instructionID;
1086 insn->spec = specifierForUID(insn->instructionID);
1092 * readSIB - Consumes the SIB byte to determine addressing information for an
1095 * @param insn - The instruction whose SIB byte is to be read.
1096 * @return - 0 if the SIB byte was successfully read; nonzero otherwise.
1098 static int readSIB(struct InternalInstruction* insn) {
1099 SIBIndex sibIndexBase = SIB_INDEX_NONE;
1100 SIBBase sibBaseBase = SIB_BASE_NONE;
1101 uint8_t index, base;
1103 dbgprintf(insn, "readSIB()");
1105 if (insn->consumedSIB)
1108 insn->consumedSIB = true;
1110 switch (insn->addressSize) {
1112 dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode");
1115 sibIndexBase = SIB_INDEX_EAX;
1116 sibBaseBase = SIB_BASE_EAX;
1119 sibIndexBase = SIB_INDEX_RAX;
1120 sibBaseBase = SIB_BASE_RAX;
1124 if (consumeByte(insn, &insn->sib))
1127 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3);
1128 if (insn->vectorExtensionType == TYPE_EVEX)
1129 index |= v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4;
1133 insn->sibIndex = SIB_INDEX_NONE;
1136 insn->sibIndex = (SIBIndex)(sibIndexBase + index);
1137 if (insn->sibIndex == SIB_INDEX_sib ||
1138 insn->sibIndex == SIB_INDEX_sib64)
1139 insn->sibIndex = SIB_INDEX_NONE;
1143 switch (scaleFromSIB(insn->sib)) {
1158 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3);
1163 switch (modFromModRM(insn->modRM)) {
1165 insn->eaDisplacement = EA_DISP_32;
1166 insn->sibBase = SIB_BASE_NONE;
1169 insn->eaDisplacement = EA_DISP_8;
1170 insn->sibBase = (SIBBase)(sibBaseBase + base);
1173 insn->eaDisplacement = EA_DISP_32;
1174 insn->sibBase = (SIBBase)(sibBaseBase + base);
1177 debug("Cannot have Mod = 0b11 and a SIB byte");
1182 insn->sibBase = (SIBBase)(sibBaseBase + base);
1190 * readDisplacement - Consumes the displacement of an instruction.
1192 * @param insn - The instruction whose displacement is to be read.
1193 * @return - 0 if the displacement byte was successfully read; nonzero
1196 static int readDisplacement(struct InternalInstruction* insn) {
1201 dbgprintf(insn, "readDisplacement()");
1203 if (insn->consumedDisplacement)
1206 insn->consumedDisplacement = true;
1207 insn->displacementOffset = insn->readerCursor - insn->startLocation;
1209 switch (insn->eaDisplacement) {
1211 insn->consumedDisplacement = false;
1214 if (consumeInt8(insn, &d8))
1216 insn->displacement = d8;
1219 if (consumeInt16(insn, &d16))
1221 insn->displacement = d16;
1224 if (consumeInt32(insn, &d32))
1226 insn->displacement = d32;
1230 insn->consumedDisplacement = true;
1235 * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and
1236 * displacement) for an instruction and interprets it.
1238 * @param insn - The instruction whose addressing information is to be read.
1239 * @return - 0 if the information was successfully read; nonzero otherwise.
1241 static int readModRM(struct InternalInstruction* insn) {
1242 uint8_t mod, rm, reg;
1244 dbgprintf(insn, "readModRM()");
1246 if (insn->consumedModRM)
1249 if (consumeByte(insn, &insn->modRM))
1251 insn->consumedModRM = true;
1253 mod = modFromModRM(insn->modRM);
1254 rm = rmFromModRM(insn->modRM);
1255 reg = regFromModRM(insn->modRM);
1258 * This goes by insn->registerSize to pick the correct register, which messes
1259 * up if we're using (say) XMM or 8-bit register operands. That gets fixed in
1262 switch (insn->registerSize) {
1264 insn->regBase = MODRM_REG_AX;
1265 insn->eaRegBase = EA_REG_AX;
1268 insn->regBase = MODRM_REG_EAX;
1269 insn->eaRegBase = EA_REG_EAX;
1272 insn->regBase = MODRM_REG_RAX;
1273 insn->eaRegBase = EA_REG_RAX;
1277 reg |= rFromREX(insn->rexPrefix) << 3;
1278 rm |= bFromREX(insn->rexPrefix) << 3;
1279 if (insn->vectorExtensionType == TYPE_EVEX) {
1280 reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1281 rm |= xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1284 insn->reg = (Reg)(insn->regBase + reg);
1286 switch (insn->addressSize) {
1288 insn->eaBaseBase = EA_BASE_BX_SI;
1293 insn->eaBase = EA_BASE_NONE;
1294 insn->eaDisplacement = EA_DISP_16;
1295 if (readDisplacement(insn))
1298 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1299 insn->eaDisplacement = EA_DISP_NONE;
1303 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1304 insn->eaDisplacement = EA_DISP_8;
1305 insn->displacementSize = 1;
1306 if (readDisplacement(insn))
1310 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1311 insn->eaDisplacement = EA_DISP_16;
1312 if (readDisplacement(insn))
1316 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1317 if (readDisplacement(insn))
1324 insn->eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
1328 insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */
1332 case 0xc: /* in case REXW.b is set */
1333 insn->eaBase = (insn->addressSize == 4 ?
1334 EA_BASE_sib : EA_BASE_sib64);
1335 if (readSIB(insn) || readDisplacement(insn))
1339 insn->eaBase = EA_BASE_NONE;
1340 insn->eaDisplacement = EA_DISP_32;
1341 if (readDisplacement(insn))
1345 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1350 insn->displacementSize = 1;
1353 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
1357 case 0xc: /* in case REXW.b is set */
1358 insn->eaBase = EA_BASE_sib;
1359 if (readSIB(insn) || readDisplacement(insn))
1363 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1364 if (readDisplacement(insn))
1370 insn->eaDisplacement = EA_DISP_NONE;
1371 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1375 } /* switch (insn->addressSize) */
1380 #define GENERIC_FIXUP_FUNC(name, base, prefix) \
1381 static uint8_t name(struct InternalInstruction *insn, \
1388 debug("Unhandled register type"); \
1392 return base + index; \
1394 if (insn->rexPrefix && \
1395 index >= 4 && index <= 7) { \
1396 return prefix##_SPL + (index - 4); \
1398 return prefix##_AL + index; \
1401 return prefix##_AX + index; \
1403 return prefix##_EAX + index; \
1405 return prefix##_RAX + index; \
1407 return prefix##_ZMM0 + index; \
1409 return prefix##_YMM0 + index; \
1414 return prefix##_XMM0 + index; \
1418 return prefix##_K0 + index; \
1424 return prefix##_MM0 + index; \
1425 case TYPE_SEGMENTREG: \
1428 return prefix##_ES + index; \
1429 case TYPE_DEBUGREG: \
1432 return prefix##_DR0 + index; \
1433 case TYPE_CONTROLREG: \
1436 return prefix##_CR0 + index; \
1441 * fixup*Value - Consults an operand type to determine the meaning of the
1442 * reg or R/M field. If the operand is an XMM operand, for example, an
1443 * operand would be XMM0 instead of AX, which readModRM() would otherwise
1444 * misinterpret it as.
1446 * @param insn - The instruction containing the operand.
1447 * @param type - The operand type.
1448 * @param index - The existing value of the field as reported by readModRM().
1449 * @param valid - The address of a uint8_t. The target is set to 1 if the
1450 * field is valid for the register class; 0 if not.
1451 * @return - The proper value.
1453 GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG)
1454 GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
1457 * fixupReg - Consults an operand specifier to determine which of the
1458 * fixup*Value functions to use in correcting readModRM()'ss interpretation.
1460 * @param insn - See fixup*Value().
1461 * @param op - The operand specifier.
1462 * @return - 0 if fixup was successful; -1 if the register returned was
1463 * invalid for its class.
1465 static int fixupReg(struct InternalInstruction *insn,
1466 const struct OperandSpecifier *op) {
1469 dbgprintf(insn, "fixupReg()");
1471 switch ((OperandEncoding)op->encoding) {
1473 debug("Expected a REG or R/M encoding in fixupReg");
1476 insn->vvvv = (Reg)fixupRegValue(insn,
1477 (OperandType)op->type,
1484 insn->reg = (Reg)fixupRegValue(insn,
1485 (OperandType)op->type,
1486 insn->reg - insn->regBase,
1492 if (insn->eaBase >= insn->eaRegBase) {
1493 insn->eaBase = (EABase)fixupRMValue(insn,
1494 (OperandType)op->type,
1495 insn->eaBase - insn->eaRegBase,
1507 * readOpcodeRegister - Reads an operand from the opcode field of an
1508 * instruction and interprets it appropriately given the operand width.
1509 * Handles AddRegFrm instructions.
1511 * @param insn - the instruction whose opcode field is to be read.
1512 * @param size - The width (in bytes) of the register being specified.
1513 * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1515 * @return - 0 on success; nonzero otherwise.
1517 static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
1518 dbgprintf(insn, "readOpcodeRegister()");
1521 size = insn->registerSize;
1525 insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3)
1526 | (insn->opcode & 7)));
1527 if (insn->rexPrefix &&
1528 insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1529 insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1530 insn->opcodeRegister = (Reg)(MODRM_REG_SPL
1531 + (insn->opcodeRegister - MODRM_REG_AL - 4));
1536 insn->opcodeRegister = (Reg)(MODRM_REG_AX
1537 + ((bFromREX(insn->rexPrefix) << 3)
1538 | (insn->opcode & 7)));
1541 insn->opcodeRegister = (Reg)(MODRM_REG_EAX
1542 + ((bFromREX(insn->rexPrefix) << 3)
1543 | (insn->opcode & 7)));
1546 insn->opcodeRegister = (Reg)(MODRM_REG_RAX
1547 + ((bFromREX(insn->rexPrefix) << 3)
1548 | (insn->opcode & 7)));
1556 * readImmediate - Consumes an immediate operand from an instruction, given the
1557 * desired operand size.
1559 * @param insn - The instruction whose operand is to be read.
1560 * @param size - The width (in bytes) of the operand.
1561 * @return - 0 if the immediate was successfully consumed; nonzero
1564 static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
1570 dbgprintf(insn, "readImmediate()");
1572 if (insn->numImmediatesConsumed == 2) {
1573 debug("Already consumed two immediates");
1578 size = insn->immediateSize;
1580 insn->immediateSize = size;
1581 insn->immediateOffset = insn->readerCursor - insn->startLocation;
1585 if (consumeByte(insn, &imm8))
1587 insn->immediates[insn->numImmediatesConsumed] = imm8;
1590 if (consumeUInt16(insn, &imm16))
1592 insn->immediates[insn->numImmediatesConsumed] = imm16;
1595 if (consumeUInt32(insn, &imm32))
1597 insn->immediates[insn->numImmediatesConsumed] = imm32;
1600 if (consumeUInt64(insn, &imm64))
1602 insn->immediates[insn->numImmediatesConsumed] = imm64;
1606 insn->numImmediatesConsumed++;
1612 * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix.
1614 * @param insn - The instruction whose operand is to be read.
1615 * @return - 0 if the vvvv was successfully consumed; nonzero
1618 static int readVVVV(struct InternalInstruction* insn) {
1619 dbgprintf(insn, "readVVVV()");
1622 if (insn->vectorExtensionType == TYPE_EVEX)
1623 vvvv = vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]);
1624 else if (insn->vectorExtensionType == TYPE_VEX_3B)
1625 vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
1626 else if (insn->vectorExtensionType == TYPE_VEX_2B)
1627 vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
1628 else if (insn->vectorExtensionType == TYPE_XOP)
1629 vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
1633 if (insn->mode != MODE_64BIT)
1636 insn->vvvv = static_cast<Reg>(vvvv);
1641 * readMaskRegister - Reads an mask register from the opcode field of an
1644 * @param insn - The instruction whose opcode field is to be read.
1645 * @return - 0 on success; nonzero otherwise.
1647 static int readMaskRegister(struct InternalInstruction* insn) {
1648 dbgprintf(insn, "readMaskRegister()");
1650 if (insn->vectorExtensionType != TYPE_EVEX)
1654 static_cast<Reg>(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]));
1659 * readOperands - Consults the specifier for an instruction and consumes all
1660 * operands for that instruction, interpreting them as it goes.
1662 * @param insn - The instruction whose operands are to be read and interpreted.
1663 * @return - 0 if all operands could be read; nonzero otherwise.
1665 static int readOperands(struct InternalInstruction* insn) {
1666 int hasVVVV, needVVVV;
1669 dbgprintf(insn, "readOperands()");
1671 /* If non-zero vvvv specified, need to make sure one of the operands
1673 hasVVVV = !readVVVV(insn);
1674 needVVVV = hasVVVV && (insn->vvvv != 0);
1676 for (const auto &Op : x86OperandSets[insn->spec->operands]) {
1677 switch (Op.encoding) {
1684 if (readModRM(insn))
1686 if (fixupReg(insn, &Op))
1695 dbgprintf(insn, "We currently don't hande code-offset encodings");
1699 /* Saw a register immediate so don't read again and instead split the
1700 previous immediate. FIXME: This is a hack. */
1701 insn->immediates[insn->numImmediatesConsumed] =
1702 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1703 ++insn->numImmediatesConsumed;
1706 if (readImmediate(insn, 1))
1708 if (Op.type == TYPE_IMM3 &&
1709 insn->immediates[insn->numImmediatesConsumed - 1] > 7)
1711 if (Op.type == TYPE_IMM5 &&
1712 insn->immediates[insn->numImmediatesConsumed - 1] > 31)
1714 if (Op.type == TYPE_XMM128 ||
1715 Op.type == TYPE_XMM256)
1719 if (readImmediate(insn, 2))
1723 if (readImmediate(insn, 4))
1727 if (readImmediate(insn, 8))
1731 if (readImmediate(insn, insn->immediateSize))
1735 if (readImmediate(insn, insn->addressSize))
1739 if (readOpcodeRegister(insn, 1))
1743 if (readOpcodeRegister(insn, 2))
1747 if (readOpcodeRegister(insn, 4))
1751 if (readOpcodeRegister(insn, 8))
1755 if (readOpcodeRegister(insn, 0))
1761 needVVVV = 0; /* Mark that we have found a VVVV operand. */
1764 if (fixupReg(insn, &Op))
1767 case ENCODING_WRITEMASK:
1768 if (readMaskRegister(insn))
1774 dbgprintf(insn, "Encountered an operand with an unknown encoding.");
1779 /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */
1780 if (needVVVV) return -1;
1786 * decodeInstruction - Reads and interprets a full instruction provided by the
1789 * @param insn - A pointer to the instruction to be populated. Must be
1791 * @param reader - The function to be used to read the instruction's bytes.
1792 * @param readerArg - A generic argument to be passed to the reader to store
1793 * any internal state.
1794 * @param logger - If non-NULL, the function to be used to write log messages
1796 * @param loggerArg - A generic argument to be passed to the logger to store
1797 * any internal state.
1798 * @param startLoc - The address (in the reader's address space) of the first
1799 * byte in the instruction.
1800 * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to
1801 * decode the instruction in.
1802 * @return - 0 if the instruction's memory could be read; nonzero if
1805 int llvm::X86Disassembler::decodeInstruction(
1806 struct InternalInstruction *insn, byteReader_t reader,
1807 const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg,
1808 uint64_t startLoc, DisassemblerMode mode) {
1809 memset(insn, 0, sizeof(struct InternalInstruction));
1811 insn->reader = reader;
1812 insn->readerArg = readerArg;
1813 insn->dlog = logger;
1814 insn->dlogArg = loggerArg;
1815 insn->startLocation = startLoc;
1816 insn->readerCursor = startLoc;
1818 insn->numImmediatesConsumed = 0;
1820 if (readPrefixes(insn) ||
1822 getID(insn, miiArg) ||
1823 insn->instructionID == 0 ||
1827 insn->operands = x86OperandSets[insn->spec->operands];
1829 insn->length = insn->readerCursor - insn->startLocation;
1831 dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu",
1832 startLoc, insn->readerCursor, insn->length);
1834 if (insn->length > 15)
1835 dbgprintf(insn, "Instruction exceeds 15-byte limit");