1 //===-- X86DisassemblerDecoder.c - Disassembler decoder -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler.
11 // It contains the implementation of the instruction decoder.
12 // Documentation for the disassembler can be found in X86Disassembler.h.
14 //===----------------------------------------------------------------------===//
16 #include <stdarg.h> /* for va_*() */
17 #include <stdio.h> /* for vsnprintf() */
18 #include <stdlib.h> /* for exit() */
19 #include <string.h> /* for memset() */
21 #include "X86DisassemblerDecoder.h"
23 using namespace llvm::X86Disassembler;
25 /// Specifies whether a ModR/M byte is needed and (if so) which
26 /// instruction each possible value of the ModR/M byte corresponds to. Once
27 /// this information is known, we have narrowed down to a single instruction.
28 struct ModRMDecision {
30 uint16_t instructionIDs;
33 /// Specifies which set of ModR/M->instruction tables to look at
34 /// given a particular opcode.
35 struct OpcodeDecision {
36 ModRMDecision modRMDecisions[256];
39 /// Specifies which opcode->instruction tables to look at given
40 /// a particular context (set of attributes). Since there are many possible
41 /// contexts, the decoder first uses CONTEXTS_SYM to determine which context
42 /// applies given a specific set of attributes. Hence there are only IC_max
43 /// entries in this table, rather than 2^(ATTR_max).
44 struct ContextDecision {
45 OpcodeDecision opcodeDecisions[IC_max];
48 #include "X86GenDisassemblerTables.inc"
54 #define debug(s) do { Debug(__FILE__, __LINE__, s); } while (0)
56 #define debug(s) do { } while (0)
61 * contextForAttrs - Client for the instruction context table. Takes a set of
62 * attributes and returns the appropriate decode context.
64 * @param attrMask - Attributes, from the enumeration attributeBits.
65 * @return - The InstructionContext to use when looking up an
66 * an instruction with these attributes.
68 static InstructionContext contextForAttrs(uint16_t attrMask) {
69 return static_cast<InstructionContext>(CONTEXTS_SYM[attrMask]);
73 * modRMRequired - Reads the appropriate instruction table to determine whether
74 * the ModR/M byte is required to decode a particular instruction.
76 * @param type - The opcode type (i.e., how many bytes it has).
77 * @param insnContext - The context for the instruction, as returned by
79 * @param opcode - The last byte of the instruction's opcode, not counting
80 * ModR/M extensions and escapes.
81 * @return - TRUE if the ModR/M byte is required, FALSE otherwise.
83 static int modRMRequired(OpcodeType type,
84 InstructionContext insnContext,
86 const struct ContextDecision* decision = 0;
90 decision = &ONEBYTE_SYM;
93 decision = &TWOBYTE_SYM;
96 decision = &THREEBYTE38_SYM;
99 decision = &THREEBYTE3A_SYM;
102 decision = &XOP8_MAP_SYM;
105 decision = &XOP9_MAP_SYM;
108 decision = &XOPA_MAP_SYM;
112 return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
113 modrm_type != MODRM_ONEENTRY;
117 * decode - Reads the appropriate instruction table to obtain the unique ID of
120 * @param type - See modRMRequired().
121 * @param insnContext - See modRMRequired().
122 * @param opcode - See modRMRequired().
123 * @param modRM - The ModR/M byte if required, or any value if not.
124 * @return - The UID of the instruction, or 0 on failure.
126 static InstrUID decode(OpcodeType type,
127 InstructionContext insnContext,
130 const struct ModRMDecision* dec = 0;
134 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
137 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
140 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
143 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
146 dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
149 dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
152 dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
156 switch (dec->modrm_type) {
158 debug("Corrupt table! Unknown modrm_type");
161 return modRMTable[dec->instructionIDs];
163 if (modFromModRM(modRM) == 0x3)
164 return modRMTable[dec->instructionIDs+1];
165 return modRMTable[dec->instructionIDs];
167 if (modFromModRM(modRM) == 0x3)
168 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)+8];
169 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
170 case MODRM_SPLITMISC:
171 if (modFromModRM(modRM) == 0x3)
172 return modRMTable[dec->instructionIDs+(modRM & 0x3f)+8];
173 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
175 return modRMTable[dec->instructionIDs+modRM];
180 * specifierForUID - Given a UID, returns the name and operand specification for
183 * @param uid - The unique ID for the instruction. This should be returned by
184 * decode(); specifierForUID will not check bounds.
185 * @return - A pointer to the specification for that instruction.
187 static const struct InstructionSpecifier *specifierForUID(InstrUID uid) {
188 return &INSTRUCTIONS_SYM[uid];
192 * consumeByte - Uses the reader function provided by the user to consume one
193 * byte from the instruction's memory and advance the cursor.
195 * @param insn - The instruction with the reader function to use. The cursor
196 * for this instruction is advanced.
197 * @param byte - A pointer to a pre-allocated memory buffer to be populated
198 * with the data read.
199 * @return - 0 if the read was successful; nonzero otherwise.
201 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) {
202 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor);
205 ++(insn->readerCursor);
211 * lookAtByte - Like consumeByte, but does not advance the cursor.
213 * @param insn - See consumeByte().
214 * @param byte - See consumeByte().
215 * @return - See consumeByte().
217 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) {
218 return insn->reader(insn->readerArg, byte, insn->readerCursor);
221 static void unconsumeByte(struct InternalInstruction* insn) {
222 insn->readerCursor--;
225 #define CONSUME_FUNC(name, type) \
226 static int name(struct InternalInstruction* insn, type* ptr) { \
229 for (offset = 0; offset < sizeof(type); ++offset) { \
231 int ret = insn->reader(insn->readerArg, \
233 insn->readerCursor + offset); \
236 combined = combined | ((uint64_t)byte << (offset * 8)); \
239 insn->readerCursor += sizeof(type); \
244 * consume* - Use the reader function provided by the user to consume data
245 * values of various sizes from the instruction's memory and advance the
246 * cursor appropriately. These readers perform endian conversion.
248 * @param insn - See consumeByte().
249 * @param ptr - A pointer to a pre-allocated memory of appropriate size to
250 * be populated with the data read.
251 * @return - See consumeByte().
253 CONSUME_FUNC(consumeInt8, int8_t)
254 CONSUME_FUNC(consumeInt16, int16_t)
255 CONSUME_FUNC(consumeInt32, int32_t)
256 CONSUME_FUNC(consumeUInt16, uint16_t)
257 CONSUME_FUNC(consumeUInt32, uint32_t)
258 CONSUME_FUNC(consumeUInt64, uint64_t)
261 * dbgprintf - Uses the logging function provided by the user to log a single
262 * message, typically without a carriage-return.
264 * @param insn - The instruction containing the logging function.
265 * @param format - See printf().
266 * @param ... - See printf().
268 static void dbgprintf(struct InternalInstruction* insn,
277 va_start(ap, format);
278 (void)vsnprintf(buffer, sizeof(buffer), format, ap);
281 insn->dlog(insn->dlogArg, buffer);
287 * setPrefixPresent - Marks that a particular prefix is present at a particular
290 * @param insn - The instruction to be marked as having the prefix.
291 * @param prefix - The prefix that is present.
292 * @param location - The location where the prefix is located (in the address
293 * space of the instruction's reader).
295 static void setPrefixPresent(struct InternalInstruction* insn,
299 insn->prefixPresent[prefix] = 1;
300 insn->prefixLocations[prefix] = location;
304 * isPrefixAtLocation - Queries an instruction to determine whether a prefix is
305 * present at a given location.
307 * @param insn - The instruction to be queried.
308 * @param prefix - The prefix.
309 * @param location - The location to query.
310 * @return - Whether the prefix is at that location.
312 static BOOL isPrefixAtLocation(struct InternalInstruction* insn,
316 if (insn->prefixPresent[prefix] == 1 &&
317 insn->prefixLocations[prefix] == location)
324 * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the
325 * instruction as having them. Also sets the instruction's default operand,
326 * address, and other relevant data sizes to report operands correctly.
328 * @param insn - The instruction whose prefixes are to be read.
329 * @return - 0 if the instruction could be read until the end of the prefix
330 * bytes, and no prefixes conflicted; nonzero otherwise.
332 static int readPrefixes(struct InternalInstruction* insn) {
333 BOOL isPrefix = TRUE;
334 BOOL prefixGroups[4] = { FALSE };
335 uint64_t prefixLocation;
339 BOOL hasAdSize = FALSE;
340 BOOL hasOpSize = FALSE;
342 dbgprintf(insn, "readPrefixes()");
345 prefixLocation = insn->readerCursor;
347 /* If we fail reading prefixes, just stop here and let the opcode reader deal with it */
348 if (consumeByte(insn, &byte))
352 * If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
353 * break and let it be disassembled as a normal "instruction".
355 if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0)
358 if (insn->readerCursor - 1 == insn->startLocation
359 && (byte == 0xf2 || byte == 0xf3)
360 && !lookAtByte(insn, &nextByte))
363 * If the byte is 0xf2 or 0xf3, and any of the following conditions are
365 * - it is followed by a LOCK (0xf0) prefix
366 * - it is followed by an xchg instruction
367 * then it should be disassembled as a xacquire/xrelease not repne/rep.
369 if ((byte == 0xf2 || byte == 0xf3) &&
370 ((nextByte == 0xf0) |
371 ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90)))
372 insn->xAcquireRelease = TRUE;
374 * Also if the byte is 0xf3, and the following condition is met:
375 * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
376 * "mov mem, imm" (opcode 0xc6/0xc7) instructions.
377 * then it should be disassembled as an xrelease not rep.
380 (nextByte == 0x88 || nextByte == 0x89 ||
381 nextByte == 0xc6 || nextByte == 0xc7))
382 insn->xAcquireRelease = TRUE;
383 if (insn->mode == MODE_64BIT && (nextByte & 0xf0) == 0x40) {
384 if (consumeByte(insn, &nextByte))
386 if (lookAtByte(insn, &nextByte))
390 if (nextByte != 0x0f && nextByte != 0x90)
395 case 0xf0: /* LOCK */
396 case 0xf2: /* REPNE/REPNZ */
397 case 0xf3: /* REP or REPE/REPZ */
399 dbgprintf(insn, "Redundant Group 1 prefix");
400 prefixGroups[0] = TRUE;
401 setPrefixPresent(insn, byte, prefixLocation);
403 case 0x2e: /* CS segment override -OR- Branch not taken */
404 case 0x36: /* SS segment override -OR- Branch taken */
405 case 0x3e: /* DS segment override */
406 case 0x26: /* ES segment override */
407 case 0x64: /* FS segment override */
408 case 0x65: /* GS segment override */
411 insn->segmentOverride = SEG_OVERRIDE_CS;
414 insn->segmentOverride = SEG_OVERRIDE_SS;
417 insn->segmentOverride = SEG_OVERRIDE_DS;
420 insn->segmentOverride = SEG_OVERRIDE_ES;
423 insn->segmentOverride = SEG_OVERRIDE_FS;
426 insn->segmentOverride = SEG_OVERRIDE_GS;
429 debug("Unhandled override");
433 dbgprintf(insn, "Redundant Group 2 prefix");
434 prefixGroups[1] = TRUE;
435 setPrefixPresent(insn, byte, prefixLocation);
437 case 0x66: /* Operand-size override */
439 dbgprintf(insn, "Redundant Group 3 prefix");
440 prefixGroups[2] = TRUE;
442 setPrefixPresent(insn, byte, prefixLocation);
444 case 0x67: /* Address-size override */
446 dbgprintf(insn, "Redundant Group 4 prefix");
447 prefixGroups[3] = TRUE;
449 setPrefixPresent(insn, byte, prefixLocation);
451 default: /* Not a prefix byte */
457 dbgprintf(insn, "Found prefix 0x%hhx", byte);
460 insn->vectorExtensionType = TYPE_NO_VEX_XOP;
463 uint8_t byte1, byte2;
465 if (consumeByte(insn, &byte1)) {
466 dbgprintf(insn, "Couldn't read second byte of EVEX prefix");
470 if (lookAtByte(insn, &byte2)) {
471 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
475 if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) &&
476 ((~byte1 & 0xc) == 0xc) && ((byte2 & 0x4) == 0x4)) {
477 insn->vectorExtensionType = TYPE_EVEX;
480 unconsumeByte(insn); /* unconsume byte1 */
481 unconsumeByte(insn); /* unconsume byte */
482 insn->necessaryPrefixLocation = insn->readerCursor - 2;
485 if (insn->vectorExtensionType == TYPE_EVEX) {
486 insn->vectorExtensionPrefix[0] = byte;
487 insn->vectorExtensionPrefix[1] = byte1;
488 if (consumeByte(insn, &insn->vectorExtensionPrefix[2])) {
489 dbgprintf(insn, "Couldn't read third byte of EVEX prefix");
492 if (consumeByte(insn, &insn->vectorExtensionPrefix[3])) {
493 dbgprintf(insn, "Couldn't read fourth byte of EVEX prefix");
497 /* We simulate the REX prefix for simplicity's sake */
498 if (insn->mode == MODE_64BIT) {
499 insn->rexPrefix = 0x40
500 | (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3)
501 | (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2)
502 | (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1)
503 | (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0);
506 dbgprintf(insn, "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
507 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
508 insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]);
511 else if (byte == 0xc4) {
514 if (lookAtByte(insn, &byte1)) {
515 dbgprintf(insn, "Couldn't read second byte of VEX");
519 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
520 insn->vectorExtensionType = TYPE_VEX_3B;
521 insn->necessaryPrefixLocation = insn->readerCursor - 1;
525 insn->necessaryPrefixLocation = insn->readerCursor - 1;
528 if (insn->vectorExtensionType == TYPE_VEX_3B) {
529 insn->vectorExtensionPrefix[0] = byte;
530 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
531 consumeByte(insn, &insn->vectorExtensionPrefix[2]);
533 /* We simulate the REX prefix for simplicity's sake */
535 if (insn->mode == MODE_64BIT) {
536 insn->rexPrefix = 0x40
537 | (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3)
538 | (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2)
539 | (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1)
540 | (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0);
543 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx",
544 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
545 insn->vectorExtensionPrefix[2]);
548 else if (byte == 0xc5) {
551 if (lookAtByte(insn, &byte1)) {
552 dbgprintf(insn, "Couldn't read second byte of VEX");
556 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
557 insn->vectorExtensionType = TYPE_VEX_2B;
563 if (insn->vectorExtensionType == TYPE_VEX_2B) {
564 insn->vectorExtensionPrefix[0] = byte;
565 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
567 if (insn->mode == MODE_64BIT) {
568 insn->rexPrefix = 0x40
569 | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2);
572 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1]))
581 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx",
582 insn->vectorExtensionPrefix[0],
583 insn->vectorExtensionPrefix[1]);
586 else if (byte == 0x8f) {
589 if (lookAtByte(insn, &byte1)) {
590 dbgprintf(insn, "Couldn't read second byte of XOP");
594 if ((byte1 & 0x38) != 0x0) { /* 0 in these 3 bits is a POP instruction. */
595 insn->vectorExtensionType = TYPE_XOP;
596 insn->necessaryPrefixLocation = insn->readerCursor - 1;
600 insn->necessaryPrefixLocation = insn->readerCursor - 1;
603 if (insn->vectorExtensionType == TYPE_XOP) {
604 insn->vectorExtensionPrefix[0] = byte;
605 consumeByte(insn, &insn->vectorExtensionPrefix[1]);
606 consumeByte(insn, &insn->vectorExtensionPrefix[2]);
608 /* We simulate the REX prefix for simplicity's sake */
610 if (insn->mode == MODE_64BIT) {
611 insn->rexPrefix = 0x40
612 | (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3)
613 | (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2)
614 | (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1)
615 | (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0);
618 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2]))
627 dbgprintf(insn, "Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
628 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1],
629 insn->vectorExtensionPrefix[2]);
633 if (insn->mode == MODE_64BIT) {
634 if ((byte & 0xf0) == 0x40) {
637 if (lookAtByte(insn, &opcodeByte) || ((opcodeByte & 0xf0) == 0x40)) {
638 dbgprintf(insn, "Redundant REX prefix");
642 insn->rexPrefix = byte;
643 insn->necessaryPrefixLocation = insn->readerCursor - 2;
645 dbgprintf(insn, "Found REX prefix 0x%hhx", byte);
648 insn->necessaryPrefixLocation = insn->readerCursor - 1;
652 insn->necessaryPrefixLocation = insn->readerCursor - 1;
656 if (insn->mode == MODE_16BIT) {
657 insn->registerSize = (hasOpSize ? 4 : 2);
658 insn->addressSize = (hasAdSize ? 4 : 2);
659 insn->displacementSize = (hasAdSize ? 4 : 2);
660 insn->immediateSize = (hasOpSize ? 4 : 2);
661 } else if (insn->mode == MODE_32BIT) {
662 insn->registerSize = (hasOpSize ? 2 : 4);
663 insn->addressSize = (hasAdSize ? 2 : 4);
664 insn->displacementSize = (hasAdSize ? 2 : 4);
665 insn->immediateSize = (hasOpSize ? 2 : 4);
666 } else if (insn->mode == MODE_64BIT) {
667 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
668 insn->registerSize = 8;
669 insn->addressSize = (hasAdSize ? 4 : 8);
670 insn->displacementSize = 4;
671 insn->immediateSize = 4;
672 } else if (insn->rexPrefix) {
673 insn->registerSize = (hasOpSize ? 2 : 4);
674 insn->addressSize = (hasAdSize ? 4 : 8);
675 insn->displacementSize = (hasOpSize ? 2 : 4);
676 insn->immediateSize = (hasOpSize ? 2 : 4);
678 insn->registerSize = (hasOpSize ? 2 : 4);
679 insn->addressSize = (hasAdSize ? 4 : 8);
680 insn->displacementSize = (hasOpSize ? 2 : 4);
681 insn->immediateSize = (hasOpSize ? 2 : 4);
689 * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of
690 * extended or escape opcodes).
692 * @param insn - The instruction whose opcode is to be read.
693 * @return - 0 if the opcode could be read successfully; nonzero otherwise.
695 static int readOpcode(struct InternalInstruction* insn) {
696 /* Determine the length of the primary opcode */
700 dbgprintf(insn, "readOpcode()");
702 insn->opcodeType = ONEBYTE;
704 if (insn->vectorExtensionType == TYPE_EVEX)
706 switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) {
708 dbgprintf(insn, "Unhandled mm field for instruction (0x%hhx)",
709 mmFromEVEX2of4(insn->vectorExtensionPrefix[1]));
712 insn->opcodeType = TWOBYTE;
713 return consumeByte(insn, &insn->opcode);
715 insn->opcodeType = THREEBYTE_38;
716 return consumeByte(insn, &insn->opcode);
718 insn->opcodeType = THREEBYTE_3A;
719 return consumeByte(insn, &insn->opcode);
722 else if (insn->vectorExtensionType == TYPE_VEX_3B) {
723 switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
725 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
726 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
729 insn->opcodeType = TWOBYTE;
730 return consumeByte(insn, &insn->opcode);
732 insn->opcodeType = THREEBYTE_38;
733 return consumeByte(insn, &insn->opcode);
735 insn->opcodeType = THREEBYTE_3A;
736 return consumeByte(insn, &insn->opcode);
739 else if (insn->vectorExtensionType == TYPE_VEX_2B) {
740 insn->opcodeType = TWOBYTE;
741 return consumeByte(insn, &insn->opcode);
743 else if (insn->vectorExtensionType == TYPE_XOP) {
744 switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) {
746 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)",
747 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]));
749 case XOP_MAP_SELECT_8:
750 insn->opcodeType = XOP8_MAP;
751 return consumeByte(insn, &insn->opcode);
752 case XOP_MAP_SELECT_9:
753 insn->opcodeType = XOP9_MAP;
754 return consumeByte(insn, &insn->opcode);
755 case XOP_MAP_SELECT_A:
756 insn->opcodeType = XOPA_MAP;
757 return consumeByte(insn, &insn->opcode);
761 if (consumeByte(insn, ¤t))
764 if (current == 0x0f) {
765 dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current);
767 if (consumeByte(insn, ¤t))
770 if (current == 0x38) {
771 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
773 if (consumeByte(insn, ¤t))
776 insn->opcodeType = THREEBYTE_38;
777 } else if (current == 0x3a) {
778 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
780 if (consumeByte(insn, ¤t))
783 insn->opcodeType = THREEBYTE_3A;
785 dbgprintf(insn, "Didn't find a three-byte escape prefix");
787 insn->opcodeType = TWOBYTE;
792 * At this point we have consumed the full opcode.
793 * Anything we consume from here on must be unconsumed.
796 insn->opcode = current;
801 static int readModRM(struct InternalInstruction* insn);
804 * getIDWithAttrMask - Determines the ID of an instruction, consuming
805 * the ModR/M byte as appropriate for extended and escape opcodes,
806 * and using a supplied attribute mask.
808 * @param instructionID - A pointer whose target is filled in with the ID of the
810 * @param insn - The instruction whose ID is to be determined.
811 * @param attrMask - The attribute mask to search.
812 * @return - 0 if the ModR/M could be read when needed or was not
813 * needed; nonzero otherwise.
815 static int getIDWithAttrMask(uint16_t* instructionID,
816 struct InternalInstruction* insn,
818 BOOL hasModRMExtension;
820 InstructionContext instructionClass = contextForAttrs(attrMask);
822 hasModRMExtension = modRMRequired(insn->opcodeType,
826 if (hasModRMExtension) {
830 *instructionID = decode(insn->opcodeType,
835 *instructionID = decode(insn->opcodeType,
845 * is16BitEquivalent - Determines whether two instruction names refer to
846 * equivalent instructions but one is 16-bit whereas the other is not.
848 * @param orig - The instruction that is not 16-bit
849 * @param equiv - The instruction that is 16-bit
851 static BOOL is16BitEquivalent(const char* orig, const char* equiv) {
855 if (orig[i] == '\0' && equiv[i] == '\0')
857 if (orig[i] == '\0' || equiv[i] == '\0')
859 if (orig[i] != equiv[i]) {
860 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
862 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
864 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
872 * getID - Determines the ID of an instruction, consuming the ModR/M byte as
873 * appropriate for extended and escape opcodes. Determines the attributes and
874 * context for the instruction before doing so.
876 * @param insn - The instruction whose ID is to be determined.
877 * @return - 0 if the ModR/M could be read when needed or was not needed;
880 static int getID(struct InternalInstruction* insn, const void *miiArg) {
882 uint16_t instructionID;
884 dbgprintf(insn, "getID()");
886 attrMask = ATTR_NONE;
888 if (insn->mode == MODE_64BIT)
889 attrMask |= ATTR_64BIT;
891 if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) {
892 attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX;
894 if (insn->vectorExtensionType == TYPE_EVEX) {
895 switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) {
897 attrMask |= ATTR_OPSIZE;
907 if (zFromEVEX4of4(insn->vectorExtensionPrefix[3]))
908 attrMask |= ATTR_EVEXKZ;
909 if (bFromEVEX4of4(insn->vectorExtensionPrefix[3]))
910 attrMask |= ATTR_EVEXB;
911 if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]))
912 attrMask |= ATTR_EVEXK;
913 if (lFromEVEX4of4(insn->vectorExtensionPrefix[3]))
914 attrMask |= ATTR_EVEXL;
915 if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]))
916 attrMask |= ATTR_EVEXL2;
918 else if (insn->vectorExtensionType == TYPE_VEX_3B) {
919 switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) {
921 attrMask |= ATTR_OPSIZE;
931 if (lFromVEX3of3(insn->vectorExtensionPrefix[2]))
932 attrMask |= ATTR_VEXL;
934 else if (insn->vectorExtensionType == TYPE_VEX_2B) {
935 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
937 attrMask |= ATTR_OPSIZE;
947 if (lFromVEX2of2(insn->vectorExtensionPrefix[1]))
948 attrMask |= ATTR_VEXL;
950 else if (insn->vectorExtensionType == TYPE_XOP) {
951 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
953 attrMask |= ATTR_OPSIZE;
963 if (lFromXOP3of3(insn->vectorExtensionPrefix[2]))
964 attrMask |= ATTR_VEXL;
971 if (insn->mode != MODE_16BIT && isPrefixAtLocation(insn, 0x66, insn->necessaryPrefixLocation))
972 attrMask |= ATTR_OPSIZE;
973 else if (isPrefixAtLocation(insn, 0x67, insn->necessaryPrefixLocation))
974 attrMask |= ATTR_ADSIZE;
975 else if (isPrefixAtLocation(insn, 0xf3, insn->necessaryPrefixLocation))
977 else if (isPrefixAtLocation(insn, 0xf2, insn->necessaryPrefixLocation))
981 if (insn->rexPrefix & 0x08)
982 attrMask |= ATTR_REXW;
984 if (getIDWithAttrMask(&instructionID, insn, attrMask))
988 * JCXZ/JECXZ need special handling for 16-bit mode because the meaning
989 * of the AdSize prefix is inverted w.r.t. 32-bit mode.
991 if (insn->mode == MODE_16BIT && insn->opcode == 0xE3) {
992 const struct InstructionSpecifier *spec;
993 spec = specifierForUID(instructionID);
996 * Check for Ii8PCRel instructions. We could alternatively do a
997 * string-compare on the names, but this is probably cheaper.
999 if (x86OperandSets[spec->operands][0].type == TYPE_REL8) {
1000 attrMask ^= ATTR_ADSIZE;
1001 if (getIDWithAttrMask(&instructionID, insn, attrMask))
1006 /* The following clauses compensate for limitations of the tables. */
1008 if ((insn->mode == MODE_16BIT || insn->prefixPresent[0x66]) &&
1009 !(attrMask & ATTR_OPSIZE)) {
1011 * The instruction tables make no distinction between instructions that
1012 * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
1013 * particular spot (i.e., many MMX operations). In general we're
1014 * conservative, but in the specific case where OpSize is present but not
1015 * in the right place we check if there's a 16-bit operation.
1018 const struct InstructionSpecifier *spec;
1019 uint16_t instructionIDWithOpsize;
1020 const char *specName, *specWithOpSizeName;
1022 spec = specifierForUID(instructionID);
1024 if (getIDWithAttrMask(&instructionIDWithOpsize,
1026 attrMask | ATTR_OPSIZE)) {
1028 * ModRM required with OpSize but not present; give up and return version
1029 * without OpSize set
1032 insn->instructionID = instructionID;
1037 specName = GetInstrName(instructionID, miiArg);
1038 specWithOpSizeName = GetInstrName(instructionIDWithOpsize, miiArg);
1040 if (is16BitEquivalent(specName, specWithOpSizeName) &&
1041 (insn->mode == MODE_16BIT) ^ insn->prefixPresent[0x66]) {
1042 insn->instructionID = instructionIDWithOpsize;
1043 insn->spec = specifierForUID(instructionIDWithOpsize);
1045 insn->instructionID = instructionID;
1051 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
1052 insn->rexPrefix & 0x01) {
1054 * NOOP shouldn't decode as NOOP if REX.b is set. Instead
1055 * it should decode as XCHG %r8, %eax.
1058 const struct InstructionSpecifier *spec;
1059 uint16_t instructionIDWithNewOpcode;
1060 const struct InstructionSpecifier *specWithNewOpcode;
1062 spec = specifierForUID(instructionID);
1064 /* Borrow opcode from one of the other XCHGar opcodes */
1065 insn->opcode = 0x91;
1067 if (getIDWithAttrMask(&instructionIDWithNewOpcode,
1070 insn->opcode = 0x90;
1072 insn->instructionID = instructionID;
1077 specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode);
1080 insn->opcode = 0x90;
1082 insn->instructionID = instructionIDWithNewOpcode;
1083 insn->spec = specWithNewOpcode;
1088 insn->instructionID = instructionID;
1089 insn->spec = specifierForUID(insn->instructionID);
1095 * readSIB - Consumes the SIB byte to determine addressing information for an
1098 * @param insn - The instruction whose SIB byte is to be read.
1099 * @return - 0 if the SIB byte was successfully read; nonzero otherwise.
1101 static int readSIB(struct InternalInstruction* insn) {
1102 SIBIndex sibIndexBase = SIB_INDEX_NONE;
1103 SIBBase sibBaseBase = SIB_BASE_NONE;
1104 uint8_t index, base;
1106 dbgprintf(insn, "readSIB()");
1108 if (insn->consumedSIB)
1111 insn->consumedSIB = TRUE;
1113 switch (insn->addressSize) {
1115 dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode");
1118 sibIndexBase = SIB_INDEX_EAX;
1119 sibBaseBase = SIB_BASE_EAX;
1122 sibIndexBase = SIB_INDEX_RAX;
1123 sibBaseBase = SIB_BASE_RAX;
1127 if (consumeByte(insn, &insn->sib))
1130 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3);
1131 if (insn->vectorExtensionType == TYPE_EVEX)
1132 index |= v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4;
1136 insn->sibIndex = SIB_INDEX_NONE;
1139 insn->sibIndex = (SIBIndex)(sibIndexBase + index);
1140 if (insn->sibIndex == SIB_INDEX_sib ||
1141 insn->sibIndex == SIB_INDEX_sib64)
1142 insn->sibIndex = SIB_INDEX_NONE;
1146 switch (scaleFromSIB(insn->sib)) {
1161 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3);
1166 switch (modFromModRM(insn->modRM)) {
1168 insn->eaDisplacement = EA_DISP_32;
1169 insn->sibBase = SIB_BASE_NONE;
1172 insn->eaDisplacement = EA_DISP_8;
1173 insn->sibBase = (SIBBase)(sibBaseBase + base);
1176 insn->eaDisplacement = EA_DISP_32;
1177 insn->sibBase = (SIBBase)(sibBaseBase + base);
1180 debug("Cannot have Mod = 0b11 and a SIB byte");
1185 insn->sibBase = (SIBBase)(sibBaseBase + base);
1193 * readDisplacement - Consumes the displacement of an instruction.
1195 * @param insn - The instruction whose displacement is to be read.
1196 * @return - 0 if the displacement byte was successfully read; nonzero
1199 static int readDisplacement(struct InternalInstruction* insn) {
1204 dbgprintf(insn, "readDisplacement()");
1206 if (insn->consumedDisplacement)
1209 insn->consumedDisplacement = TRUE;
1210 insn->displacementOffset = insn->readerCursor - insn->startLocation;
1212 switch (insn->eaDisplacement) {
1214 insn->consumedDisplacement = FALSE;
1217 if (consumeInt8(insn, &d8))
1219 insn->displacement = d8;
1222 if (consumeInt16(insn, &d16))
1224 insn->displacement = d16;
1227 if (consumeInt32(insn, &d32))
1229 insn->displacement = d32;
1233 insn->consumedDisplacement = TRUE;
1238 * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and
1239 * displacement) for an instruction and interprets it.
1241 * @param insn - The instruction whose addressing information is to be read.
1242 * @return - 0 if the information was successfully read; nonzero otherwise.
1244 static int readModRM(struct InternalInstruction* insn) {
1245 uint8_t mod, rm, reg;
1247 dbgprintf(insn, "readModRM()");
1249 if (insn->consumedModRM)
1252 if (consumeByte(insn, &insn->modRM))
1254 insn->consumedModRM = TRUE;
1256 mod = modFromModRM(insn->modRM);
1257 rm = rmFromModRM(insn->modRM);
1258 reg = regFromModRM(insn->modRM);
1261 * This goes by insn->registerSize to pick the correct register, which messes
1262 * up if we're using (say) XMM or 8-bit register operands. That gets fixed in
1265 switch (insn->registerSize) {
1267 insn->regBase = MODRM_REG_AX;
1268 insn->eaRegBase = EA_REG_AX;
1271 insn->regBase = MODRM_REG_EAX;
1272 insn->eaRegBase = EA_REG_EAX;
1275 insn->regBase = MODRM_REG_RAX;
1276 insn->eaRegBase = EA_REG_RAX;
1280 reg |= rFromREX(insn->rexPrefix) << 3;
1281 rm |= bFromREX(insn->rexPrefix) << 3;
1282 if (insn->vectorExtensionType == TYPE_EVEX) {
1283 reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1284 rm |= xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
1287 insn->reg = (Reg)(insn->regBase + reg);
1289 switch (insn->addressSize) {
1291 insn->eaBaseBase = EA_BASE_BX_SI;
1296 insn->eaBase = EA_BASE_NONE;
1297 insn->eaDisplacement = EA_DISP_16;
1298 if (readDisplacement(insn))
1301 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1302 insn->eaDisplacement = EA_DISP_NONE;
1306 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1307 insn->eaDisplacement = EA_DISP_8;
1308 insn->displacementSize = 1;
1309 if (readDisplacement(insn))
1313 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1314 insn->eaDisplacement = EA_DISP_16;
1315 if (readDisplacement(insn))
1319 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1320 if (readDisplacement(insn))
1327 insn->eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
1331 insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */
1335 case 0xc: /* in case REXW.b is set */
1336 insn->eaBase = (insn->addressSize == 4 ?
1337 EA_BASE_sib : EA_BASE_sib64);
1338 if (readSIB(insn) || readDisplacement(insn))
1342 insn->eaBase = EA_BASE_NONE;
1343 insn->eaDisplacement = EA_DISP_32;
1344 if (readDisplacement(insn))
1348 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1353 insn->displacementSize = 1;
1356 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
1360 case 0xc: /* in case REXW.b is set */
1361 insn->eaBase = EA_BASE_sib;
1362 if (readSIB(insn) || readDisplacement(insn))
1366 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1367 if (readDisplacement(insn))
1373 insn->eaDisplacement = EA_DISP_NONE;
1374 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1378 } /* switch (insn->addressSize) */
1383 #define GENERIC_FIXUP_FUNC(name, base, prefix) \
1384 static uint8_t name(struct InternalInstruction *insn, \
1391 debug("Unhandled register type"); \
1395 return base + index; \
1397 if (insn->rexPrefix && \
1398 index >= 4 && index <= 7) { \
1399 return prefix##_SPL + (index - 4); \
1401 return prefix##_AL + index; \
1404 return prefix##_AX + index; \
1406 return prefix##_EAX + index; \
1408 return prefix##_RAX + index; \
1410 return prefix##_ZMM0 + index; \
1412 return prefix##_YMM0 + index; \
1417 return prefix##_XMM0 + index; \
1421 return prefix##_K0 + index; \
1427 return prefix##_MM0 + index; \
1428 case TYPE_SEGMENTREG: \
1431 return prefix##_ES + index; \
1432 case TYPE_DEBUGREG: \
1435 return prefix##_DR0 + index; \
1436 case TYPE_CONTROLREG: \
1439 return prefix##_CR0 + index; \
1444 * fixup*Value - Consults an operand type to determine the meaning of the
1445 * reg or R/M field. If the operand is an XMM operand, for example, an
1446 * operand would be XMM0 instead of AX, which readModRM() would otherwise
1447 * misinterpret it as.
1449 * @param insn - The instruction containing the operand.
1450 * @param type - The operand type.
1451 * @param index - The existing value of the field as reported by readModRM().
1452 * @param valid - The address of a uint8_t. The target is set to 1 if the
1453 * field is valid for the register class; 0 if not.
1454 * @return - The proper value.
1456 GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG)
1457 GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
1460 * fixupReg - Consults an operand specifier to determine which of the
1461 * fixup*Value functions to use in correcting readModRM()'ss interpretation.
1463 * @param insn - See fixup*Value().
1464 * @param op - The operand specifier.
1465 * @return - 0 if fixup was successful; -1 if the register returned was
1466 * invalid for its class.
1468 static int fixupReg(struct InternalInstruction *insn,
1469 const struct OperandSpecifier *op) {
1472 dbgprintf(insn, "fixupReg()");
1474 switch ((OperandEncoding)op->encoding) {
1476 debug("Expected a REG or R/M encoding in fixupReg");
1479 insn->vvvv = (Reg)fixupRegValue(insn,
1480 (OperandType)op->type,
1487 insn->reg = (Reg)fixupRegValue(insn,
1488 (OperandType)op->type,
1489 insn->reg - insn->regBase,
1495 if (insn->eaBase >= insn->eaRegBase) {
1496 insn->eaBase = (EABase)fixupRMValue(insn,
1497 (OperandType)op->type,
1498 insn->eaBase - insn->eaRegBase,
1510 * readOpcodeRegister - Reads an operand from the opcode field of an
1511 * instruction and interprets it appropriately given the operand width.
1512 * Handles AddRegFrm instructions.
1514 * @param insn - the instruction whose opcode field is to be read.
1515 * @param size - The width (in bytes) of the register being specified.
1516 * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1518 * @return - 0 on success; nonzero otherwise.
1520 static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
1521 dbgprintf(insn, "readOpcodeRegister()");
1524 size = insn->registerSize;
1528 insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3)
1529 | (insn->opcode & 7)));
1530 if (insn->rexPrefix &&
1531 insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1532 insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1533 insn->opcodeRegister = (Reg)(MODRM_REG_SPL
1534 + (insn->opcodeRegister - MODRM_REG_AL - 4));
1539 insn->opcodeRegister = (Reg)(MODRM_REG_AX
1540 + ((bFromREX(insn->rexPrefix) << 3)
1541 | (insn->opcode & 7)));
1544 insn->opcodeRegister = (Reg)(MODRM_REG_EAX
1545 + ((bFromREX(insn->rexPrefix) << 3)
1546 | (insn->opcode & 7)));
1549 insn->opcodeRegister = (Reg)(MODRM_REG_RAX
1550 + ((bFromREX(insn->rexPrefix) << 3)
1551 | (insn->opcode & 7)));
1559 * readImmediate - Consumes an immediate operand from an instruction, given the
1560 * desired operand size.
1562 * @param insn - The instruction whose operand is to be read.
1563 * @param size - The width (in bytes) of the operand.
1564 * @return - 0 if the immediate was successfully consumed; nonzero
1567 static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
1573 dbgprintf(insn, "readImmediate()");
1575 if (insn->numImmediatesConsumed == 2) {
1576 debug("Already consumed two immediates");
1581 size = insn->immediateSize;
1583 insn->immediateSize = size;
1584 insn->immediateOffset = insn->readerCursor - insn->startLocation;
1588 if (consumeByte(insn, &imm8))
1590 insn->immediates[insn->numImmediatesConsumed] = imm8;
1593 if (consumeUInt16(insn, &imm16))
1595 insn->immediates[insn->numImmediatesConsumed] = imm16;
1598 if (consumeUInt32(insn, &imm32))
1600 insn->immediates[insn->numImmediatesConsumed] = imm32;
1603 if (consumeUInt64(insn, &imm64))
1605 insn->immediates[insn->numImmediatesConsumed] = imm64;
1609 insn->numImmediatesConsumed++;
1615 * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix.
1617 * @param insn - The instruction whose operand is to be read.
1618 * @return - 0 if the vvvv was successfully consumed; nonzero
1621 static int readVVVV(struct InternalInstruction* insn) {
1622 dbgprintf(insn, "readVVVV()");
1625 if (insn->vectorExtensionType == TYPE_EVEX)
1626 vvvv = vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]);
1627 else if (insn->vectorExtensionType == TYPE_VEX_3B)
1628 vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
1629 else if (insn->vectorExtensionType == TYPE_VEX_2B)
1630 vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
1631 else if (insn->vectorExtensionType == TYPE_XOP)
1632 vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
1636 if (insn->mode != MODE_64BIT)
1639 insn->vvvv = static_cast<Reg>(vvvv);
1644 * readMaskRegister - Reads an mask register from the opcode field of an
1647 * @param insn - The instruction whose opcode field is to be read.
1648 * @return - 0 on success; nonzero otherwise.
1650 static int readMaskRegister(struct InternalInstruction* insn) {
1651 dbgprintf(insn, "readMaskRegister()");
1653 if (insn->vectorExtensionType != TYPE_EVEX)
1657 static_cast<Reg>(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]));
1662 * readOperands - Consults the specifier for an instruction and consumes all
1663 * operands for that instruction, interpreting them as it goes.
1665 * @param insn - The instruction whose operands are to be read and interpreted.
1666 * @return - 0 if all operands could be read; nonzero otherwise.
1668 static int readOperands(struct InternalInstruction* insn) {
1670 int hasVVVV, needVVVV;
1673 dbgprintf(insn, "readOperands()");
1675 /* If non-zero vvvv specified, need to make sure one of the operands
1677 hasVVVV = !readVVVV(insn);
1678 needVVVV = hasVVVV && (insn->vvvv != 0);
1680 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
1681 switch (x86OperandSets[insn->spec->operands][index].encoding) {
1688 if (readModRM(insn))
1690 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1699 dbgprintf(insn, "We currently don't hande code-offset encodings");
1703 /* Saw a register immediate so don't read again and instead split the
1704 previous immediate. FIXME: This is a hack. */
1705 insn->immediates[insn->numImmediatesConsumed] =
1706 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1707 ++insn->numImmediatesConsumed;
1710 if (readImmediate(insn, 1))
1712 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM3 &&
1713 insn->immediates[insn->numImmediatesConsumed - 1] > 7)
1715 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM5 &&
1716 insn->immediates[insn->numImmediatesConsumed - 1] > 31)
1718 if (x86OperandSets[insn->spec->operands][index].type == TYPE_XMM128 ||
1719 x86OperandSets[insn->spec->operands][index].type == TYPE_XMM256)
1723 if (readImmediate(insn, 2))
1727 if (readImmediate(insn, 4))
1731 if (readImmediate(insn, 8))
1735 if (readImmediate(insn, insn->immediateSize))
1739 if (readImmediate(insn, insn->addressSize))
1743 if (readOpcodeRegister(insn, 1))
1747 if (readOpcodeRegister(insn, 2))
1751 if (readOpcodeRegister(insn, 4))
1755 if (readOpcodeRegister(insn, 8))
1759 if (readOpcodeRegister(insn, 0))
1765 needVVVV = 0; /* Mark that we have found a VVVV operand. */
1768 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1771 case ENCODING_WRITEMASK:
1772 if (readMaskRegister(insn))
1778 dbgprintf(insn, "Encountered an operand with an unknown encoding.");
1783 /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */
1784 if (needVVVV) return -1;
1790 * decodeInstruction - Reads and interprets a full instruction provided by the
1793 * @param insn - A pointer to the instruction to be populated. Must be
1795 * @param reader - The function to be used to read the instruction's bytes.
1796 * @param readerArg - A generic argument to be passed to the reader to store
1797 * any internal state.
1798 * @param logger - If non-NULL, the function to be used to write log messages
1800 * @param loggerArg - A generic argument to be passed to the logger to store
1801 * any internal state.
1802 * @param startLoc - The address (in the reader's address space) of the first
1803 * byte in the instruction.
1804 * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to
1805 * decode the instruction in.
1806 * @return - 0 if the instruction's memory could be read; nonzero if
1809 int llvm::X86Disassembler::decodeInstruction(
1810 struct InternalInstruction *insn, byteReader_t reader,
1811 const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg,
1812 uint64_t startLoc, DisassemblerMode mode) {
1813 memset(insn, 0, sizeof(struct InternalInstruction));
1815 insn->reader = reader;
1816 insn->readerArg = readerArg;
1817 insn->dlog = logger;
1818 insn->dlogArg = loggerArg;
1819 insn->startLocation = startLoc;
1820 insn->readerCursor = startLoc;
1822 insn->numImmediatesConsumed = 0;
1824 if (readPrefixes(insn) ||
1826 getID(insn, miiArg) ||
1827 insn->instructionID == 0 ||
1831 insn->operands = &x86OperandSets[insn->spec->operands][0];
1833 insn->length = insn->readerCursor - insn->startLocation;
1835 dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu",
1836 startLoc, insn->readerCursor, insn->length);
1838 if (insn->length > 15)
1839 dbgprintf(insn, "Instruction exceeds 15-byte limit");