1 /*===-- X86DisassemblerDecoderCommon.h - Disassembler decoder -----*- C -*-===*
3 * The LLVM Compiler Infrastructure
5 * This file is distributed under the University of Illinois Open Source
6 * License. See LICENSE.TXT for details.
8 *===----------------------------------------------------------------------===*
10 * This file is part of the X86 Disassembler.
11 * It contains common definitions used by both the disassembler and the table
13 * Documentation for the disassembler can be found in X86Disassembler.h.
15 *===----------------------------------------------------------------------===*/
18 * This header file provides those definitions that need to be shared between
19 * the decoder and the table generator in a C-friendly manner.
22 #ifndef X86DISASSEMBLERDECODERCOMMON_H
23 #define X86DISASSEMBLERDECODERCOMMON_H
25 #include "llvm/Support/DataTypes.h"
27 #define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers
28 #define CONTEXTS_SYM x86DisassemblerContexts
29 #define ONEBYTE_SYM x86DisassemblerOneByteOpcodes
30 #define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes
31 #define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes
32 #define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes
33 #define THREEBYTEA6_SYM x86DisassemblerThreeByteA6Opcodes
34 #define THREEBYTEA7_SYM x86DisassemblerThreeByteA7Opcodes
36 #define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers"
37 #define CONTEXTS_STR "x86DisassemblerContexts"
38 #define ONEBYTE_STR "x86DisassemblerOneByteOpcodes"
39 #define TWOBYTE_STR "x86DisassemblerTwoByteOpcodes"
40 #define THREEBYTE38_STR "x86DisassemblerThreeByte38Opcodes"
41 #define THREEBYTE3A_STR "x86DisassemblerThreeByte3AOpcodes"
42 #define THREEBYTEA6_STR "x86DisassemblerThreeByteA6Opcodes"
43 #define THREEBYTEA7_STR "x86DisassemblerThreeByteA7Opcodes"
46 * Attributes of an instruction that must be known before the opcode can be
47 * processed correctly. Most of these indicate the presence of particular
48 * prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
50 #define ATTRIBUTE_BITS \
51 ENUM_ENTRY(ATTR_NONE, 0x00) \
52 ENUM_ENTRY(ATTR_64BIT, 0x01) \
53 ENUM_ENTRY(ATTR_XS, 0x02) \
54 ENUM_ENTRY(ATTR_XD, 0x04) \
55 ENUM_ENTRY(ATTR_REXW, 0x08) \
56 ENUM_ENTRY(ATTR_OPSIZE, 0x10) \
57 ENUM_ENTRY(ATTR_ADSIZE, 0x20) \
58 ENUM_ENTRY(ATTR_VEX, 0x40) \
59 ENUM_ENTRY(ATTR_VEXL, 0x80)
61 #define ENUM_ENTRY(n, v) n = v,
69 * Combinations of the above attributes that are relevant to instruction
70 * decode. Although other combinations are possible, they can be reduced to
71 * these without affecting the ultimately decoded instruction.
74 /* Class name Rank Rationale for rank assignment */
75 #define INSTRUCTION_CONTEXTS \
76 ENUM_ENTRY(IC, 0, "says nothing about the instruction") \
77 ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \
78 "64-bit mode but no more") \
79 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
80 "operands change width") \
81 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
82 "operands change width") \
83 ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \
84 "but not the operands") \
85 ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \
86 "but not the operands") \
87 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
88 "operands change width") \
89 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
90 "operands change width") \
91 ENUM_ENTRY(IC_64BIT_REXW, 4, "requires a REX.W prefix, so operands "\
92 "change width; overrides IC_OPSIZE") \
93 ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \
94 ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \
95 ENUM_ENTRY(IC_64BIT_XD, 5, "XD instructions are SSE; REX.W is " \
97 ENUM_ENTRY(IC_64BIT_XS, 5, "Just as meaningful as IC_64BIT_XD") \
98 ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \
99 ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \
100 ENUM_ENTRY(IC_64BIT_REXW_XS, 6, "OPSIZE could mean a different " \
102 ENUM_ENTRY(IC_64BIT_REXW_XD, 6, "Just as meaningful as " \
103 "IC_64BIT_REXW_XS") \
104 ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 7, "The Dynamic Duo! Prefer over all " \
105 "else because this changes most " \
106 "operands' meaning") \
107 ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \
108 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \
109 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \
110 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
111 ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \
112 ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \
113 ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \
114 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
115 ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \
116 ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\
117 ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\
118 ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \
119 ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize")
122 #define ENUM_ENTRY(n, r, d) n,
126 } InstructionContext;
130 * Opcode types, which determine which decode table to use, both in the Intel
131 * manual and also for the decoder.
143 * The following structs are used for the hierarchical decode table. After
144 * determining the instruction's class (i.e., which IC_* constant applies to
145 * it), the decoder reads the opcode. Some instructions require specific
146 * values of the ModR/M byte, so the ModR/M byte indexes into the final table.
148 * If a ModR/M byte is not required, "required" is left unset, and the values
149 * for each instructionID are identical.
152 typedef uint16_t InstrUID;
155 * ModRMDecisionType - describes the type of ModR/M decision, allowing the
156 * consumer to determine the number of entries in it.
158 * MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded
159 * instruction is the same.
160 * MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode
161 * corresponds to one instruction; otherwise, it corresponds to
162 * a different instruction.
163 * MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This
164 corresponds to instructions that use reg field as opcode
165 * MODRM_FULL - Potentially, each value of the ModR/M byte could correspond
166 * to a different instruction.
170 ENUM_ENTRY(MODRM_ONEENTRY) \
171 ENUM_ENTRY(MODRM_SPLITRM) \
172 ENUM_ENTRY(MODRM_SPLITREG) \
173 ENUM_ENTRY(MODRM_FULL)
175 #define ENUM_ENTRY(n) n,
183 * ModRMDecision - Specifies whether a ModR/M byte is needed and (if so) which
184 * instruction each possible value of the ModR/M byte corresponds to. Once
185 * this information is known, we have narrowed down to a single instruction.
187 struct ModRMDecision {
190 /* The macro below must be defined wherever this file is included. */
195 * OpcodeDecision - Specifies which set of ModR/M->instruction tables to look at
196 * given a particular opcode.
198 struct OpcodeDecision {
199 struct ModRMDecision modRMDecisions[256];
203 * ContextDecision - Specifies which opcode->instruction tables to look at given
204 * a particular context (set of attributes). Since there are many possible
205 * contexts, the decoder first uses CONTEXTS_SYM to determine which context
206 * applies given a specific set of attributes. Hence there are only IC_max
207 * entries in this table, rather than 2^(ATTR_max).
209 struct ContextDecision {
210 struct OpcodeDecision opcodeDecisions[IC_max];
214 * Physical encodings of instruction operands.
218 ENUM_ENTRY(ENCODING_NONE, "") \
219 ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \
220 ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \
221 ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \
222 ENUM_ENTRY(ENCODING_CB, "1-byte code offset (possible new CS value)") \
223 ENUM_ENTRY(ENCODING_CW, "2-byte") \
224 ENUM_ENTRY(ENCODING_CD, "4-byte") \
225 ENUM_ENTRY(ENCODING_CP, "6-byte") \
226 ENUM_ENTRY(ENCODING_CO, "8-byte") \
227 ENUM_ENTRY(ENCODING_CT, "10-byte") \
228 ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \
229 ENUM_ENTRY(ENCODING_IW, "2-byte") \
230 ENUM_ENTRY(ENCODING_ID, "4-byte") \
231 ENUM_ENTRY(ENCODING_IO, "8-byte") \
232 ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \
234 ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \
235 ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \
236 ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \
237 ENUM_ENTRY(ENCODING_I, "Position on floating-point stack added to the " \
240 ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \
241 ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \
242 ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \
244 ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \
247 #define ENUM_ENTRY(n, d) n,
255 * Semantic interpretations of instruction operands.
259 ENUM_ENTRY(TYPE_NONE, "") \
260 ENUM_ENTRY(TYPE_REL8, "1-byte immediate address") \
261 ENUM_ENTRY(TYPE_REL16, "2-byte") \
262 ENUM_ENTRY(TYPE_REL32, "4-byte") \
263 ENUM_ENTRY(TYPE_REL64, "8-byte") \
264 ENUM_ENTRY(TYPE_PTR1616, "2+2-byte segment+offset address") \
265 ENUM_ENTRY(TYPE_PTR1632, "2+4-byte") \
266 ENUM_ENTRY(TYPE_PTR1664, "2+8-byte") \
267 ENUM_ENTRY(TYPE_R8, "1-byte register operand") \
268 ENUM_ENTRY(TYPE_R16, "2-byte") \
269 ENUM_ENTRY(TYPE_R32, "4-byte") \
270 ENUM_ENTRY(TYPE_R64, "8-byte") \
271 ENUM_ENTRY(TYPE_IMM8, "1-byte immediate operand") \
272 ENUM_ENTRY(TYPE_IMM16, "2-byte") \
273 ENUM_ENTRY(TYPE_IMM32, "4-byte") \
274 ENUM_ENTRY(TYPE_IMM64, "8-byte") \
275 ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \
276 ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \
277 ENUM_ENTRY(TYPE_RM8, "1-byte register or memory operand") \
278 ENUM_ENTRY(TYPE_RM16, "2-byte") \
279 ENUM_ENTRY(TYPE_RM32, "4-byte") \
280 ENUM_ENTRY(TYPE_RM64, "8-byte") \
281 ENUM_ENTRY(TYPE_M, "Memory operand") \
282 ENUM_ENTRY(TYPE_M8, "1-byte") \
283 ENUM_ENTRY(TYPE_M16, "2-byte") \
284 ENUM_ENTRY(TYPE_M32, "4-byte") \
285 ENUM_ENTRY(TYPE_M64, "8-byte") \
286 ENUM_ENTRY(TYPE_LEA, "Effective address") \
287 ENUM_ENTRY(TYPE_M128, "16-byte (SSE/SSE2)") \
288 ENUM_ENTRY(TYPE_M256, "256-byte (AVX)") \
289 ENUM_ENTRY(TYPE_M1616, "2+2-byte segment+offset address") \
290 ENUM_ENTRY(TYPE_M1632, "2+4-byte") \
291 ENUM_ENTRY(TYPE_M1664, "2+8-byte") \
292 ENUM_ENTRY(TYPE_M16_32, "2+4-byte two-part memory operand (LIDT, LGDT)") \
293 ENUM_ENTRY(TYPE_M16_16, "2+2-byte (BOUND)") \
294 ENUM_ENTRY(TYPE_M32_32, "4+4-byte (BOUND)") \
295 ENUM_ENTRY(TYPE_M16_64, "2+8-byte (LIDT, LGDT)") \
296 ENUM_ENTRY(TYPE_MOFFS8, "1-byte memory offset (relative to segment " \
298 ENUM_ENTRY(TYPE_MOFFS16, "2-byte") \
299 ENUM_ENTRY(TYPE_MOFFS32, "4-byte") \
300 ENUM_ENTRY(TYPE_MOFFS64, "8-byte") \
301 ENUM_ENTRY(TYPE_SREG, "Byte with single bit set: 0 = ES, 1 = CS, " \
302 "2 = SS, 3 = DS, 4 = FS, 5 = GS") \
303 ENUM_ENTRY(TYPE_M32FP, "32-bit IEE754 memory floating-point operand") \
304 ENUM_ENTRY(TYPE_M64FP, "64-bit") \
305 ENUM_ENTRY(TYPE_M80FP, "80-bit extended") \
306 ENUM_ENTRY(TYPE_M16INT, "2-byte memory integer operand for use in " \
307 "floating-point instructions") \
308 ENUM_ENTRY(TYPE_M32INT, "4-byte") \
309 ENUM_ENTRY(TYPE_M64INT, "8-byte") \
310 ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \
311 ENUM_ENTRY(TYPE_MM, "MMX register operand") \
312 ENUM_ENTRY(TYPE_MM32, "4-byte MMX register or memory operand") \
313 ENUM_ENTRY(TYPE_MM64, "8-byte") \
314 ENUM_ENTRY(TYPE_XMM, "XMM register operand") \
315 ENUM_ENTRY(TYPE_XMM32, "4-byte XMM register or memory operand") \
316 ENUM_ENTRY(TYPE_XMM64, "8-byte") \
317 ENUM_ENTRY(TYPE_XMM128, "16-byte") \
318 ENUM_ENTRY(TYPE_XMM256, "32-byte") \
319 ENUM_ENTRY(TYPE_XMM0, "Implicit use of XMM0") \
320 ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
321 ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
322 ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \
324 ENUM_ENTRY(TYPE_Mv, "Memory operand of operand size") \
325 ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \
326 ENUM_ENTRY(TYPE_IMMv, "Immediate operand of operand size") \
327 ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \
328 ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \
329 ENUM_ENTRY(TYPE_DUP1, "operand 1") \
330 ENUM_ENTRY(TYPE_DUP2, "operand 2") \
331 ENUM_ENTRY(TYPE_DUP3, "operand 3") \
332 ENUM_ENTRY(TYPE_DUP4, "operand 4") \
333 ENUM_ENTRY(TYPE_M512, "512-bit FPU/MMX/XMM/MXCSR state")
335 #define ENUM_ENTRY(n, d) n,
343 * OperandSpecifier - The specification for how to extract and interpret one
346 struct OperandSpecifier {
352 * Indicates where the opcode modifier (if any) is to be found. Extended
353 * opcodes with AddRegFrm have the opcode modifier in the ModR/M byte.
356 #define MODIFIER_TYPES \
357 ENUM_ENTRY(MODIFIER_NONE) \
358 ENUM_ENTRY(MODIFIER_OPCODE) \
359 ENUM_ENTRY(MODIFIER_MODRM)
361 #define ENUM_ENTRY(n) n,
368 #define X86_MAX_OPERANDS 5
371 * The specification for how to extract and interpret a full instruction and
374 struct InstructionSpecifier {
375 uint8_t modifierType;
376 uint8_t modifierBase;
377 struct OperandSpecifier operands[X86_MAX_OPERANDS];
379 /* The macro below must be defined wherever this file is included. */
380 INSTRUCTION_SPECIFIER_FIELDS
384 * Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode
385 * are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,