1 //===-- FloatingPoint.cpp - Floating point Reg -> Stack converter ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // virtual registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // This pass is hampered by the lack of decent CFG manipulation routines for
16 // machine code. In particular, this wants to be able to split critical edges
17 // as necessary, traverse the machine basic block CFG in depth-first order, and
18 // allow there to be multiple machine basic blocks for each LLVM basicblock
19 // (needed for critical edge splitting).
21 // In particular, this pass currently barfs on critical edges. Because of this,
22 // it requires the instruction selector to insert FP_REG_KILL instructions on
23 // the exits of any basic block that has critical edges going from it, or which
24 // branch to a critical basic block.
26 // FIXME: this is not implemented yet. The stackifier pass only works on local
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "fp"
33 #include "X86InstrInfo.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/LiveVariables.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Function.h" // FIXME: remove when using MBB CFG!
41 #include "llvm/Support/CFG.h" // FIXME: remove when using MBB CFG!
42 #include "Support/Debug.h"
43 #include "Support/DepthFirstIterator.h"
44 #include "Support/Statistic.h"
50 Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted");
51 Statistic<> NumFP ("x86-codegen", "Number of floating point instructions");
53 struct FPS : public MachineFunctionPass {
54 virtual bool runOnMachineFunction(MachineFunction &MF);
56 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
58 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
59 AU.addRequired<LiveVariables>();
60 MachineFunctionPass::getAnalysisUsage(AU);
63 LiveVariables *LV; // Live variable info for current function...
64 MachineBasicBlock *MBB; // Current basic block
65 unsigned Stack[8]; // FP<n> Registers in each stack slot...
66 unsigned RegMap[8]; // Track which stack slot contains each register
67 unsigned StackTop; // The current top of the FP stack.
69 void dumpStack() const {
70 std::cerr << "Stack contents:";
71 for (unsigned i = 0; i != StackTop; ++i) {
72 std::cerr << " FP" << Stack[i];
73 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
78 // getSlot - Return the stack slot number a particular register number is
80 unsigned getSlot(unsigned RegNo) const {
81 assert(RegNo < 8 && "Regno out of range!");
85 // getStackEntry - Return the X86::FP<n> register in register ST(i)
86 unsigned getStackEntry(unsigned STi) const {
87 assert(STi < StackTop && "Access past stack top!");
88 return Stack[StackTop-1-STi];
91 // getSTReg - Return the X86::ST(i) register which contains the specified
93 unsigned getSTReg(unsigned RegNo) const {
94 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
97 // pushReg - Push the specified FP<n> register onto the stack
98 void pushReg(unsigned Reg) {
99 assert(Reg < 8 && "Register number out of range!");
100 assert(StackTop < 8 && "Stack overflow!");
101 Stack[StackTop] = Reg;
102 RegMap[Reg] = StackTop++;
105 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
106 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
107 if (!isAtTop(RegNo)) {
108 unsigned Slot = getSlot(RegNo);
109 unsigned STReg = getSTReg(RegNo);
110 unsigned RegOnTop = getStackEntry(0);
112 // Swap the slots the regs are in
113 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
115 // Swap stack slot contents
116 assert(RegMap[RegOnTop] < StackTop);
117 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
119 // Emit an fxch to update the runtime processors version of the state
120 MachineInstr *MI = BuildMI(X86::FXCH, 1).addReg(STReg);
121 I = 1+MBB->insert(I, MI);
126 void duplicateToTop(unsigned RegNo, unsigned AsReg,
127 MachineBasicBlock::iterator &I) {
128 unsigned STReg = getSTReg(RegNo);
129 pushReg(AsReg); // New register on top of stack
131 MachineInstr *MI = BuildMI(X86::FLDrr, 1).addReg(STReg);
132 I = 1+MBB->insert(I, MI);
135 // popStackAfter - Pop the current value off of the top of the FP stack
136 // after the specified instruction.
137 void popStackAfter(MachineBasicBlock::iterator &I);
139 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
141 void handleZeroArgFP(MachineBasicBlock::iterator &I);
142 void handleOneArgFP(MachineBasicBlock::iterator &I);
143 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
144 void handleTwoArgFP(MachineBasicBlock::iterator &I);
145 void handleSpecialFP(MachineBasicBlock::iterator &I);
149 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
151 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
152 /// register references into FP stack references.
154 bool FPS::runOnMachineFunction(MachineFunction &MF) {
155 LV = &getAnalysis<LiveVariables>();
158 // Figure out the mapping of MBB's to BB's.
160 // FIXME: Eventually we should be able to traverse the MBB CFG directly, and
161 // we will need to extend this when one llvm basic block can codegen to
164 // FIXME again: Just use the mapping established by LiveVariables!
166 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
167 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
168 MBBMap[I->getBasicBlock()] = I;
170 // Process the function in depth first order so that we process at least one
171 // of the predecessors for every reachable block in the function.
172 std::set<const BasicBlock*> Processed;
173 const BasicBlock *Entry = MF.getFunction()->begin();
175 bool Changed = false;
176 for (df_ext_iterator<const BasicBlock*, std::set<const BasicBlock*> >
177 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
179 Changed |= processBasicBlock(MF, *MBBMap[*I]);
181 assert(MBBMap.size() == Processed.size() &&
182 "Doesn't handle unreachable code yet!");
187 /// processBasicBlock - Loop over all of the instructions in the basic block,
188 /// transforming FP instructions into their stack form.
190 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
191 const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
192 bool Changed = false;
195 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
196 MachineInstr *MI = *I;
197 unsigned Flags = TII.get(MI->getOpcode()).TSFlags;
198 if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
199 continue; // Efficiently ignore non-fp insts!
201 MachineInstr *PrevMI = I == BB.begin() ? 0 : *(I-1);
203 ++NumFP; // Keep track of # of pseudo instrs
204 DEBUG(std::cerr << "\nFPInst:\t";
205 MI->print(std::cerr, MF.getTarget()));
207 // Get dead variables list now because the MI pointer may be deleted as part
209 LiveVariables::killed_iterator IB = LV->dead_begin(MI);
210 LiveVariables::killed_iterator IE = LV->dead_end(MI);
212 DEBUG(const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
213 LiveVariables::killed_iterator I = LV->killed_begin(MI);
214 LiveVariables::killed_iterator E = LV->killed_end(MI);
216 std::cerr << "Killed Operands:";
218 std::cerr << " %" << MRI->getName(I->second);
222 switch (Flags & X86II::FPTypeMask) {
223 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
224 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
225 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
226 case X86II::TwoArgFP: handleTwoArgFP(I); break;
227 case X86II::SpecialFP: handleSpecialFP(I); break;
228 default: assert(0 && "Unknown FP Type!");
231 // Check to see if any of the values defined by this instruction are dead
232 // after definition. If so, pop them.
233 for (; IB != IE; ++IB) {
234 unsigned Reg = IB->second;
235 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
236 DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
237 ++I; // Insert fxch AFTER the instruction
238 moveToTop(Reg-X86::FP0, I); // Insert fxch if necessary
239 --I; // Move to fxch or old instruction
240 popStackAfter(I); // Pop the top of the stack, killing value
244 // Print out all of the instructions expanded to if -debug
245 DEBUG(if (*I == PrevMI) {
246 std::cerr<< "Just deleted pseudo instruction\n";
248 MachineBasicBlock::iterator Start = I;
249 // Rewind to first instruction newly inserted.
250 while (Start != BB.begin() && *(Start-1) != PrevMI) --Start;
251 std::cerr << "Inserted instructions:\n\t";
252 (*Start)->print(std::cerr, MF.getTarget());
253 while (++Start != I+1);
261 assert(StackTop == 0 && "Stack not empty at end of basic block?");
265 //===----------------------------------------------------------------------===//
266 // Efficient Lookup Table Support
267 //===----------------------------------------------------------------------===//
273 bool operator<(const TableEntry &TE) const { return from < TE.from; }
274 bool operator<(unsigned V) const { return from < V; }
278 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
279 for (unsigned i = 0; i != NumEntries-1; ++i)
280 if (!(Table[i] < Table[i+1])) return false;
284 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
285 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
286 if (I != Table+N && I->from == Opcode)
291 #define ARRAY_SIZE(TABLE) \
292 (sizeof(TABLE)/sizeof(TABLE[0]))
295 #define ASSERT_SORTED(TABLE)
297 #define ASSERT_SORTED(TABLE) \
298 { static bool TABLE##Checked = false; \
299 if (!TABLE##Checked) \
300 assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \
301 "All lookup tables must be sorted for efficient access!"); \
306 //===----------------------------------------------------------------------===//
308 //===----------------------------------------------------------------------===//
310 // PopTable - Sorted map of instructions to their popping version. The first
311 // element is an instruction, the second is the version which pops.
313 static const TableEntry PopTable[] = {
314 { X86::FADDrST0 , X86::FADDPrST0 },
316 { X86::FDIVRrST0, X86::FDIVRPrST0 },
317 { X86::FDIVrST0 , X86::FDIVPrST0 },
319 { X86::FISTr16 , X86::FISTPr16 },
320 { X86::FISTr32 , X86::FISTPr32 },
322 { X86::FMULrST0 , X86::FMULPrST0 },
324 { X86::FSTr32 , X86::FSTPr32 },
325 { X86::FSTr64 , X86::FSTPr64 },
326 { X86::FSTrr , X86::FSTPrr },
328 { X86::FSUBRrST0, X86::FSUBRPrST0 },
329 { X86::FSUBrST0 , X86::FSUBPrST0 },
331 { X86::FUCOMPr , X86::FUCOMPPr },
332 { X86::FUCOMr , X86::FUCOMPr },
335 /// popStackAfter - Pop the current value off of the top of the FP stack after
336 /// the specified instruction. This attempts to be sneaky and combine the pop
337 /// into the instruction itself if possible. The iterator is left pointing to
338 /// the last instruction, be it a new pop instruction inserted, or the old
339 /// instruction if it was modified in place.
341 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
342 ASSERT_SORTED(PopTable);
343 assert(StackTop > 0 && "Cannot pop empty stack!");
344 RegMap[Stack[--StackTop]] = ~0; // Update state
346 // Check to see if there is a popping version of this instruction...
347 int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), (*I)->getOpcode());
349 (*I)->setOpcode(Opcode);
350 if (Opcode == X86::FUCOMPPr)
351 (*I)->RemoveOperand(0);
353 } else { // Insert an explicit pop
354 MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(X86::ST0);
355 I = MBB->insert(I+1, MI);
359 static unsigned getFPReg(const MachineOperand &MO) {
360 assert(MO.isPhysicalRegister() && "Expected an FP register!");
361 unsigned Reg = MO.getReg();
362 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
363 return Reg - X86::FP0;
367 //===----------------------------------------------------------------------===//
368 // Instruction transformation implementation
369 //===----------------------------------------------------------------------===//
371 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
373 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
374 MachineInstr *MI = *I;
375 unsigned DestReg = getFPReg(MI->getOperand(0));
376 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
378 // Result gets pushed on the stack...
382 /// handleOneArgFP - fst <mem>, ST(0)
384 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
385 MachineInstr *MI = *I;
386 assert(MI->getNumOperands() == 5 && "Can only handle fst* instructions!");
388 // Is this the last use of the source register?
389 unsigned Reg = getFPReg(MI->getOperand(4));
390 bool KillsSrc = false;
391 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
392 E = LV->killed_end(MI); KI != E; ++KI)
393 KillsSrc |= KI->second == X86::FP0+Reg;
395 // FSTPr80 and FISTPr64 are strange because there are no non-popping versions.
396 // If we have one _and_ we don't want to pop the operand, duplicate the value
397 // on the stack instead of moving it. This ensure that popping the value is
400 if ((MI->getOpcode() == X86::FSTPr80 ||
401 MI->getOpcode() == X86::FISTPr64) && !KillsSrc) {
402 duplicateToTop(Reg, 7 /*temp register*/, I);
404 moveToTop(Reg, I); // Move to the top of the stack...
406 MI->RemoveOperand(4); // Remove explicit ST(0) operand
408 if (MI->getOpcode() == X86::FSTPr80 || MI->getOpcode() == X86::FISTPr64) {
409 assert(StackTop > 0 && "Stack empty??");
411 } else if (KillsSrc) { // Last use of operand?
417 /// handleOneArgFPRW - fchs - ST(0) = -ST(0)
419 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
420 MachineInstr *MI = *I;
421 assert(MI->getNumOperands() == 2 && "Can only handle fst* instructions!");
423 // Is this the last use of the source register?
424 unsigned Reg = getFPReg(MI->getOperand(1));
425 bool KillsSrc = false;
426 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
427 E = LV->killed_end(MI); KI != E; ++KI)
428 KillsSrc |= KI->second == X86::FP0+Reg;
431 // If this is the last use of the source register, just make sure it's on
432 // the top of the stack.
434 assert(StackTop > 0 && "Stack cannot be empty!");
436 pushReg(getFPReg(MI->getOperand(0)));
438 // If this is not the last use of the source register, _copy_ it to the top
440 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
443 MI->RemoveOperand(1); // Drop the source operand.
444 MI->RemoveOperand(0); // Drop the destination operand.
448 //===----------------------------------------------------------------------===//
449 // Define tables of various ways to map pseudo instructions
452 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
453 static const TableEntry ForwardST0Table[] = {
454 { X86::FpADD, X86::FADDST0r },
455 { X86::FpDIV, X86::FDIVST0r },
456 { X86::FpMUL, X86::FMULST0r },
457 { X86::FpSUB, X86::FSUBST0r },
458 { X86::FpUCOM, X86::FUCOMr },
461 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
462 static const TableEntry ReverseST0Table[] = {
463 { X86::FpADD, X86::FADDST0r }, // commutative
464 { X86::FpDIV, X86::FDIVRST0r },
465 { X86::FpMUL, X86::FMULST0r }, // commutative
466 { X86::FpSUB, X86::FSUBRST0r },
470 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
471 static const TableEntry ForwardSTiTable[] = {
472 { X86::FpADD, X86::FADDrST0 }, // commutative
473 { X86::FpDIV, X86::FDIVRrST0 },
474 { X86::FpMUL, X86::FMULrST0 }, // commutative
475 { X86::FpSUB, X86::FSUBRrST0 },
476 { X86::FpUCOM, X86::FUCOMr },
479 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
480 static const TableEntry ReverseSTiTable[] = {
481 { X86::FpADD, X86::FADDrST0 },
482 { X86::FpDIV, X86::FDIVrST0 },
483 { X86::FpMUL, X86::FMULrST0 },
484 { X86::FpSUB, X86::FSUBrST0 },
489 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
490 /// instructions which need to be simplified and possibly transformed.
492 /// Result: ST(0) = fsub ST(0), ST(i)
493 /// ST(i) = fsub ST(0), ST(i)
494 /// ST(0) = fsubr ST(0), ST(i)
495 /// ST(i) = fsubr ST(0), ST(i)
497 /// In addition to three address instructions, this also handles the FpUCOM
498 /// instruction which only has two operands, but no destination. This
499 /// instruction is also annoying because there is no "reverse" form of it
502 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
503 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
504 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
505 MachineInstr *MI = *I;
507 unsigned NumOperands = MI->getNumOperands();
508 assert(NumOperands == 3 ||
509 (NumOperands == 2 && MI->getOpcode() == X86::FpUCOM) &&
510 "Illegal TwoArgFP instruction!");
511 unsigned Dest = getFPReg(MI->getOperand(0));
512 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
513 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
514 bool KillsOp0 = false, KillsOp1 = false;
516 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
517 E = LV->killed_end(MI); KI != E; ++KI) {
518 KillsOp0 |= (KI->second == X86::FP0+Op0);
519 KillsOp1 |= (KI->second == X86::FP0+Op1);
522 // If this is an FpUCOM instruction, we must make sure the first operand is on
523 // the top of stack, the other one can be anywhere...
524 if (MI->getOpcode() == X86::FpUCOM)
527 unsigned TOS = getStackEntry(0);
529 // One of our operands must be on the top of the stack. If neither is yet, we
531 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
532 // We can choose to move either operand to the top of the stack. If one of
533 // the operands is killed by this instruction, we want that one so that we
534 // can update right on top of the old version.
536 moveToTop(Op0, I); // Move dead operand to TOS.
538 } else if (KillsOp1) {
542 // All of the operands are live after this instruction executes, so we
543 // cannot update on top of any operand. Because of this, we must
544 // duplicate one of the stack elements to the top. It doesn't matter
545 // which one we pick.
547 duplicateToTop(Op0, Dest, I);
551 } else if (!KillsOp0 && !KillsOp1 && MI->getOpcode() != X86::FpUCOM) {
552 // If we DO have one of our operands at the top of the stack, but we don't
553 // have a dead operand, we must duplicate one of the operands to a new slot
555 duplicateToTop(Op0, Dest, I);
560 // Now we know that one of our operands is on the top of the stack, and at
561 // least one of our operands is killed by this instruction.
562 assert((TOS == Op0 || TOS == Op1) &&
563 (KillsOp0 || KillsOp1 || MI->getOpcode() == X86::FpUCOM) &&
564 "Stack conditions not set up right!");
566 // We decide which form to use based on what is on the top of the stack, and
567 // which operand is killed by this instruction.
568 const TableEntry *InstTable;
569 bool isForward = TOS == Op0;
570 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
573 InstTable = ForwardST0Table;
575 InstTable = ReverseST0Table;
578 InstTable = ForwardSTiTable;
580 InstTable = ReverseSTiTable;
583 int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode());
584 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
586 // NotTOS - The register which is not on the top of stack...
587 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
589 // Replace the old instruction with a new instruction
590 *I = BuildMI(Opcode, 1).addReg(getSTReg(NotTOS));
592 // If both operands are killed, pop one off of the stack in addition to
593 // overwriting the other one.
594 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
595 assert(!updateST0 && "Should have updated other operand!");
596 popStackAfter(I); // Pop the top of stack
599 // Insert an explicit pop of the "updated" operand for FUCOM
600 if (MI->getOpcode() == X86::FpUCOM) {
601 if (KillsOp0 && !KillsOp1)
602 popStackAfter(I); // If we kill the first operand, pop it!
603 else if (KillsOp1 && Op0 != Op1) {
604 if (getStackEntry(0) == Op1) {
605 popStackAfter(I); // If it's right at the top of stack, just pop it
607 // Otherwise, move the top of stack into the dead slot, killing the
608 // operand without having to add in an explicit xchg then pop.
610 unsigned STReg = getSTReg(Op1);
611 unsigned OldSlot = getSlot(Op1);
612 unsigned TopReg = Stack[StackTop-1];
613 Stack[OldSlot] = TopReg;
614 RegMap[TopReg] = OldSlot;
616 Stack[--StackTop] = ~0;
618 MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(STReg);
619 I = MBB->insert(I+1, MI);
624 // Update stack information so that we know the destination register is now on
626 if (MI->getOpcode() != X86::FpUCOM) {
627 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
628 assert(UpdatedSlot < StackTop && Dest < 7);
629 Stack[UpdatedSlot] = Dest;
630 RegMap[Dest] = UpdatedSlot;
632 delete MI; // Remove the old instruction
636 /// handleSpecialFP - Handle special instructions which behave unlike other
637 /// floating point instructions. This is primarily intended for use by pseudo
640 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
641 MachineInstr *MI = *I;
642 switch (MI->getOpcode()) {
643 default: assert(0 && "Unknown SpecialFP instruction!");
644 case X86::FpGETRESULT: // Appears immediately after a call returning FP type!
645 assert(StackTop == 0 && "Stack should be empty after a call!");
646 pushReg(getFPReg(MI->getOperand(0)));
648 case X86::FpSETRESULT:
649 assert(StackTop == 1 && "Stack should have one element on it to return!");
650 --StackTop; // "Forget" we have something on the top of stack!
653 unsigned SrcReg = getFPReg(MI->getOperand(1));
654 unsigned DestReg = getFPReg(MI->getOperand(0));
655 bool KillsSrc = false;
656 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
657 E = LV->killed_end(MI); KI != E; ++KI)
658 KillsSrc |= KI->second == X86::FP0+SrcReg;
661 // If the input operand is killed, we can just change the owner of the
662 // incoming stack slot into the result.
663 unsigned Slot = getSlot(SrcReg);
664 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
665 Stack[Slot] = DestReg;
666 RegMap[DestReg] = Slot;
669 // For FMOV we just duplicate the specified value to a new stack slot.
670 // This could be made better, but would require substantial changes.
671 duplicateToTop(SrcReg, DestReg, I);
677 I = MBB->erase(I)-1; // Remove the pseudo instruction