1 //===-- FloatingPoint.cpp - Floating point Reg -> Stack converter ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // virtual registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // This pass is hampered by the lack of decent CFG manipulation routines for
16 // machine code. In particular, this wants to be able to split critical edges
17 // as necessary, traverse the machine basic block CFG in depth-first order, and
18 // allow there to be multiple machine basic blocks for each LLVM basicblock
19 // (needed for critical edge splitting).
21 // In particular, this pass currently barfs on critical edges. Because of this,
22 // it requires the instruction selector to insert FP_REG_KILL instructions on
23 // the exits of any basic block that has critical edges going from it, or which
24 // branch to a critical basic block.
26 // FIXME: this is not implemented yet. The stackifier pass only works on local
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "fp"
33 #include "X86InstrInfo.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/LiveVariables.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Function.h" // FIXME: remove when using MBB CFG!
41 #include "llvm/Support/CFG.h" // FIXME: remove when using MBB CFG!
42 #include "Support/Debug.h"
43 #include "Support/DepthFirstIterator.h"
44 #include "Support/Statistic.h"
50 Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted");
51 Statistic<> NumFP ("x86-codegen", "Number of floating point instructions");
53 struct FPS : public MachineFunctionPass {
54 virtual bool runOnMachineFunction(MachineFunction &MF);
56 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
58 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
59 AU.addRequired<LiveVariables>();
60 MachineFunctionPass::getAnalysisUsage(AU);
63 LiveVariables *LV; // Live variable info for current function...
64 MachineBasicBlock *MBB; // Current basic block
65 unsigned Stack[8]; // FP<n> Registers in each stack slot...
66 unsigned RegMap[8]; // Track which stack slot contains each register
67 unsigned StackTop; // The current top of the FP stack.
69 void dumpStack() const {
70 std::cerr << "Stack contents:";
71 for (unsigned i = 0; i != StackTop; ++i) {
72 std::cerr << " FP" << Stack[i];
73 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
78 // getSlot - Return the stack slot number a particular register number is
80 unsigned getSlot(unsigned RegNo) const {
81 assert(RegNo < 8 && "Regno out of range!");
85 // getStackEntry - Return the X86::FP<n> register in register ST(i)
86 unsigned getStackEntry(unsigned STi) const {
87 assert(STi < StackTop && "Access past stack top!");
88 return Stack[StackTop-1-STi];
91 // getSTReg - Return the X86::ST(i) register which contains the specified
93 unsigned getSTReg(unsigned RegNo) const {
94 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
97 // pushReg - Push the specifiex FP<n> register onto the stack
98 void pushReg(unsigned Reg) {
99 assert(Reg < 8 && "Register number out of range!");
100 assert(StackTop < 8 && "Stack overflow!");
101 Stack[StackTop] = Reg;
102 RegMap[Reg] = StackTop++;
105 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
106 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
107 if (!isAtTop(RegNo)) {
108 unsigned Slot = getSlot(RegNo);
109 unsigned STReg = getSTReg(RegNo);
110 unsigned RegOnTop = getStackEntry(0);
112 // Swap the slots the regs are in
113 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
115 // Swap stack slot contents
116 assert(RegMap[RegOnTop] < StackTop);
117 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
119 // Emit an fxch to update the runtime processors version of the state
120 MachineInstr *MI = BuildMI(X86::FXCH, 1).addReg(STReg);
121 I = 1+MBB->insert(I, MI);
126 void duplicateToTop(unsigned RegNo, unsigned AsReg,
127 MachineBasicBlock::iterator &I) {
128 unsigned STReg = getSTReg(RegNo);
129 pushReg(AsReg); // New register on top of stack
131 MachineInstr *MI = BuildMI(X86::FLDrr, 1).addReg(STReg);
132 I = 1+MBB->insert(I, MI);
135 // popStackAfter - Pop the current value off of the top of the FP stack
136 // after the specified instruction.
137 void popStackAfter(MachineBasicBlock::iterator &I);
139 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
141 void handleZeroArgFP(MachineBasicBlock::iterator &I);
142 void handleOneArgFP(MachineBasicBlock::iterator &I);
143 void handleTwoArgFP(MachineBasicBlock::iterator &I);
144 void handleSpecialFP(MachineBasicBlock::iterator &I);
148 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
150 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
151 /// register references into FP stack references.
153 bool FPS::runOnMachineFunction(MachineFunction &MF) {
154 LV = &getAnalysis<LiveVariables>();
157 // Figure out the mapping of MBB's to BB's.
159 // FIXME: Eventually we should be able to traverse the MBB CFG directly, and
160 // we will need to extend this when one llvm basic block can codegen to
163 // FIXME again: Just use the mapping established by LiveVariables!
165 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
166 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
167 MBBMap[I->getBasicBlock()] = I;
169 // Process the function in depth first order so that we process at least one
170 // of the predecessors for every reachable block in the function.
171 std::set<const BasicBlock*> Processed;
172 const BasicBlock *Entry = MF.getFunction()->begin();
174 bool Changed = false;
175 for (df_ext_iterator<const BasicBlock*, std::set<const BasicBlock*> >
176 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
178 Changed |= processBasicBlock(MF, *MBBMap[*I]);
180 assert(MBBMap.size() == Processed.size() &&
181 "Doesn't handle unreachable code yet!");
186 /// processBasicBlock - Loop over all of the instructions in the basic block,
187 /// transforming FP instructions into their stack form.
189 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
190 const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
191 bool Changed = false;
194 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
195 MachineInstr *MI = *I;
196 unsigned Flags = TII.get(MI->getOpcode()).TSFlags;
197 if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
198 continue; // Efficiently ignore non-fp insts!
200 MachineInstr *PrevMI = I == BB.begin() ? 0 : *(I-1);
202 ++NumFP; // Keep track of # of pseudo instrs
203 DEBUG(std::cerr << "\nFPInst:\t";
204 MI->print(std::cerr, MF.getTarget()));
206 // Get dead variables list now because the MI pointer may be deleted as part
208 LiveVariables::killed_iterator IB = LV->dead_begin(MI);
209 LiveVariables::killed_iterator IE = LV->dead_end(MI);
211 DEBUG(const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
212 LiveVariables::killed_iterator I = LV->killed_begin(MI);
213 LiveVariables::killed_iterator E = LV->killed_end(MI);
215 std::cerr << "Killed Operands:";
217 std::cerr << " %" << MRI->getName(I->second);
221 switch (Flags & X86II::FPTypeMask) {
222 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
223 case X86II::OneArgFP: handleOneArgFP(I); break;
225 case X86II::OneArgFPRW: // ST(0) = fsqrt(ST(0))
226 assert(0 && "FP instr type not handled yet!");
228 case X86II::TwoArgFP: handleTwoArgFP(I); break;
229 case X86II::SpecialFP: handleSpecialFP(I); break;
230 default: assert(0 && "Unknown FP Type!");
233 // Check to see if any of the values defined by this instruction are dead
234 // after definition. If so, pop them.
235 for (; IB != IE; ++IB) {
236 unsigned Reg = IB->second;
237 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
238 DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
239 ++I; // Insert fxch AFTER the instruction
240 moveToTop(Reg-X86::FP0, I); // Insert fxch if necessary
241 --I; // Move to fxch or old instruction
242 popStackAfter(I); // Pop the top of the stack, killing value
246 // Print out all of the instructions expanded to if -debug
247 DEBUG(if (*I == PrevMI) {
248 std::cerr<< "Just deleted pseudo instruction\n";
250 MachineBasicBlock::iterator Start = I;
251 // Rewind to first instruction newly inserted.
252 while (Start != BB.begin() && *(Start-1) != PrevMI) --Start;
253 std::cerr << "Inserted instructions:\n\t";
254 (*Start)->print(std::cerr, MF.getTarget());
255 while (++Start != I+1);
263 assert(StackTop == 0 && "Stack not empty at end of basic block?");
267 //===----------------------------------------------------------------------===//
268 // Efficient Lookup Table Support
269 //===----------------------------------------------------------------------===//
275 bool operator<(const TableEntry &TE) const { return from < TE.from; }
276 bool operator<(unsigned V) const { return from < V; }
280 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
281 for (unsigned i = 0; i != NumEntries-1; ++i)
282 if (!(Table[i] < Table[i+1])) return false;
286 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
287 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
288 if (I != Table+N && I->from == Opcode)
293 #define ARRAY_SIZE(TABLE) \
294 (sizeof(TABLE)/sizeof(TABLE[0]))
297 #define ASSERT_SORTED(TABLE)
299 #define ASSERT_SORTED(TABLE) \
300 { static bool TABLE##Checked = false; \
301 if (!TABLE##Checked) \
302 assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \
303 "All lookup tables must be sorted for efficient access!"); \
308 //===----------------------------------------------------------------------===//
310 //===----------------------------------------------------------------------===//
312 // PopTable - Sorted map of instructions to their popping version. The first
313 // element is an instruction, the second is the version which pops.
315 static const TableEntry PopTable[] = {
316 { X86::FADDrST0 , X86::FADDPrST0 },
318 { X86::FDIVRrST0, X86::FDIVRPrST0 },
319 { X86::FDIVrST0 , X86::FDIVPrST0 },
321 { X86::FISTr16 , X86::FISTPr16 },
322 { X86::FISTr32 , X86::FISTPr32 },
324 { X86::FMULrST0 , X86::FMULPrST0 },
326 { X86::FSTr32 , X86::FSTPr32 },
327 { X86::FSTr64 , X86::FSTPr64 },
328 { X86::FSTrr , X86::FSTPrr },
330 { X86::FSUBRrST0, X86::FSUBRPrST0 },
331 { X86::FSUBrST0 , X86::FSUBPrST0 },
333 { X86::FUCOMPr , X86::FUCOMPPr },
334 { X86::FUCOMr , X86::FUCOMPr },
337 /// popStackAfter - Pop the current value off of the top of the FP stack after
338 /// the specified instruction. This attempts to be sneaky and combine the pop
339 /// into the instruction itself if possible. The iterator is left pointing to
340 /// the last instruction, be it a new pop instruction inserted, or the old
341 /// instruction if it was modified in place.
343 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
344 ASSERT_SORTED(PopTable);
345 assert(StackTop > 0 && "Cannot pop empty stack!");
346 RegMap[Stack[--StackTop]] = ~0; // Update state
348 // Check to see if there is a popping version of this instruction...
349 int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), (*I)->getOpcode());
351 (*I)->setOpcode(Opcode);
352 if (Opcode == X86::FUCOMPPr)
353 (*I)->RemoveOperand(0);
355 } else { // Insert an explicit pop
356 MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(X86::ST0);
357 I = MBB->insert(I+1, MI);
361 static unsigned getFPReg(const MachineOperand &MO) {
362 assert(MO.isPhysicalRegister() && "Expected an FP register!");
363 unsigned Reg = MO.getReg();
364 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
365 return Reg - X86::FP0;
369 //===----------------------------------------------------------------------===//
370 // Instruction transformation implementation
371 //===----------------------------------------------------------------------===//
373 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
375 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
376 MachineInstr *MI = *I;
377 unsigned DestReg = getFPReg(MI->getOperand(0));
378 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
380 // Result gets pushed on the stack...
384 /// handleOneArgFP - fst ST(0), <mem>
386 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
387 MachineInstr *MI = *I;
388 assert(MI->getNumOperands() == 5 && "Can only handle fst* instructions!");
390 unsigned Reg = getFPReg(MI->getOperand(4));
391 bool KillsSrc = false;
392 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
393 E = LV->killed_end(MI); KI != E; ++KI)
394 KillsSrc |= KI->second == X86::FP0+Reg;
396 // FSTPr80 and FISTPr64 are strange because there are no non-popping versions.
397 // If we have one _and_ we don't want to pop the operand, duplicate the value
398 // on the stack instead of moving it. This ensure that popping the value is
401 if ((MI->getOpcode() == X86::FSTPr80 ||
402 MI->getOpcode() == X86::FISTPr64) && !KillsSrc) {
403 duplicateToTop(Reg, 7 /*temp register*/, I);
405 moveToTop(Reg, I); // Move to the top of the stack...
407 MI->RemoveOperand(4); // Remove explicit ST(0) operand
409 if (MI->getOpcode() == X86::FSTPr80 || MI->getOpcode() == X86::FISTPr64) {
410 assert(StackTop > 0 && "Stack empty??");
412 } else if (KillsSrc) { // Last use of operand?
417 //===----------------------------------------------------------------------===//
418 // Define tables of various ways to map pseudo instructions
421 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
422 static const TableEntry ForwardST0Table[] = {
423 { X86::FpADD, X86::FADDST0r },
424 { X86::FpDIV, X86::FDIVST0r },
425 { X86::FpMUL, X86::FMULST0r },
426 { X86::FpSUB, X86::FSUBST0r },
427 { X86::FpUCOM, X86::FUCOMr },
430 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
431 static const TableEntry ReverseST0Table[] = {
432 { X86::FpADD, X86::FADDST0r }, // commutative
433 { X86::FpDIV, X86::FDIVRST0r },
434 { X86::FpMUL, X86::FMULST0r }, // commutative
435 { X86::FpSUB, X86::FSUBRST0r },
439 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
440 static const TableEntry ForwardSTiTable[] = {
441 { X86::FpADD, X86::FADDrST0 }, // commutative
442 { X86::FpDIV, X86::FDIVRrST0 },
443 { X86::FpMUL, X86::FMULrST0 }, // commutative
444 { X86::FpSUB, X86::FSUBRrST0 },
445 { X86::FpUCOM, X86::FUCOMr },
448 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
449 static const TableEntry ReverseSTiTable[] = {
450 { X86::FpADD, X86::FADDrST0 },
451 { X86::FpDIV, X86::FDIVrST0 },
452 { X86::FpMUL, X86::FMULrST0 },
453 { X86::FpSUB, X86::FSUBrST0 },
458 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
459 /// instructions which need to be simplified and possibly transformed.
461 /// Result: ST(0) = fsub ST(0), ST(i)
462 /// ST(i) = fsub ST(0), ST(i)
463 /// ST(0) = fsubr ST(0), ST(i)
464 /// ST(i) = fsubr ST(0), ST(i)
466 /// In addition to three address instructions, this also handles the FpUCOM
467 /// instruction which only has two operands, but no destination. This
468 /// instruction is also annoying because there is no "reverse" form of it
471 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
472 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
473 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
474 MachineInstr *MI = *I;
476 unsigned NumOperands = MI->getNumOperands();
477 assert(NumOperands == 3 ||
478 (NumOperands == 2 && MI->getOpcode() == X86::FpUCOM) &&
479 "Illegal TwoArgFP instruction!");
480 unsigned Dest = getFPReg(MI->getOperand(0));
481 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
482 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
483 bool KillsOp0 = false, KillsOp1 = false;
485 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
486 E = LV->killed_end(MI); KI != E; ++KI) {
487 KillsOp0 |= (KI->second == X86::FP0+Op0);
488 KillsOp1 |= (KI->second == X86::FP0+Op1);
491 // If this is an FpUCOM instruction, we must make sure the first operand is on
492 // the top of stack, the other one can be anywhere...
493 if (MI->getOpcode() == X86::FpUCOM)
496 unsigned TOS = getStackEntry(0);
498 // One of our operands must be on the top of the stack. If neither is yet, we
500 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
501 // We can choose to move either operand to the top of the stack. If one of
502 // the operands is killed by this instruction, we want that one so that we
503 // can update right on top of the old version.
505 moveToTop(Op0, I); // Move dead operand to TOS.
507 } else if (KillsOp1) {
511 // All of the operands are live after this instruction executes, so we
512 // cannot update on top of any operand. Because of this, we must
513 // duplicate one of the stack elements to the top. It doesn't matter
514 // which one we pick.
516 duplicateToTop(Op0, Dest, I);
520 } else if (!KillsOp0 && !KillsOp1 && MI->getOpcode() != X86::FpUCOM) {
521 // If we DO have one of our operands at the top of the stack, but we don't
522 // have a dead operand, we must duplicate one of the operands to a new slot
524 duplicateToTop(Op0, Dest, I);
529 // Now we know that one of our operands is on the top of the stack, and at
530 // least one of our operands is killed by this instruction.
531 assert((TOS == Op0 || TOS == Op1) &&
532 (KillsOp0 || KillsOp1 || MI->getOpcode() == X86::FpUCOM) &&
533 "Stack conditions not set up right!");
535 // We decide which form to use based on what is on the top of the stack, and
536 // which operand is killed by this instruction.
537 const TableEntry *InstTable;
538 bool isForward = TOS == Op0;
539 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
542 InstTable = ForwardST0Table;
544 InstTable = ReverseST0Table;
547 InstTable = ForwardSTiTable;
549 InstTable = ReverseSTiTable;
552 int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode());
553 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
555 // NotTOS - The register which is not on the top of stack...
556 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
558 // Replace the old instruction with a new instruction
559 *I = BuildMI(Opcode, 1).addReg(getSTReg(NotTOS));
561 // If both operands are killed, pop one off of the stack in addition to
562 // overwriting the other one.
563 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
564 assert(!updateST0 && "Should have updated other operand!");
565 popStackAfter(I); // Pop the top of stack
568 // Insert an explicit pop of the "updated" operand for FUCOM
569 if (MI->getOpcode() == X86::FpUCOM) {
570 if (KillsOp0 && !KillsOp1)
571 popStackAfter(I); // If we kill the first operand, pop it!
572 else if (KillsOp1 && Op0 != Op1) {
573 if (getStackEntry(0) == Op1) {
574 popStackAfter(I); // If it's right at the top of stack, just pop it
576 // Otherwise, move the top of stack into the dead slot, killing the
577 // operand without having to add in an explicit xchg then pop.
579 unsigned STReg = getSTReg(Op1);
580 unsigned OldSlot = getSlot(Op1);
581 unsigned TopReg = Stack[StackTop-1];
582 Stack[OldSlot] = TopReg;
583 RegMap[TopReg] = OldSlot;
585 Stack[--StackTop] = ~0;
587 MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(STReg);
588 I = MBB->insert(I+1, MI);
593 // Update stack information so that we know the destination register is now on
595 if (MI->getOpcode() != X86::FpUCOM) {
596 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
597 assert(UpdatedSlot < StackTop && Dest < 7);
598 Stack[UpdatedSlot] = Dest;
599 RegMap[Dest] = UpdatedSlot;
601 delete MI; // Remove the old instruction
605 /// handleSpecialFP - Handle special instructions which behave unlike other
606 /// floating point instructions. This is primarily intended for use by pseudo
609 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
610 MachineInstr *MI = *I;
611 switch (MI->getOpcode()) {
612 default: assert(0 && "Unknown SpecialFP instruction!");
613 case X86::FpGETRESULT: // Appears immediately after a call returning FP type!
614 assert(StackTop == 0 && "Stack should be empty after a call!");
615 pushReg(getFPReg(MI->getOperand(0)));
617 case X86::FpSETRESULT:
618 assert(StackTop == 1 && "Stack should have one element on it to return!");
619 --StackTop; // "Forget" we have something on the top of stack!
622 unsigned SrcReg = getFPReg(MI->getOperand(1));
623 unsigned DestReg = getFPReg(MI->getOperand(0));
624 bool KillsSrc = false;
625 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
626 E = LV->killed_end(MI); KI != E; ++KI)
627 KillsSrc |= KI->second == X86::FP0+SrcReg;
630 // If the input operand is killed, we can just change the owner of the
631 // incoming stack slot into the result.
632 unsigned Slot = getSlot(SrcReg);
633 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
634 Stack[Slot] = DestReg;
635 RegMap[DestReg] = Slot;
638 // For FMOV we just duplicate the specified value to a new stack slot.
639 // This could be made better, but would require substantial changes.
640 duplicateToTop(SrcReg, DestReg, I);
646 I = MBB->erase(I)-1; // Remove the pseudo instruction