1 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as AT&T-style
13 //===----------------------------------------------------------------------===//
15 #include "X86ATTInstPrinter.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "MCTargetDesc/X86MCTargetDesc.h"
18 #include "X86InstComments.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/Format.h"
26 #include "llvm/Support/FormattedStream.h"
30 #define DEBUG_TYPE "asm-printer"
32 // Include the auto-generated portion of the assembly writer.
33 #define PRINT_ALIAS_INSTR
34 #include "X86GenAsmWriter.inc"
36 void X86ATTInstPrinter::printRegName(raw_ostream &OS,
37 unsigned RegNo) const {
39 << '%' << getRegisterName(RegNo)
43 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
45 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
46 uint64_t TSFlags = Desc.TSFlags;
48 if (TSFlags & X86II::LOCK)
51 // Try to print any aliases first.
52 if (!printAliasInstr(MI, OS))
53 printInstruction(MI, OS);
55 // Next always print the annotation.
56 printAnnotation(OS, Annot);
58 // If verbose assembly is enabled, we can print some informative comments.
60 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
63 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
65 int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
67 default: llvm_unreachable("Invalid ssecc argument!");
68 case 0: O << "eq"; break;
69 case 1: O << "lt"; break;
70 case 2: O << "le"; break;
71 case 3: O << "unord"; break;
72 case 4: O << "neq"; break;
73 case 5: O << "nlt"; break;
74 case 6: O << "nle"; break;
75 case 7: O << "ord"; break;
76 case 8: O << "eq_uq"; break;
77 case 9: O << "nge"; break;
78 case 0xa: O << "ngt"; break;
79 case 0xb: O << "false"; break;
80 case 0xc: O << "neq_oq"; break;
81 case 0xd: O << "ge"; break;
82 case 0xe: O << "gt"; break;
83 case 0xf: O << "true"; break;
87 void X86ATTInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
89 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
91 default: llvm_unreachable("Invalid avxcc argument!");
92 case 0: O << "eq"; break;
93 case 1: O << "lt"; break;
94 case 2: O << "le"; break;
95 case 3: O << "unord"; break;
96 case 4: O << "neq"; break;
97 case 5: O << "nlt"; break;
98 case 6: O << "nle"; break;
99 case 7: O << "ord"; break;
100 case 8: O << "eq_uq"; break;
101 case 9: O << "nge"; break;
102 case 0xa: O << "ngt"; break;
103 case 0xb: O << "false"; break;
104 case 0xc: O << "neq_oq"; break;
105 case 0xd: O << "ge"; break;
106 case 0xe: O << "gt"; break;
107 case 0xf: O << "true"; break;
108 case 0x10: O << "eq_os"; break;
109 case 0x11: O << "lt_oq"; break;
110 case 0x12: O << "le_oq"; break;
111 case 0x13: O << "unord_s"; break;
112 case 0x14: O << "neq_us"; break;
113 case 0x15: O << "nlt_uq"; break;
114 case 0x16: O << "nle_uq"; break;
115 case 0x17: O << "ord_s"; break;
116 case 0x18: O << "eq_us"; break;
117 case 0x19: O << "nge_uq"; break;
118 case 0x1a: O << "ngt_uq"; break;
119 case 0x1b: O << "false_os"; break;
120 case 0x1c: O << "neq_os"; break;
121 case 0x1d: O << "ge_oq"; break;
122 case 0x1e: O << "gt_oq"; break;
123 case 0x1f: O << "true_us"; break;
127 void X86ATTInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
129 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
131 case 0: O << "{rn-sae}"; break;
132 case 1: O << "{rd-sae}"; break;
133 case 2: O << "{ru-sae}"; break;
134 case 3: O << "{rz-sae}"; break;
137 /// printPCRelImm - This is used to print an immediate value that ends up
138 /// being encoded as a pc-relative value (e.g. for jumps and calls). These
139 /// print slightly differently than normal immediates. For example, a $ is not
141 void X86ATTInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
143 const MCOperand &Op = MI->getOperand(OpNo);
145 O << formatImm(Op.getImm());
147 assert(Op.isExpr() && "unknown pcrel immediate operand");
148 // If a symbolic branch target was added as a constant expression then print
149 // that address in hex.
150 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
152 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
153 O << formatHex((uint64_t)Address);
156 // Otherwise, just print the expression.
162 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
164 const MCOperand &Op = MI->getOperand(OpNo);
166 printRegName(O, Op.getReg());
167 } else if (Op.isImm()) {
168 // Print X86 immediates as signed values.
170 << '$' << formatImm((int64_t)Op.getImm())
173 if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256))
174 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
177 assert(Op.isExpr() && "unknown operand kind in printOperand");
179 << '$' << *Op.getExpr()
184 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
186 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
187 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
188 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
189 const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg);
191 O << markup("<mem:");
193 // If this has a segment register, print it.
194 if (SegReg.getReg()) {
195 printOperand(MI, Op+X86::AddrSegmentReg, O);
199 if (DispSpec.isImm()) {
200 int64_t DispVal = DispSpec.getImm();
201 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
202 O << formatImm(DispVal);
204 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
205 O << *DispSpec.getExpr();
208 if (IndexReg.getReg() || BaseReg.getReg()) {
210 if (BaseReg.getReg())
211 printOperand(MI, Op+X86::AddrBaseReg, O);
213 if (IndexReg.getReg()) {
215 printOperand(MI, Op+X86::AddrIndexReg, O);
216 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
220 << ScaleVal // never printed in hex.
230 void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
232 const MCOperand &SegReg = MI->getOperand(Op+1);
234 O << markup("<mem:");
236 // If this has a segment register, print it.
237 if (SegReg.getReg()) {
238 printOperand(MI, Op+1, O);
243 printOperand(MI, Op, O);
249 void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
251 O << markup("<mem:");
254 printOperand(MI, Op, O);
260 void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
262 const MCOperand &DispSpec = MI->getOperand(Op);
263 const MCOperand &SegReg = MI->getOperand(Op+1);
265 O << markup("<mem:");
267 // If this has a segment register, print it.
268 if (SegReg.getReg()) {
269 printOperand(MI, Op+1, O);
273 if (DispSpec.isImm()) {
274 O << formatImm(DispSpec.getImm());
276 assert(DispSpec.isExpr() && "non-immediate displacement?");
277 O << *DispSpec.getExpr();