1 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as AT&T-style
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "X86ATTInstPrinter.h"
17 #include "X86InstComments.h"
18 #include "MCTargetDesc/X86MCTargetDesc.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/Format.h"
24 #include "llvm/Support/FormattedStream.h"
28 // Include the auto-generated portion of the assembly writer.
29 #define GET_INSTRUCTION_NAME
30 #define PRINT_ALIAS_INSTR
31 #include "X86GenAsmWriter.inc"
33 X86ATTInstPrinter::X86ATTInstPrinter(const MCAsmInfo &MAI)
34 : MCInstPrinter(MAI) {
37 void X86ATTInstPrinter::printRegName(raw_ostream &OS,
38 unsigned RegNo) const {
39 OS << '%' << getRegisterName(RegNo);
42 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
44 // Try to print any aliases first.
45 if (!printAliasInstr(MI, OS))
46 printInstruction(MI, OS);
48 // If verbose assembly is enabled, we can print some informative comments.
50 printAnnotation(OS, Annot);
51 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
55 StringRef X86ATTInstPrinter::getOpcodeName(unsigned Opcode) const {
56 return getInstructionName(Opcode);
59 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
61 switch (MI->getOperand(Op).getImm()) {
62 default: llvm_unreachable("Invalid ssecc argument!");
63 case 0: O << "eq"; break;
64 case 1: O << "lt"; break;
65 case 2: O << "le"; break;
66 case 3: O << "unord"; break;
67 case 4: O << "neq"; break;
68 case 5: O << "nlt"; break;
69 case 6: O << "nle"; break;
70 case 7: O << "ord"; break;
71 case 8: O << "eq_uq"; break;
72 case 9: O << "nge"; break;
73 case 0xa: O << "ngt"; break;
74 case 0xb: O << "false"; break;
75 case 0xc: O << "neq_oq"; break;
76 case 0xd: O << "ge"; break;
77 case 0xe: O << "gt"; break;
78 case 0xf: O << "true"; break;
79 case 0x10: O << "eq_os"; break;
80 case 0x11: O << "lt_oq"; break;
81 case 0x12: O << "le_oq"; break;
82 case 0x13: O << "unord_s"; break;
83 case 0x14: O << "neq_us"; break;
84 case 0x15: O << "nlt_uq"; break;
85 case 0x16: O << "nle_uq"; break;
86 case 0x17: O << "ord_s"; break;
87 case 0x18: O << "eq_us"; break;
88 case 0x19: O << "nge_uq"; break;
89 case 0x1a: O << "ngt_uq"; break;
90 case 0x1b: O << "false_os"; break;
91 case 0x1c: O << "neq_os"; break;
92 case 0x1d: O << "ge_oq"; break;
93 case 0x1e: O << "gt_oq"; break;
94 case 0x1f: O << "true_us"; break;
98 /// print_pcrel_imm - This is used to print an immediate value that ends up
99 /// being encoded as a pc-relative value (e.g. for jumps and calls). These
100 /// print slightly differently than normal immediates. For example, a $ is not
102 void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo,
104 const MCOperand &Op = MI->getOperand(OpNo);
106 // Print this as a signed 32-bit value.
107 O << (int)Op.getImm();
109 assert(Op.isExpr() && "unknown pcrel immediate operand");
114 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
116 const MCOperand &Op = MI->getOperand(OpNo);
118 O << '%' << getRegisterName(Op.getReg());
119 } else if (Op.isImm()) {
120 // Print X86 immediates as signed values.
121 O << '$' << (int64_t)Op.getImm();
123 if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256))
124 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
127 assert(Op.isExpr() && "unknown operand kind in printOperand");
128 O << '$' << *Op.getExpr();
132 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
134 const MCOperand &BaseReg = MI->getOperand(Op);
135 const MCOperand &IndexReg = MI->getOperand(Op+2);
136 const MCOperand &DispSpec = MI->getOperand(Op+3);
137 const MCOperand &SegReg = MI->getOperand(Op+4);
139 // If this has a segment register, print it.
140 if (SegReg.getReg()) {
141 printOperand(MI, Op+4, O);
145 if (DispSpec.isImm()) {
146 int64_t DispVal = DispSpec.getImm();
147 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
150 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
151 O << *DispSpec.getExpr();
154 if (IndexReg.getReg() || BaseReg.getReg()) {
156 if (BaseReg.getReg())
157 printOperand(MI, Op, O);
159 if (IndexReg.getReg()) {
161 printOperand(MI, Op+2, O);
162 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
164 O << ',' << ScaleVal;