1 //===-- X86IntelInstPrinter.cpp - AT&T assembly instruction printing ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as AT&T-style
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "X86IntelInstPrinter.h"
17 #include "X86InstComments.h"
18 #include "MCTargetDesc/X86MCTargetDesc.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/FormattedStream.h"
27 // Include the auto-generated portion of the assembly writer.
28 #define GET_INSTRUCTION_NAME
29 #include "X86GenAsmWriter1.inc"
31 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
32 OS << getRegisterName(RegNo);
35 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
37 printInstruction(MI, OS);
39 // Next always print the annotation.
40 printAnnotation(OS, Annot);
42 // If verbose assembly is enabled, we can print some informative comments.
44 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
46 StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
47 return getInstructionName(Opcode);
50 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
52 switch (MI->getOperand(Op).getImm()) {
53 default: llvm_unreachable("Invalid ssecc argument!");
54 case 0: O << "eq"; break;
55 case 1: O << "lt"; break;
56 case 2: O << "le"; break;
57 case 3: O << "unord"; break;
58 case 4: O << "neq"; break;
59 case 5: O << "nlt"; break;
60 case 6: O << "nle"; break;
61 case 7: O << "ord"; break;
62 case 8: O << "eq_uq"; break;
63 case 9: O << "nge"; break;
64 case 0xa: O << "ngt"; break;
65 case 0xb: O << "false"; break;
66 case 0xc: O << "neq_oq"; break;
67 case 0xd: O << "ge"; break;
68 case 0xe: O << "gt"; break;
69 case 0xf: O << "true"; break;
70 case 0x10: O << "eq_os"; break;
71 case 0x11: O << "lt_oq"; break;
72 case 0x12: O << "le_oq"; break;
73 case 0x13: O << "unord_s"; break;
74 case 0x14: O << "neq_us"; break;
75 case 0x15: O << "nlt_uq"; break;
76 case 0x16: O << "nle_uq"; break;
77 case 0x17: O << "ord_s"; break;
78 case 0x18: O << "eq_us"; break;
79 case 0x19: O << "nge_uq"; break;
80 case 0x1a: O << "ngt_uq"; break;
81 case 0x1b: O << "false_os"; break;
82 case 0x1c: O << "neq_os"; break;
83 case 0x1d: O << "ge_oq"; break;
84 case 0x1e: O << "gt_oq"; break;
85 case 0x1f: O << "true_us"; break;
90 /// print_pcrel_imm - This is used to print an immediate value that ends up
91 /// being encoded as a pc-relative value.
92 void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo,
94 const MCOperand &Op = MI->getOperand(OpNo);
98 assert(Op.isExpr() && "unknown pcrel immediate operand");
99 // If a symbolic branch target was added as a constant expression then print
100 // that address in hex.
101 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
103 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
105 O.write_hex(Address);
108 // Otherwise, just print the expression.
114 static void PrintRegName(raw_ostream &O, StringRef RegName) {
115 for (unsigned i = 0, e = RegName.size(); i != e; ++i)
116 O << (char)toupper(RegName[i]);
119 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
121 const MCOperand &Op = MI->getOperand(OpNo);
123 PrintRegName(O, getRegisterName(Op.getReg()));
124 } else if (Op.isImm()) {
127 assert(Op.isExpr() && "unknown operand kind in printOperand");
132 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
134 const MCOperand &BaseReg = MI->getOperand(Op);
135 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
136 const MCOperand &IndexReg = MI->getOperand(Op+2);
137 const MCOperand &DispSpec = MI->getOperand(Op+3);
138 const MCOperand &SegReg = MI->getOperand(Op+4);
140 // If this has a segment register, print it.
141 if (SegReg.getReg()) {
142 printOperand(MI, Op+4, O);
148 bool NeedPlus = false;
149 if (BaseReg.getReg()) {
150 printOperand(MI, Op, O);
154 if (IndexReg.getReg()) {
155 if (NeedPlus) O << " + ";
157 O << ScaleVal << '*';
158 printOperand(MI, Op+2, O);
163 if (!DispSpec.isImm()) {
164 if (NeedPlus) O << " + ";
165 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
166 O << *DispSpec.getExpr();
168 int64_t DispVal = DispSpec.getImm();
169 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {