1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 target
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/iTerminators.h"
12 #include "llvm/iOperators.h"
13 #include "llvm/iOther.h"
14 #include "llvm/iPHINode.h"
15 #include "llvm/iMemory.h"
16 #include "llvm/Type.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Pass.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SSARegMap.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Support/InstVisitor.h"
27 #include "llvm/Target/MRegisterInfo.h"
30 /// BMI - A special BuildMI variant that takes an iterator to insert the
31 /// instruction at as well as a basic block.
32 /// this is the version for when you have a destination register in mind.
33 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
34 MachineBasicBlock::iterator &I,
38 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
39 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
40 I = MBB->insert(I, MI)+1;
41 return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
44 /// BMI - A special BuildMI variant that takes an iterator to insert the
45 /// instruction at as well as a basic block.
46 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
47 MachineBasicBlock::iterator &I,
49 unsigned NumOperands) {
50 assert(I > MBB->begin() && I <= MBB->end() && "Bad iterator!");
51 MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
52 I = MBB->insert(I, MI)+1;
53 return MachineInstrBuilder(MI);
58 struct ISel : public FunctionPass, InstVisitor<ISel> {
60 MachineFunction *F; // The function we are compiling into
61 MachineBasicBlock *BB; // The current MBB we are compiling
63 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
65 // MBBMap - Mapping between LLVM BB -> Machine BB
66 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
68 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
70 /// runOnFunction - Top level implementation of instruction selection for
71 /// the entire function.
73 bool runOnFunction(Function &Fn) {
74 F = &MachineFunction::construct(&Fn, TM);
76 // Create all of the machine basic blocks for the function...
77 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
78 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
81 LoadArgumentsToVirtualRegs(Fn);
83 // Instruction select everything except PHI nodes
86 // Select the PHI nodes
92 return false; // We never modify the LLVM itself.
95 virtual const char *getPassName() const {
96 return "X86 Simple Instruction Selection";
99 /// visitBasicBlock - This method is called when we are visiting a new basic
100 /// block. This simply creates a new MachineBasicBlock to emit code into
101 /// and adds it to the current MachineFunction. Subsequent visit* for
102 /// instructions will be invoked for all instructions in the basic block.
104 void visitBasicBlock(BasicBlock &LLVM_BB) {
105 BB = MBBMap[&LLVM_BB];
108 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
109 /// from the stack into virtual registers.
111 void LoadArgumentsToVirtualRegs(Function &F);
113 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
114 /// because we have to generate our sources into the source basic blocks,
115 /// not the current one.
117 void SelectPHINodes();
119 // Visitation methods for various instructions. These methods simply emit
120 // fixed X86 code for each instruction.
123 // Control flow operators
124 void visitReturnInst(ReturnInst &RI);
125 void visitBranchInst(BranchInst &BI);
130 ValueRecord(unsigned R, const Type *T) : Reg(R), Ty(T) {}
132 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
133 const std::vector<ValueRecord> &Args);
134 void visitCallInst(CallInst &I);
136 // Arithmetic operators
137 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
138 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
139 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
140 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
141 unsigned DestReg, const Type *DestTy,
142 unsigned Op0Reg, unsigned Op1Reg);
143 void visitMul(BinaryOperator &B);
145 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
146 void visitRem(BinaryOperator &B) { visitDivRem(B); }
147 void visitDivRem(BinaryOperator &B);
150 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
151 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
152 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
154 // Comparison operators...
155 void visitSetCondInst(SetCondInst &I);
156 bool EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1);
158 // Memory Instructions
159 MachineInstr *doFPLoad(MachineBasicBlock *MBB,
160 MachineBasicBlock::iterator &MBBI,
161 const Type *Ty, unsigned DestReg);
162 void visitLoadInst(LoadInst &I);
163 void doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg);
164 void visitStoreInst(StoreInst &I);
165 void visitGetElementPtrInst(GetElementPtrInst &I);
166 void visitAllocaInst(AllocaInst &I);
167 void visitMallocInst(MallocInst &I);
168 void visitFreeInst(FreeInst &I);
171 void visitShiftInst(ShiftInst &I);
172 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
173 void visitCastInst(CastInst &I);
175 void visitInstruction(Instruction &I) {
176 std::cerr << "Cannot instruction select: " << I;
180 /// promote32 - Make a value 32-bits wide, and put it somewhere.
182 void promote32(unsigned targetReg, const ValueRecord &VR);
184 /// EmitByteSwap - Byteswap SrcReg into DestReg.
186 void EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class);
188 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
189 /// constant expression GEP support.
191 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator&IP,
192 Value *Src, User::op_iterator IdxBegin,
193 User::op_iterator IdxEnd, unsigned TargetReg);
195 /// emitCastOperation - Common code shared between visitCastInst and
196 /// constant expression cast support.
197 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
198 Value *Src, const Type *DestTy, unsigned TargetReg);
200 /// copyConstantToRegister - Output the instructions required to put the
201 /// specified constant into the specified register.
203 void copyConstantToRegister(MachineBasicBlock *MBB,
204 MachineBasicBlock::iterator &MBBI,
205 Constant *C, unsigned Reg);
207 /// makeAnotherReg - This method returns the next register number we haven't
210 /// Long values are handled somewhat specially. They are always allocated
211 /// as pairs of 32 bit integer values. The register number returned is the
212 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
213 /// of the long value.
215 unsigned makeAnotherReg(const Type *Ty) {
216 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
217 const TargetRegisterClass *RC =
218 TM.getRegisterInfo()->getRegClassForType(Type::IntTy);
219 // Create the lower part
220 F->getSSARegMap()->createVirtualRegister(RC);
221 // Create the upper part.
222 return F->getSSARegMap()->createVirtualRegister(RC)-1;
225 // Add the mapping of regnumber => reg class to MachineFunction
226 const TargetRegisterClass *RC =
227 TM.getRegisterInfo()->getRegClassForType(Ty);
228 return F->getSSARegMap()->createVirtualRegister(RC);
231 /// getReg - This method turns an LLVM value into a register number. This
232 /// is guaranteed to produce the same register number for a particular value
233 /// every time it is queried.
235 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
236 unsigned getReg(Value *V) {
237 // Just append to the end of the current bb.
238 MachineBasicBlock::iterator It = BB->end();
239 return getReg(V, BB, It);
241 unsigned getReg(Value *V, MachineBasicBlock *MBB,
242 MachineBasicBlock::iterator &IPt) {
243 unsigned &Reg = RegMap[V];
245 Reg = makeAnotherReg(V->getType());
249 // If this operand is a constant, emit the code to copy the constant into
250 // the register here...
252 if (Constant *C = dyn_cast<Constant>(V)) {
253 copyConstantToRegister(MBB, IPt, C, Reg);
254 RegMap.erase(V); // Assign a new name to this constant if ref'd again
255 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
256 // Move the address of the global into the register
257 BMI(MBB, IPt, X86::MOVir32, 1, Reg).addGlobalAddress(GV);
258 RegMap.erase(V); // Assign a new name to this address if ref'd again
266 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
270 cByte, cShort, cInt, cFP, cLong
273 /// getClass - Turn a primitive type into a "class" number which is based on the
274 /// size of the type, and whether or not it is floating point.
276 static inline TypeClass getClass(const Type *Ty) {
277 switch (Ty->getPrimitiveID()) {
278 case Type::SByteTyID:
279 case Type::UByteTyID: return cByte; // Byte operands are class #0
280 case Type::ShortTyID:
281 case Type::UShortTyID: return cShort; // Short operands are class #1
284 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
286 case Type::FloatTyID:
287 case Type::DoubleTyID: return cFP; // Floating Point is #3
290 case Type::ULongTyID: return cLong; // Longs are class #4
292 assert(0 && "Invalid type to getClass!");
293 return cByte; // not reached
297 // getClassB - Just like getClass, but treat boolean values as bytes.
298 static inline TypeClass getClassB(const Type *Ty) {
299 if (Ty == Type::BoolTy) return cByte;
304 /// copyConstantToRegister - Output the instructions required to put the
305 /// specified constant into the specified register.
307 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
308 MachineBasicBlock::iterator &IP,
309 Constant *C, unsigned R) {
310 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
311 if (CE->getOpcode() == Instruction::GetElementPtr) {
312 emitGEPOperation(MBB, IP, CE->getOperand(0),
313 CE->op_begin()+1, CE->op_end(), R);
315 } else if (CE->getOpcode() == Instruction::Cast) {
316 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
320 std::cerr << "Offending expr: " << C << "\n";
321 assert(0 && "Constant expressions not yet handled!\n");
324 if (C->getType()->isIntegral()) {
325 unsigned Class = getClassB(C->getType());
327 if (Class == cLong) {
328 // Copy the value into the register pair.
330 if (C->getType()->isSigned())
331 Val = cast<ConstantSInt>(C)->getValue();
333 Val = cast<ConstantUInt>(C)->getValue();
335 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(Val & 0xFFFFFFFF);
336 BMI(MBB, IP, X86::MOVir32, 1, R+1).addZImm(Val >> 32);
340 assert(Class <= cInt && "Type not handled yet!");
342 static const unsigned IntegralOpcodeTab[] = {
343 X86::MOVir8, X86::MOVir16, X86::MOVir32
346 if (C->getType() == Type::BoolTy) {
347 BMI(MBB, IP, X86::MOVir8, 1, R).addZImm(C == ConstantBool::True);
348 } else if (C->getType()->isSigned()) {
349 ConstantSInt *CSI = cast<ConstantSInt>(C);
350 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CSI->getValue());
352 ConstantUInt *CUI = cast<ConstantUInt>(C);
353 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
355 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
356 double Value = CFP->getValue();
358 BMI(MBB, IP, X86::FLD0, 0, R);
359 else if (Value == +1.0)
360 BMI(MBB, IP, X86::FLD1, 0, R);
362 // Otherwise we need to spill the constant to memory...
363 MachineConstantPool *CP = F->getConstantPool();
364 unsigned CPI = CP->getConstantPoolIndex(CFP);
365 addConstantPoolReference(doFPLoad(MBB, IP, CFP->getType(), R), CPI);
368 } else if (isa<ConstantPointerNull>(C)) {
369 // Copy zero (null pointer) to the register.
370 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0);
371 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
372 unsigned SrcReg = getReg(CPR->getValue(), MBB, IP);
373 BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg);
375 std::cerr << "Offending constant: " << C << "\n";
376 assert(0 && "Type not handled yet!");
380 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
381 /// the stack into virtual registers.
383 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
384 // Emit instructions to load the arguments... On entry to a function on the
385 // X86, the stack frame looks like this:
387 // [ESP] -- return address
388 // [ESP + 4] -- first argument (leftmost lexically)
389 // [ESP + 8] -- second argument, if first argument is four bytes in size
392 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
393 MachineFrameInfo *MFI = F->getFrameInfo();
395 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
396 unsigned Reg = getReg(*I);
398 int FI; // Frame object index
399 switch (getClassB(I->getType())) {
401 FI = MFI->CreateFixedObject(1, ArgOffset);
402 addFrameReference(BuildMI(BB, X86::MOVmr8, 4, Reg), FI);
405 FI = MFI->CreateFixedObject(2, ArgOffset);
406 addFrameReference(BuildMI(BB, X86::MOVmr16, 4, Reg), FI);
409 FI = MFI->CreateFixedObject(4, ArgOffset);
410 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
413 FI = MFI->CreateFixedObject(8, ArgOffset);
414 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
415 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg+1), FI, 4);
416 ArgOffset += 4; // longs require 4 additional bytes
420 if (I->getType() == Type::FloatTy) {
421 Opcode = X86::FLDr32;
422 FI = MFI->CreateFixedObject(4, ArgOffset);
424 Opcode = X86::FLDr64;
425 FI = MFI->CreateFixedObject(8, ArgOffset);
426 ArgOffset += 4; // doubles require 4 additional bytes
428 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
431 assert(0 && "Unhandled argument type!");
433 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
438 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
439 /// because we have to generate our sources into the source basic blocks, not
442 void ISel::SelectPHINodes() {
443 const TargetInstrInfo &TII = TM.getInstrInfo();
444 const Function &LF = *F->getFunction(); // The LLVM function...
445 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
446 const BasicBlock *BB = I;
447 MachineBasicBlock *MBB = MBBMap[I];
449 // Loop over all of the PHI nodes in the LLVM basic block...
450 unsigned NumPHIs = 0;
451 for (BasicBlock::const_iterator I = BB->begin();
452 PHINode *PN = (PHINode*)dyn_cast<PHINode>(I); ++I) {
454 // Create a new machine instr PHI node, and insert it.
455 unsigned PHIReg = getReg(*PN);
456 MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
457 MBB->insert(MBB->begin()+NumPHIs++, PhiMI);
459 MachineInstr *LongPhiMI = 0;
460 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
461 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
462 MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
465 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
466 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
468 // Get the incoming value into a virtual register. If it is not already
469 // available in a virtual register, insert the computation code into
472 MachineBasicBlock::iterator PI = PredMBB->end();
473 while (PI != PredMBB->begin() &&
474 TII.isTerminatorInstr((*(PI-1))->getOpcode()))
476 unsigned ValReg = getReg(PN->getIncomingValue(i), PredMBB, PI);
477 PhiMI->addRegOperand(ValReg);
478 PhiMI->addMachineBasicBlockOperand(PredMBB);
480 LongPhiMI->addRegOperand(ValReg+1);
481 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
488 // canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
489 // the conditional branch instruction which is the only user of the cc
490 // instruction. This is the case if the conditional branch is the only user of
491 // the setcc, and if the setcc is in the same basic block as the conditional
492 // branch. We also don't handle long arguments below, so we reject them here as
495 static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
496 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
497 if (SCI->use_size() == 1 && isa<BranchInst>(SCI->use_back()) &&
498 SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
499 const Type *Ty = SCI->getOperand(0)->getType();
500 if (Ty != Type::LongTy && Ty != Type::ULongTy)
506 // Return a fixed numbering for setcc instructions which does not depend on the
507 // order of the opcodes.
509 static unsigned getSetCCNumber(unsigned Opcode) {
511 default: assert(0 && "Unknown setcc instruction!");
512 case Instruction::SetEQ: return 0;
513 case Instruction::SetNE: return 1;
514 case Instruction::SetLT: return 2;
515 case Instruction::SetGE: return 3;
516 case Instruction::SetGT: return 4;
517 case Instruction::SetLE: return 5;
521 // LLVM -> X86 signed X86 unsigned
522 // ----- ---------- ------------
523 // seteq -> sete sete
524 // setne -> setne setne
525 // setlt -> setl setb
526 // setge -> setge setae
527 // setgt -> setg seta
528 // setle -> setle setbe
529 static const unsigned SetCCOpcodeTab[2][6] = {
530 {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr},
531 {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr},
534 bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
536 // The arguments are already supposed to be of the same type.
537 const Type *CompTy = Op0->getType();
538 bool isSigned = CompTy->isSigned();
539 unsigned reg1 = getReg(Op0);
540 unsigned reg2 = getReg(Op1);
542 unsigned Class = getClassB(CompTy);
544 default: assert(0 && "Unknown type class!");
545 // Emit: cmp <var1>, <var2> (do the comparison). We can
546 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
549 BuildMI(BB, X86::CMPrr8, 2).addReg(reg1).addReg(reg2);
552 BuildMI(BB, X86::CMPrr16, 2).addReg(reg1).addReg(reg2);
555 BuildMI(BB, X86::CMPrr32, 2).addReg(reg1).addReg(reg2);
558 BuildMI(BB, X86::FpUCOM, 2).addReg(reg1).addReg(reg2);
559 BuildMI(BB, X86::FNSTSWr8, 0);
560 BuildMI(BB, X86::SAHF, 1);
561 isSigned = false; // Compare with unsigned operators
565 if (OpNum < 2) { // seteq, setne
566 unsigned LoTmp = makeAnotherReg(Type::IntTy);
567 unsigned HiTmp = makeAnotherReg(Type::IntTy);
568 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
569 BuildMI(BB, X86::XORrr32, 2, LoTmp).addReg(reg1).addReg(reg2);
570 BuildMI(BB, X86::XORrr32, 2, HiTmp).addReg(reg1+1).addReg(reg2+1);
571 BuildMI(BB, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
572 break; // Allow the sete or setne to be generated from flags set by OR
574 // Emit a sequence of code which compares the high and low parts once
575 // each, then uses a conditional move to handle the overflow case. For
576 // example, a setlt for long would generate code like this:
578 // AL = lo(op1) < lo(op2) // Signedness depends on operands
579 // BL = hi(op1) < hi(op2) // Always unsigned comparison
580 // dest = hi(op1) == hi(op2) ? AL : BL;
583 // FIXME: This would be much better if we had hierarchical register
584 // classes! Until then, hardcode registers so that we can deal with their
585 // aliases (because we don't have conditional byte moves).
587 BuildMI(BB, X86::CMPrr32, 2).addReg(reg1).addReg(reg2);
588 BuildMI(BB, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
589 BuildMI(BB, X86::CMPrr32, 2).addReg(reg1+1).addReg(reg2+1);
590 BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
591 BuildMI(BB, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
592 // NOTE: visitSetCondInst knows that the value is dumped into the BL
593 // register at this point for long values...
601 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
602 /// register, then move it to wherever the result should be.
604 void ISel::visitSetCondInst(SetCondInst &I) {
605 if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
607 unsigned OpNum = getSetCCNumber(I.getOpcode());
608 unsigned DestReg = getReg(I);
609 bool isSigned = EmitComparisonGetSignedness(OpNum, I.getOperand(0),
612 if (getClassB(I.getOperand(0)->getType()) != cLong || OpNum < 2) {
613 // Handle normal comparisons with a setcc instruction...
614 BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, DestReg);
616 // Handle long comparisons by copying the value which is already in BL into
617 // the register we want...
618 BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(X86::BL);
622 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
623 /// operand, in the specified target register.
624 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
625 bool isUnsigned = VR.Ty->isUnsigned();
626 switch (getClassB(VR.Ty)) {
628 // Extend value into target register (8->32)
630 BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(VR.Reg);
632 BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(VR.Reg);
635 // Extend value into target register (16->32)
637 BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(VR.Reg);
639 BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(VR.Reg);
642 // Move value into target register (32->32)
643 BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(VR.Reg);
646 assert(0 && "Unpromotable operand class in promote32");
650 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
651 /// we have the following possibilities:
653 /// ret void: No return value, simply emit a 'ret' instruction
654 /// ret sbyte, ubyte : Extend value into EAX and return
655 /// ret short, ushort: Extend value into EAX and return
656 /// ret int, uint : Move value into EAX and return
657 /// ret pointer : Move value into EAX and return
658 /// ret long, ulong : Move value into EAX/EDX and return
659 /// ret float/double : Top of FP stack
661 void ISel::visitReturnInst(ReturnInst &I) {
662 if (I.getNumOperands() == 0) {
663 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
667 Value *RetVal = I.getOperand(0);
668 unsigned RetReg = getReg(RetVal);
669 switch (getClassB(RetVal->getType())) {
670 case cByte: // integral return values: extend or move into EAX and return
673 promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
675 case cFP: // Floats & Doubles: Return in ST(0)
676 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
679 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
680 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
685 // Emit a 'ret' instruction
686 BuildMI(BB, X86::RET, 0);
689 // getBlockAfter - Return the basic block which occurs lexically after the
691 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
692 Function::iterator I = BB; ++I; // Get iterator to next block
693 return I != BB->getParent()->end() ? &*I : 0;
696 /// visitBranchInst - Handle conditional and unconditional branches here. Note
697 /// that since code layout is frozen at this point, that if we are trying to
698 /// jump to a block that is the immediate successor of the current block, we can
699 /// just make a fall-through (but we don't currently).
701 void ISel::visitBranchInst(BranchInst &BI) {
702 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
704 if (!BI.isConditional()) { // Unconditional branch?
705 if (BI.getSuccessor(0) != NextBB)
706 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
710 // See if we can fold the setcc into the branch itself...
711 SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
713 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
714 // computed some other way...
715 unsigned condReg = getReg(BI.getCondition());
716 BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
717 if (BI.getSuccessor(1) == NextBB) {
718 if (BI.getSuccessor(0) != NextBB)
719 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
721 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
723 if (BI.getSuccessor(0) != NextBB)
724 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
729 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
730 bool isSigned = EmitComparisonGetSignedness(OpNum, SCI->getOperand(0),
733 // LLVM -> X86 signed X86 unsigned
734 // ----- ---------- ------------
741 static const unsigned OpcodeTab[2][6] = {
742 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE },
743 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE },
746 if (BI.getSuccessor(0) != NextBB) {
747 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
748 if (BI.getSuccessor(1) != NextBB)
749 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
751 // Change to the inverse condition...
752 if (BI.getSuccessor(1) != NextBB) {
754 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
760 /// doCall - This emits an abstract call instruction, setting up the arguments
761 /// and the return value as appropriate. For the actual function call itself,
762 /// it inserts the specified CallMI instruction into the stream.
764 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
765 const std::vector<ValueRecord> &Args) {
767 // Count how many bytes are to be pushed on the stack...
768 unsigned NumBytes = 0;
771 for (unsigned i = 0, e = Args.size(); i != e; ++i)
772 switch (getClassB(Args[i].Ty)) {
773 case cByte: case cShort: case cInt:
774 NumBytes += 4; break;
776 NumBytes += 8; break;
778 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
780 default: assert(0 && "Unknown class!");
783 // Adjust the stack pointer for the new arguments...
784 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes);
786 // Arguments go on the stack in reverse order, as specified by the ABI.
787 unsigned ArgOffset = 0;
788 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
789 unsigned ArgReg = Args[i].Reg;
790 switch (getClassB(Args[i].Ty)) {
793 // Promote arg to 32 bits wide into a temporary register...
794 unsigned R = makeAnotherReg(Type::UIntTy);
795 promote32(R, Args[i]);
796 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
797 X86::ESP, ArgOffset).addReg(R);
801 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
802 X86::ESP, ArgOffset).addReg(ArgReg);
805 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
806 X86::ESP, ArgOffset).addReg(ArgReg);
807 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
808 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
809 ArgOffset += 4; // 8 byte entry, not 4.
813 if (Args[i].Ty == Type::FloatTy) {
814 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
815 X86::ESP, ArgOffset).addReg(ArgReg);
817 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
818 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
819 X86::ESP, ArgOffset).addReg(ArgReg);
820 ArgOffset += 4; // 8 byte entry, not 4.
824 default: assert(0 && "Unknown class!");
829 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(0);
832 BB->push_back(CallMI);
834 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes);
836 // If there is a return value, scavenge the result from the location the call
839 if (Ret.Ty != Type::VoidTy) {
840 unsigned DestClass = getClassB(Ret.Ty);
845 // Integral results are in %eax, or the appropriate portion
847 static const unsigned regRegMove[] = {
848 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
850 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
851 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
854 case cFP: // Floating-point return values live in %ST(0)
855 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
857 case cLong: // Long values are left in EDX:EAX
858 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg).addReg(X86::EAX);
859 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg+1).addReg(X86::EDX);
861 default: assert(0 && "Unknown class!");
867 /// visitCallInst - Push args on stack and do a procedure call instruction.
868 void ISel::visitCallInst(CallInst &CI) {
869 MachineInstr *TheCall;
870 if (Function *F = CI.getCalledFunction()) {
871 // Emit a CALL instruction with PC-relative displacement.
872 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
873 } else { // Emit an indirect call...
874 unsigned Reg = getReg(CI.getCalledValue());
875 TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg);
878 std::vector<ValueRecord> Args;
879 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
880 Args.push_back(ValueRecord(getReg(CI.getOperand(i)),
881 CI.getOperand(i)->getType()));
883 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
884 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
888 /// visitSimpleBinary - Implement simple binary operators for integral types...
889 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
892 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
893 unsigned Class = getClassB(B.getType());
895 static const unsigned OpcodeTab[][4] = {
896 // Arithmetic operators
897 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
898 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
901 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
902 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
903 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
907 if (Class == cLong) {
909 Class = cInt; // Bottom 32 bits are handled just like ints
912 unsigned Opcode = OpcodeTab[OperatorClass][Class];
913 assert(Opcode && "Floating point arguments to logical inst?");
914 unsigned Op0r = getReg(B.getOperand(0));
915 unsigned Op1r = getReg(B.getOperand(1));
916 unsigned DestReg = getReg(B);
917 BuildMI(BB, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
919 if (isLong) { // Handle the upper 32 bits of long values...
920 static const unsigned TopTab[] = {
921 X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
923 BuildMI(BB, TopTab[OperatorClass], 2,
924 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
928 /// doMultiply - Emit appropriate instructions to multiply together the
929 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
930 /// result should be given as DestTy.
932 /// FIXME: doMultiply should use one of the two address IMUL instructions!
934 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
935 unsigned DestReg, const Type *DestTy,
936 unsigned op0Reg, unsigned op1Reg) {
937 unsigned Class = getClass(DestTy);
939 case cFP: // Floating point multiply
940 BMI(BB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
943 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
946 case cInt: // Small integerals, handled below...
950 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
951 static const unsigned MulOpcode[]={ X86::MULr8 , X86::MULr16 , X86::MULr32 };
952 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
953 unsigned Reg = Regs[Class];
955 // Emit a MOV to put the first operand into the appropriately-sized
957 BMI(MBB, MBBI, MovOpcode[Class], 1, Reg).addReg(op0Reg);
959 // Emit the appropriate multiply instruction.
960 BMI(MBB, MBBI, MulOpcode[Class], 1).addReg(op1Reg);
962 // Emit another MOV to put the result into the destination register.
963 BMI(MBB, MBBI, MovOpcode[Class], 1, DestReg).addReg(Reg);
966 /// visitMul - Multiplies are not simple binary operators because they must deal
967 /// with the EAX register explicitly.
969 void ISel::visitMul(BinaryOperator &I) {
970 unsigned Op0Reg = getReg(I.getOperand(0));
971 unsigned Op1Reg = getReg(I.getOperand(1));
972 unsigned DestReg = getReg(I);
974 // Simple scalar multiply?
975 if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
976 MachineBasicBlock::iterator MBBI = BB->end();
977 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
979 // Long value. We have to do things the hard way...
980 // Multiply the two low parts... capturing carry into EDX
981 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
982 BuildMI(BB, X86::MULr32, 1).addReg(Op1Reg); // AL*BL
984 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
985 BuildMI(BB, X86::MOVrr32, 1, DestReg).addReg(X86::EAX); // AL*BL
986 BuildMI(BB, X86::MOVrr32, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32
988 MachineBasicBlock::iterator MBBI = BB->end();
989 unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
990 doMultiply(BB, MBBI, AHBLReg, Type::UIntTy, Op0Reg+1, Op1Reg); // AH*BL
992 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
993 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
994 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
997 unsigned ALBHReg = makeAnotherReg(Type::UIntTy);
998 doMultiply(BB, MBBI, ALBHReg, Type::UIntTy, Op0Reg, Op1Reg+1); // AL*BH
1000 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1001 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1006 /// visitDivRem - Handle division and remainder instructions... these
1007 /// instruction both require the same instructions to be generated, they just
1008 /// select the result from a different register. Note that both of these
1009 /// instructions work differently for signed and unsigned operands.
1011 void ISel::visitDivRem(BinaryOperator &I) {
1012 unsigned Class = getClass(I.getType());
1013 unsigned Op0Reg = getReg(I.getOperand(0));
1014 unsigned Op1Reg = getReg(I.getOperand(1));
1015 unsigned ResultReg = getReg(I);
1018 case cFP: // Floating point divide
1019 if (I.getOpcode() == Instruction::Div)
1020 BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1021 else { // Floating point remainder...
1022 MachineInstr *TheCall =
1023 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1024 std::vector<ValueRecord> Args;
1025 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1026 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1027 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1031 static const char *FnName[] =
1032 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1034 unsigned NameIdx = I.getType()->isUnsigned()*2;
1035 NameIdx += I.getOpcode() == Instruction::Div;
1036 MachineInstr *TheCall =
1037 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
1039 std::vector<ValueRecord> Args;
1040 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1041 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1042 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1045 case cByte: case cShort: case cInt:
1046 break; // Small integerals, handled below...
1047 default: assert(0 && "Unknown class!");
1050 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1051 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1052 static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
1053 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
1054 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
1056 static const unsigned DivOpcode[][4] = {
1057 { X86::DIVr8 , X86::DIVr16 , X86::DIVr32 , 0 }, // Unsigned division
1058 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
1061 bool isSigned = I.getType()->isSigned();
1062 unsigned Reg = Regs[Class];
1063 unsigned ExtReg = ExtRegs[Class];
1065 // Put the first operand into one of the A registers...
1066 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
1069 // Emit a sign extension instruction...
1070 BuildMI(BB, ExtOpcode[Class], 0);
1072 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
1073 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
1076 // Emit the appropriate divide or remainder instruction...
1077 BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
1079 // Figure out which register we want to pick the result out of...
1080 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
1082 // Put the result into the destination register...
1083 BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
1087 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1088 /// for constant immediate shift values, and for constant immediate
1089 /// shift values equal to 1. Even the general case is sort of special,
1090 /// because the shift amount has to be in CL, not just any old register.
1092 void ISel::visitShiftInst(ShiftInst &I) {
1093 unsigned SrcReg = getReg(I.getOperand(0));
1094 unsigned DestReg = getReg(I);
1095 bool isLeftShift = I.getOpcode() == Instruction::Shl;
1096 bool isSigned = I.getType()->isSigned();
1097 unsigned Class = getClass(I.getType());
1099 static const unsigned ConstantOperand[][4] = {
1100 { X86::SHRir8, X86::SHRir16, X86::SHRir32, X86::SHRDir32 }, // SHR
1101 { X86::SARir8, X86::SARir16, X86::SARir32, X86::SHRDir32 }, // SAR
1102 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SHL
1103 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SAL = SHL
1106 static const unsigned NonConstantOperand[][4] = {
1107 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
1108 { X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
1109 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
1110 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
1113 // Longs, as usual, are handled specially...
1114 if (Class == cLong) {
1115 // If we have a constant shift, we can generate much more efficient code
1116 // than otherwise...
1118 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getOperand(1))) {
1119 unsigned Amount = CUI->getValue();
1121 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1123 BuildMI(BB, Opc[3], 3,
1124 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1125 BuildMI(BB, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1127 BuildMI(BB, Opc[3], 3,
1128 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1129 BuildMI(BB, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1131 } else { // Shifting more than 32 bits
1134 BuildMI(BB, X86::SHLir32, 2,DestReg+1).addReg(SrcReg).addZImm(Amount);
1135 BuildMI(BB, X86::MOVir32, 1,DestReg ).addZImm(0);
1137 unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32;
1138 BuildMI(BB, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1139 BuildMI(BB, X86::MOVir32, 1, DestReg+1).addZImm(0);
1143 visitInstruction(I); // FIXME: Implement long shift by non-constant
1148 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getOperand(1))) {
1149 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
1150 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
1152 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1153 BuildMI(BB, Opc[Class], 2, DestReg).addReg(SrcReg).addZImm(CUI->getValue());
1154 } else { // The shift amount is non-constant.
1155 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
1157 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
1158 BuildMI(BB, Opc[Class], 1, DestReg).addReg(SrcReg);
1163 /// doFPLoad - This method is used to load an FP value from memory using the
1164 /// current endianness. NOTE: This method returns a partially constructed load
1165 /// instruction which needs to have the memory source filled in still.
1167 MachineInstr *ISel::doFPLoad(MachineBasicBlock *MBB,
1168 MachineBasicBlock::iterator &MBBI,
1169 const Type *Ty, unsigned DestReg) {
1170 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1171 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
1173 if (TM.getTargetData().isLittleEndian()) // fast path...
1174 return BMI(MBB, MBBI, LoadOpcode, 4, DestReg);
1176 // If we are big-endian, start by creating an LEA instruction to represent the
1177 // address of the memory location to load from...
1179 unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy);
1180 MachineInstr *Result = BMI(MBB, MBBI, X86::LEAr32, 5, SrcAddrReg);
1182 // Allocate a temporary stack slot to transform the value into...
1183 int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData());
1185 // Perform the bswaps 32 bits at a time...
1186 unsigned TmpReg1 = makeAnotherReg(Type::UIntTy);
1187 unsigned TmpReg2 = makeAnotherReg(Type::UIntTy);
1188 addDirectMem(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg);
1189 BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1190 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1191 addFrameReference(BMI(MBB, MBBI, X86::MOVrm32, 5),
1192 FrameIdx, Offset).addReg(TmpReg2);
1194 if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value...
1195 TmpReg1 = makeAnotherReg(Type::UIntTy);
1196 TmpReg2 = makeAnotherReg(Type::UIntTy);
1198 addRegOffset(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4);
1199 BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1200 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1201 addFrameReference(BMI(MBB, MBBI, X86::MOVrm32,5), FrameIdx).addReg(TmpReg2);
1204 // Now we can reload the final byteswapped result into the final destination.
1205 addFrameReference(BMI(MBB, MBBI, LoadOpcode, 4, DestReg), FrameIdx);
1209 /// EmitByteSwap - Byteswap SrcReg into DestReg.
1211 void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) {
1212 // Emit the byte swap instruction...
1215 // No byteswap necessary for 8 bit value...
1216 BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(SrcReg);
1219 // Use the 32 bit bswap instruction to do a 32 bit swap...
1220 BuildMI(BB, X86::BSWAPr32, 1, DestReg).addReg(SrcReg);
1224 // For 16 bit we have to use an xchg instruction, because there is no
1225 // 16-bit bswap. XCHG is necessarily not in SSA form, so we force things
1226 // into AX to do the xchg.
1228 BuildMI(BB, X86::MOVrr16, 1, X86::AX).addReg(SrcReg);
1229 BuildMI(BB, X86::XCHGrr8, 2).addReg(X86::AL, MOTy::UseAndDef)
1230 .addReg(X86::AH, MOTy::UseAndDef);
1231 BuildMI(BB, X86::MOVrr16, 1, DestReg).addReg(X86::AX);
1233 default: assert(0 && "Cannot byteswap this class!");
1238 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
1239 /// instruction. The load and store instructions are the only place where we
1240 /// need to worry about the memory layout of the target machine.
1242 void ISel::visitLoadInst(LoadInst &I) {
1243 bool isLittleEndian = TM.getTargetData().isLittleEndian();
1244 bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
1245 unsigned SrcAddrReg = getReg(I.getOperand(0));
1246 unsigned DestReg = getReg(I);
1248 unsigned Class = getClass(I.getType());
1251 MachineBasicBlock::iterator MBBI = BB->end();
1252 addDirectMem(doFPLoad(BB, MBBI, I.getType(), DestReg), SrcAddrReg);
1255 case cLong: case cInt: case cShort: case cByte:
1256 break; // Integers of various sizes handled below
1257 default: assert(0 && "Unknown memory class!");
1260 // We need to adjust the input pointer if we are emulating a big-endian
1261 // long-pointer target. On these systems, the pointer that we are interested
1262 // in is in the upper part of the eight byte memory image of the pointer. It
1263 // also happens to be byte-swapped, but this will be handled later.
1265 if (!isLittleEndian && hasLongPointers && isa<PointerType>(I.getType())) {
1266 unsigned R = makeAnotherReg(Type::UIntTy);
1267 BuildMI(BB, X86::ADDri32, 2, R).addReg(SrcAddrReg).addZImm(4);
1271 unsigned IReg = DestReg;
1272 if (!isLittleEndian) // If big endian we need an intermediate stage
1273 DestReg = makeAnotherReg(Class != cLong ? I.getType() : Type::UIntTy);
1275 static const unsigned Opcode[] = {
1276 X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, 0, X86::MOVmr32
1278 addDirectMem(BuildMI(BB, Opcode[Class], 4, DestReg), SrcAddrReg);
1280 // Handle long values now...
1281 if (Class == cLong) {
1282 if (isLittleEndian) {
1283 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
1285 EmitByteSwap(IReg+1, DestReg, cInt);
1286 unsigned TempReg = makeAnotherReg(Type::IntTy);
1287 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TempReg), SrcAddrReg, 4);
1288 EmitByteSwap(IReg, TempReg, cInt);
1293 if (!isLittleEndian)
1294 EmitByteSwap(IReg, DestReg, Class);
1298 /// doFPStore - This method is used to store an FP value to memory using the
1299 /// current endianness.
1301 void ISel::doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg) {
1302 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1303 unsigned StoreOpcode = Ty == Type::FloatTy ? X86::FSTr32 : X86::FSTr64;
1305 if (TM.getTargetData().isLittleEndian()) { // fast path...
1306 addDirectMem(BuildMI(BB, StoreOpcode,5), DestAddrReg).addReg(SrcReg);
1310 // Allocate a temporary stack slot to transform the value into...
1311 int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData());
1312 unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy);
1313 addFrameReference(BuildMI(BB, X86::LEAr32, 5, SrcAddrReg), FrameIdx);
1315 // Store the value into a temporary stack slot...
1316 addDirectMem(BuildMI(BB, StoreOpcode, 5), SrcAddrReg).addReg(SrcReg);
1318 // Perform the bswaps 32 bits at a time...
1319 unsigned TmpReg1 = makeAnotherReg(Type::UIntTy);
1320 unsigned TmpReg2 = makeAnotherReg(Type::UIntTy);
1321 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg);
1322 BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1323 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1324 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1325 DestAddrReg, Offset).addReg(TmpReg2);
1327 if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value...
1328 TmpReg1 = makeAnotherReg(Type::UIntTy);
1329 TmpReg2 = makeAnotherReg(Type::UIntTy);
1331 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4);
1332 BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1333 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1334 addDirectMem(BuildMI(BB, X86::MOVrm32, 5), DestAddrReg).addReg(TmpReg2);
1339 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
1342 void ISel::visitStoreInst(StoreInst &I) {
1343 bool isLittleEndian = TM.getTargetData().isLittleEndian();
1344 bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
1345 unsigned ValReg = getReg(I.getOperand(0));
1346 unsigned AddressReg = getReg(I.getOperand(1));
1348 unsigned Class = getClass(I.getOperand(0)->getType());
1351 if (isLittleEndian) {
1352 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
1353 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4),
1354 AddressReg, 4).addReg(ValReg+1);
1356 unsigned T1 = makeAnotherReg(Type::IntTy);
1357 unsigned T2 = makeAnotherReg(Type::IntTy);
1358 EmitByteSwap(T1, ValReg , cInt);
1359 EmitByteSwap(T2, ValReg+1, cInt);
1360 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(T2);
1361 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg, 4).addReg(T1);
1365 doFPStore(I.getOperand(0)->getType(), AddressReg, ValReg);
1367 case cInt: case cShort: case cByte:
1368 break; // Integers of various sizes handled below
1369 default: assert(0 && "Unknown memory class!");
1372 if (!isLittleEndian && hasLongPointers &&
1373 isa<PointerType>(I.getOperand(0)->getType())) {
1374 unsigned R = makeAnotherReg(Type::UIntTy);
1375 BuildMI(BB, X86::ADDri32, 2, R).addReg(AddressReg).addZImm(4);
1379 if (!isLittleEndian && Class != cByte) {
1380 unsigned R = makeAnotherReg(I.getOperand(0)->getType());
1381 EmitByteSwap(R, ValReg, Class);
1385 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1386 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
1390 /// visitCastInst - Here we have various kinds of copying with or without
1391 /// sign extension going on.
1392 void ISel::visitCastInst(CastInst &CI) {
1393 unsigned DestReg = getReg(CI);
1394 MachineBasicBlock::iterator MI = BB->end();
1395 emitCastOperation(BB, MI, CI.getOperand(0), CI.getType(), DestReg);
1398 /// emitCastOperation - Common code shared between visitCastInst and
1399 /// constant expression cast support.
1400 void ISel::emitCastOperation(MachineBasicBlock *BB,
1401 MachineBasicBlock::iterator &IP,
1402 Value *Src, const Type *DestTy,
1404 unsigned SrcReg = getReg(Src, BB, IP);
1405 const Type *SrcTy = Src->getType();
1406 unsigned SrcClass = getClassB(SrcTy);
1407 unsigned DestClass = getClassB(DestTy);
1409 // Implement casts to bool by using compare on the operand followed by set if
1410 // not zero on the result.
1411 if (DestTy == Type::BoolTy) {
1412 if (SrcClass == cFP || SrcClass == cLong)
1413 abort(); // FIXME: implement cast (long & FP) to bool
1415 BMI(BB, IP, X86::CMPri8, 2).addReg(SrcReg).addZImm(0);
1416 BMI(BB, IP, X86::SETNEr, 1, DestReg);
1420 static const unsigned RegRegMove[] = {
1421 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV, X86::MOVrr32
1424 // Implement casts between values of the same type class (as determined by
1425 // getClass) by using a register-to-register move.
1426 if (SrcClass == DestClass) {
1427 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
1428 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
1429 } else if (SrcClass == cFP) {
1430 if (SrcTy == Type::FloatTy) { // double -> float
1431 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1432 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
1433 } else { // float -> double
1434 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1435 "Unknown cFP member!");
1436 // Truncate from double to float by storing to memory as short, then
1438 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
1439 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
1440 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1441 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
1443 } else if (SrcClass == cLong) {
1444 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1445 BMI(BB, IP, X86::MOVrr32, 1, DestReg+1).addReg(SrcReg+1);
1452 // Handle cast of SMALLER int to LARGER int using a move with sign extension
1453 // or zero extension, depending on whether the source type was signed.
1454 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
1455 SrcClass < DestClass) {
1456 bool isLong = DestClass == cLong;
1457 if (isLong) DestClass = cInt;
1459 static const unsigned Opc[][4] = {
1460 { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, X86::MOVrr32 }, // s
1461 { X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16, X86::MOVrr32 } // u
1464 bool isUnsigned = SrcTy->isUnsigned();
1465 BMI(BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
1466 DestReg).addReg(SrcReg);
1468 if (isLong) { // Handle upper 32 bits as appropriate...
1469 if (isUnsigned) // Zero out top bits...
1470 BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1471 else // Sign extend bottom half...
1472 BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31);
1477 // Special case long -> int ...
1478 if (SrcClass == cLong && DestClass == cInt) {
1479 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1483 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
1484 // move out of AX or AL.
1485 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
1486 && SrcClass > DestClass) {
1487 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
1488 BMI(BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
1489 BMI(BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
1493 // Handle casts from integer to floating point now...
1494 if (DestClass == cFP) {
1495 // unsigned int -> load as 64 bit int.
1496 // unsigned long long -> more complex
1497 if (SrcTy->isUnsigned() && SrcTy != Type::UByteTy)
1498 abort(); // don't handle unsigned src yet!
1500 // We don't have the facilities for directly loading byte sized data from
1501 // memory. Promote it to 16 bits.
1502 if (SrcClass == cByte) {
1503 unsigned TmpReg = makeAnotherReg(Type::ShortTy);
1504 BMI(BB, IP, SrcTy->isSigned() ? X86::MOVSXr16r8 : X86::MOVZXr16r8,
1505 1, TmpReg).addReg(SrcReg);
1506 SrcTy = Type::ShortTy; // Pretend the short is our input now!
1511 // Spill the integer to memory and reload it from there...
1513 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
1515 if (SrcClass == cLong) {
1516 if (SrcTy == Type::ULongTy) abort(); // FIXME: Handle ulong -> FP
1517 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5), FrameIdx).addReg(SrcReg);
1518 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5),
1519 FrameIdx, 4).addReg(SrcReg+1);
1521 static const unsigned Op1[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1522 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
1525 static const unsigned Op2[] =
1526 { 0, X86::FILDr16, X86::FILDr32, 0, X86::FILDr64 };
1527 addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
1531 // Handle casts from floating point to integer now...
1532 if (SrcClass == cFP) {
1533 // Change the floating point control register to use "round towards zero"
1534 // mode when truncating to an integer value.
1536 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1537 addFrameReference(BMI(BB, IP, X86::FNSTCWm16, 4), CWFrameIdx);
1539 // Load the old value of the high byte of the control word...
1540 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
1541 addFrameReference(BMI(BB, IP, X86::MOVmr8, 4, HighPartOfCW), CWFrameIdx, 1);
1543 // Set the high part to be round to zero...
1544 addFrameReference(BMI(BB, IP, X86::MOVim8, 5), CWFrameIdx, 1).addZImm(12);
1546 // Reload the modified control word now...
1547 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1549 // Restore the memory image of control word to original value
1550 addFrameReference(BMI(BB, IP, X86::MOVrm8, 5),
1551 CWFrameIdx, 1).addReg(HighPartOfCW);
1553 // We don't have the facilities for directly storing byte sized data to
1554 // memory. Promote it to 16 bits. We also must promote unsigned values to
1555 // larger classes because we only have signed FP stores.
1556 unsigned StoreClass = DestClass;
1557 const Type *StoreTy = DestTy;
1558 if (StoreClass == cByte || DestTy->isUnsigned())
1559 switch (StoreClass) {
1560 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
1561 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
1562 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
1563 case cLong: abort(); // FIXME: unsigned long long -> more complex
1564 default: assert(0 && "Unknown store class!");
1567 // Spill the integer to memory and reload it from there...
1569 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
1571 static const unsigned Op1[] =
1572 { 0, X86::FISTr16, X86::FISTr32, 0, X86::FISTPr64 };
1573 addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg);
1575 if (DestClass == cLong) {
1576 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg), FrameIdx);
1577 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg+1), FrameIdx, 4);
1579 static const unsigned Op2[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
1580 addFrameReference(BMI(BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
1583 // Reload the original control word now...
1584 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1588 // Anything we haven't handled already, we can't (yet) handle at all.
1592 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1593 // returns zero when the input is not exactly a power of two.
1594 static unsigned ExactLog2(unsigned Val) {
1595 if (Val == 0) return 0;
1598 if (Val & 1) return 0;
1605 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
1606 unsigned outputReg = getReg(I);
1607 MachineBasicBlock::iterator MI = BB->end();
1608 emitGEPOperation(BB, MI, I.getOperand(0),
1609 I.op_begin()+1, I.op_end(), outputReg);
1612 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
1613 MachineBasicBlock::iterator &IP,
1614 Value *Src, User::op_iterator IdxBegin,
1615 User::op_iterator IdxEnd, unsigned TargetReg) {
1616 const TargetData &TD = TM.getTargetData();
1617 const Type *Ty = Src->getType();
1618 unsigned BaseReg = getReg(Src, MBB, IP);
1620 // GEPs have zero or more indices; we must perform a struct access
1621 // or array access for each one.
1622 for (GetElementPtrInst::op_iterator oi = IdxBegin,
1623 oe = IdxEnd; oi != oe; ++oi) {
1625 unsigned NextReg = BaseReg;
1626 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1627 // It's a struct access. idx is the index into the structure,
1628 // which names the field. This index must have ubyte type.
1629 const ConstantUInt *CUI = cast<ConstantUInt>(idx);
1630 assert(CUI->getType() == Type::UByteTy
1631 && "Funny-looking structure index in GEP");
1632 // Use the TargetData structure to pick out what the layout of
1633 // the structure is in memory. Since the structure index must
1634 // be constant, we can get its value and use it to find the
1635 // right byte offset from the StructLayout class's list of
1636 // structure member offsets.
1637 unsigned idxValue = CUI->getValue();
1638 unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue];
1640 NextReg = makeAnotherReg(Type::UIntTy);
1641 // Emit an ADD to add FieldOff to the basePtr.
1642 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff);
1644 // The next type is the member of the structure selected by the
1646 Ty = StTy->getElementTypes()[idxValue];
1647 } else if (const SequentialType *SqTy = cast<SequentialType>(Ty)) {
1648 // It's an array or pointer access: [ArraySize x ElementType].
1650 // idx is the index into the array. Unlike with structure
1651 // indices, we may not know its actual value at code-generation
1653 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
1655 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
1656 // must find the size of the pointed-to type (Not coincidentally, the next
1657 // type is the type of the elements in the array).
1658 Ty = SqTy->getElementType();
1659 unsigned elementSize = TD.getTypeSize(Ty);
1661 // If idxReg is a constant, we don't need to perform the multiply!
1662 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
1663 if (!CSI->isNullValue()) {
1664 unsigned Offset = elementSize*CSI->getValue();
1665 NextReg = makeAnotherReg(Type::UIntTy);
1666 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(Offset);
1668 } else if (elementSize == 1) {
1669 // If the element size is 1, we don't have to multiply, just add
1670 unsigned idxReg = getReg(idx, MBB, IP);
1671 NextReg = makeAnotherReg(Type::UIntTy);
1672 BMI(MBB, IP, X86::ADDrr32, 2, NextReg).addReg(BaseReg).addReg(idxReg);
1674 unsigned idxReg = getReg(idx, MBB, IP);
1675 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
1676 if (unsigned Shift = ExactLog2(elementSize)) {
1677 // If the element size is exactly a power of 2, use a shift to get it.
1678 BMI(MBB, IP, X86::SHLir32, 2,
1679 OffsetReg).addReg(idxReg).addZImm(Shift-1);
1681 // Most general case, emit a multiply...
1682 unsigned elementSizeReg = makeAnotherReg(Type::LongTy);
1683 BMI(MBB, IP, X86::MOVir32, 1, elementSizeReg).addZImm(elementSize);
1685 // Emit a MUL to multiply the register holding the index by
1686 // elementSize, putting the result in OffsetReg.
1687 doMultiply(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSizeReg);
1689 // Emit an ADD to add OffsetReg to the basePtr.
1690 NextReg = makeAnotherReg(Type::UIntTy);
1691 BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg);
1694 // Now that we are here, further indices refer to subtypes of this
1695 // one, so we don't need to worry about BaseReg itself, anymore.
1698 // After we have processed all the indices, the result is left in
1699 // BaseReg. Move it to the register where we were expected to
1700 // put the answer. A 32-bit move should do it, because we are in
1702 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
1706 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
1707 /// frame manager, otherwise do it the hard way.
1709 void ISel::visitAllocaInst(AllocaInst &I) {
1710 // Find the data size of the alloca inst's getAllocatedType.
1711 const Type *Ty = I.getAllocatedType();
1712 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
1714 // If this is a fixed size alloca in the entry block for the function,
1715 // statically stack allocate the space.
1717 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
1718 if (I.getParent() == I.getParent()->getParent()->begin()) {
1719 TySize *= CUI->getValue(); // Get total allocated size...
1720 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
1722 // Create a new stack object using the frame manager...
1723 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
1724 addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx);
1729 // Create a register to hold the temporary result of multiplying the type size
1730 // constant by the variable amount.
1731 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
1732 unsigned SrcReg1 = getReg(I.getArraySize());
1733 unsigned SizeReg = makeAnotherReg(Type::UIntTy);
1734 BuildMI(BB, X86::MOVir32, 1, SizeReg).addZImm(TySize);
1736 // TotalSizeReg = mul <numelements>, <TypeSize>
1737 MachineBasicBlock::iterator MBBI = BB->end();
1738 doMultiply(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, SizeReg);
1740 // AddedSize = add <TotalSizeReg>, 15
1741 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
1742 BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15);
1744 // AlignedSize = and <AddedSize>, ~15
1745 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
1746 BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15);
1748 // Subtract size from stack pointer, thereby allocating some space.
1749 BuildMI(BB, X86::SUBrr32, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
1751 // Put a pointer to the space into the result register, by copying
1752 // the stack pointer.
1753 BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP);
1755 // Inform the Frame Information that we have just allocated a variable sized
1757 F->getFrameInfo()->CreateVariableSizedObject();
1760 /// visitMallocInst - Malloc instructions are code generated into direct calls
1761 /// to the library malloc.
1763 void ISel::visitMallocInst(MallocInst &I) {
1764 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
1767 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
1768 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
1770 Arg = makeAnotherReg(Type::UIntTy);
1771 unsigned Op0Reg = getReg(ConstantUInt::get(Type::UIntTy, AllocSize));
1772 unsigned Op1Reg = getReg(I.getOperand(0));
1773 MachineBasicBlock::iterator MBBI = BB->end();
1774 doMultiply(BB, MBBI, Arg, Type::UIntTy, Op0Reg, Op1Reg);
1779 std::vector<ValueRecord> Args;
1780 Args.push_back(ValueRecord(Arg, Type::UIntTy));
1781 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
1782 1).addExternalSymbol("malloc", true);
1783 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
1787 /// visitFreeInst - Free instructions are code gen'd to call the free libc
1790 void ISel::visitFreeInst(FreeInst &I) {
1791 std::vector<ValueRecord> Args;
1792 Args.push_back(ValueRecord(getReg(I.getOperand(0)),
1793 I.getOperand(0)->getType()));
1794 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
1795 1).addExternalSymbol("free", true);
1796 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
1800 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
1801 /// into a machine code representation is a very simple peep-hole fashion. The
1802 /// generated code sucks but the implementation is nice and simple.
1804 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {
1805 return new ISel(TM);