1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 platform
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "llvm/Function.h"
10 #include "llvm/iTerminators.h"
11 #include "llvm/iOther.h"
12 #include "llvm/Type.h"
13 #include "llvm/Constants.h"
14 #include "llvm/Pass.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/Support/InstVisitor.h"
21 struct ISel : public FunctionPass, InstVisitor<ISel> {
23 MachineFunction *F; // The function we are compiling into
24 MachineBasicBlock *BB; // The current MBB we are compiling
27 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
29 ISel(TargetMachine &tm)
30 : TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
32 /// runOnFunction - Top level implementation of instruction selection for
33 /// the entire function.
35 bool runOnFunction(Function &Fn) {
36 F = &MachineFunction::construct(&Fn, TM);
40 return false; // We never modify the LLVM itself.
43 /// visitBasicBlock - This method is called when we are visiting a new basic
44 /// block. This simply creates a new MachineBasicBlock to emit code into
45 /// and adds it to the current MachineFunction. Subsequent visit* for
46 /// instructions will be invoked for all instructions in the basic block.
48 void visitBasicBlock(BasicBlock &LLVM_BB) {
49 BB = new MachineBasicBlock(&LLVM_BB);
50 // FIXME: Use the auto-insert form when it's available
51 F->getBasicBlockList().push_back(BB);
54 // Visitation methods for various instructions. These methods simply emit
55 // fixed X86 code for each instruction.
57 void visitReturnInst(ReturnInst &RI);
58 void visitAdd(BinaryOperator &B);
59 void visitShiftInst(ShiftInst &I);
61 void visitInstruction(Instruction &I) {
62 std::cerr << "Cannot instruction select: " << I;
67 /// copyConstantToRegister - Output the instructions required to put the
68 /// specified constant into the specified register.
70 void copyConstantToRegister(Constant *C, unsigned Reg);
72 /// getReg - This method turns an LLVM value into a register number. This
73 /// is guaranteed to produce the same register number for a particular value
74 /// every time it is queried.
76 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
77 unsigned getReg(Value *V) {
78 unsigned &Reg = RegMap[V];
82 // If this operand is a constant, emit the code to copy the constant into
83 // the register here...
85 if (Constant *C = dyn_cast<Constant>(V))
86 copyConstantToRegister(C, Reg);
93 /// getClass - Turn a primitive type into a "class" number which is based on the
94 /// size of the type, and whether or not it is floating point.
96 static inline unsigned getClass(const Type *Ty) {
97 switch (Ty->getPrimitiveID()) {
99 case Type::UByteTyID: return 0; // Byte operands are class #0
100 case Type::ShortTyID:
101 case Type::UShortTyID: return 1; // Short operands are class #1
104 case Type::PointerTyID: return 2; // Int's and pointers are class #2
107 case Type::ULongTyID: return 3; // Longs are class #3
108 case Type::FloatTyID: return 4; // Float is class #4
109 case Type::DoubleTyID: return 5; // Doubles are class #5
111 assert(0 && "Invalid type to getClass!");
112 return 0; // not reached
116 /// copyConstantToRegister - Output the instructions required to put the
117 /// specified constant into the specified register.
119 void ISel::copyConstantToRegister(Constant *C, unsigned R) {
120 assert (!isa<ConstantExpr>(C) && "Constant expressions not yet handled!\n");
122 if (C->getType()->isIntegral()) {
123 unsigned Class = getClass(C->getType());
124 assert(Class != 3 && "Type not handled yet!");
126 static const unsigned IntegralOpcodeTab[] = {
127 X86::MOVir8, X86::MOVir16, X86::MOVir32
130 if (C->getType()->isSigned()) {
131 ConstantSInt *CSI = cast<ConstantSInt>(C);
132 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
134 ConstantUInt *CUI = cast<ConstantUInt>(C);
135 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
138 assert(0 && "Type not handled yet!");
143 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
144 /// we have the following possibilities:
146 /// ret void: No return value, simply emit a 'ret' instruction
147 /// ret sbyte, ubyte : Extend value into EAX and return
148 /// ret short, ushort: Extend value into EAX and return
149 /// ret int, uint : Move value into EAX and return
150 /// ret pointer : Move value into EAX and return
151 /// ret long, ulong : Move value into EAX/EDX (?) and return
152 /// ret float/double : ? Top of FP stack? XMM0?
154 void ISel::visitReturnInst(ReturnInst &I) {
155 if (I.getNumOperands() != 0) { // Not 'ret void'?
156 // Move result into a hard register... then emit a ret
157 visitInstruction(I); // abort
160 // Emit a simple 'ret' instruction... appending it to the end of the basic
162 BuildMI(BB, X86::RET, 0);
165 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
166 /// for constant immediate shift values, and for constant immediate
167 /// shift values equal to 1. Even the general case is sort of special,
168 /// because the shift amount has to be in CL, not just any old register.
171 ISel::visitShiftInst (ShiftInst & I)
173 unsigned Op0r = getReg (I.getOperand (0));
174 unsigned DestReg = getReg (I);
175 bool isLeftShift = I.getOpcode() == Instruction::Shl;
176 bool isOperandSigned = I.getType()->isUnsigned();
177 unsigned OperandClass = getClass(I.getType());
179 if (OperandClass > 2)
180 visitInstruction(I); // Can't handle longs yet!
182 if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
184 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
185 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
186 unsigned char shAmt = CUI->getValue();
188 static const unsigned ConstantOperand[][4] = {
189 { X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
190 { X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
191 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
192 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
195 const unsigned *OpTab = // Figure out the operand table to use
196 ConstantOperand[isLeftShift*2+isOperandSigned];
198 // Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
199 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
203 // The shift amount is non-constant.
205 // In fact, you can only shift with a variable shift amount if
206 // that amount is already in the CL register, so we have to put it
210 // Emit: move cl, shiftAmount (put the shift amount in CL.)
211 BuildMI (BB, X86::MOVrr8, 2, X86::CL).addReg(getReg(I.getOperand(1)));
213 // This is a shift right (SHR).
214 static const unsigned NonConstantOperand[][4] = {
215 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
216 { X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
217 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
218 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
221 const unsigned *OpTab = // Figure out the operand table to use
222 NonConstantOperand[isLeftShift*2+isOperandSigned];
224 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL);
229 /// 'add' instruction - Simply turn this into an x86 reg,reg add instruction.
230 void ISel::visitAdd(BinaryOperator &B) {
231 unsigned Op0r = getReg(B.getOperand(0)), Op1r = getReg(B.getOperand(1));
232 unsigned DestReg = getReg(B);
233 unsigned Class = getClass(B.getType());
235 static const unsigned Opcodes[] = { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32 };
237 if (Class >= sizeof(Opcodes)/sizeof(Opcodes[0]))
238 visitInstruction(B); // Not handled class yet...
240 BuildMI(BB, Opcodes[Class], 2, DestReg).addReg(Op0r).addReg(Op1r);
242 // For Longs: Here we have a pair of operands each occupying a pair of
243 // registers. We need to do an ADDrr32 of the least-significant pair
244 // immediately followed by an ADCrr32 (Add with Carry) of the most-significant
245 // pair. I don't know how we are representing these multi-register arguments.
250 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
251 /// into a machine code representation is a very simple peep-hole fashion. The
252 /// generated code sucks but the implementation is nice and simple.
254 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {