1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 platform
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/iTerminators.h"
12 #include "llvm/iOperators.h"
13 #include "llvm/iOther.h"
14 #include "llvm/iPHINode.h"
15 #include "llvm/iMemory.h"
16 #include "llvm/Type.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Pass.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/Support/InstVisitor.h"
23 struct ISel : public FunctionPass, InstVisitor<ISel> {
25 MachineFunction *F; // The function we are compiling into
26 MachineBasicBlock *BB; // The current MBB we are compiling
29 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
31 ISel(TargetMachine &tm)
32 : TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
34 /// runOnFunction - Top level implementation of instruction selection for
35 /// the entire function.
37 bool runOnFunction(Function &Fn) {
38 F = &MachineFunction::construct(&Fn, TM);
42 return false; // We never modify the LLVM itself.
45 /// visitBasicBlock - This method is called when we are visiting a new basic
46 /// block. This simply creates a new MachineBasicBlock to emit code into
47 /// and adds it to the current MachineFunction. Subsequent visit* for
48 /// instructions will be invoked for all instructions in the basic block.
50 void visitBasicBlock(BasicBlock &LLVM_BB) {
51 BB = new MachineBasicBlock(&LLVM_BB);
52 // FIXME: Use the auto-insert form when it's available
53 F->getBasicBlockList().push_back(BB);
56 // Visitation methods for various instructions. These methods simply emit
57 // fixed X86 code for each instruction.
59 void visitReturnInst(ReturnInst &RI);
60 void visitBranchInst(BranchInst &BI);
62 // Arithmetic operators
63 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
64 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
65 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
66 void visitMul(BinaryOperator &B);
68 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
69 void visitRem(BinaryOperator &B) { visitDivRem(B); }
70 void visitDivRem(BinaryOperator &B);
73 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
74 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
75 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
77 // Binary comparison operators
78 void visitSetCondInst(SetCondInst &I);
80 // Memory Instructions
81 void visitLoadInst(LoadInst &I);
82 void visitStoreInst(StoreInst &I);
85 void visitShiftInst(ShiftInst &I);
86 void visitPHINode(PHINode &I);
88 void visitInstruction(Instruction &I) {
89 std::cerr << "Cannot instruction select: " << I;
94 /// copyConstantToRegister - Output the instructions required to put the
95 /// specified constant into the specified register.
97 void copyConstantToRegister(Constant *C, unsigned Reg);
99 /// getReg - This method turns an LLVM value into a register number. This
100 /// is guaranteed to produce the same register number for a particular value
101 /// every time it is queried.
103 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
104 unsigned getReg(Value *V) {
105 unsigned &Reg = RegMap[V];
109 // If this operand is a constant, emit the code to copy the constant into
110 // the register here...
112 if (Constant *C = dyn_cast<Constant>(V))
113 copyConstantToRegister(C, Reg);
120 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
124 cByte, cShort, cInt, cLong, cFloat, cDouble
127 /// getClass - Turn a primitive type into a "class" number which is based on the
128 /// size of the type, and whether or not it is floating point.
130 static inline TypeClass getClass(const Type *Ty) {
131 switch (Ty->getPrimitiveID()) {
132 case Type::SByteTyID:
133 case Type::UByteTyID: return cByte; // Byte operands are class #0
134 case Type::ShortTyID:
135 case Type::UShortTyID: return cShort; // Short operands are class #1
138 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
141 case Type::ULongTyID: return cLong; // Longs are class #3
142 case Type::FloatTyID: return cFloat; // Float is class #4
143 case Type::DoubleTyID: return cDouble; // Doubles are class #5
145 assert(0 && "Invalid type to getClass!");
146 return cByte; // not reached
150 /// copyConstantToRegister - Output the instructions required to put the
151 /// specified constant into the specified register.
153 void ISel::copyConstantToRegister(Constant *C, unsigned R) {
154 assert (!isa<ConstantExpr>(C) && "Constant expressions not yet handled!\n");
156 if (C->getType()->isIntegral()) {
157 unsigned Class = getClass(C->getType());
158 assert(Class != 3 && "Type not handled yet!");
160 static const unsigned IntegralOpcodeTab[] = {
161 X86::MOVir8, X86::MOVir16, X86::MOVir32
164 if (C->getType()->isSigned()) {
165 ConstantSInt *CSI = cast<ConstantSInt>(C);
166 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
168 ConstantUInt *CUI = cast<ConstantUInt>(C);
169 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
172 assert(0 && "Type not handled yet!");
176 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
177 /// register, then move it to wherever the result should be.
178 /// We handle FP setcc instructions by pushing them, doing a
179 /// compare-and-pop-twice, and then copying the concodes to the main
180 /// processor's concodes (I didn't make this up, it's in the Intel manual)
183 ISel::visitSetCondInst (SetCondInst & I)
185 // The arguments are already supposed to be of the same type.
186 Value *var1 = I.getOperand (0);
187 Value *var2 = I.getOperand (1);
188 unsigned reg1 = getReg (var1);
189 unsigned reg2 = getReg (var2);
190 unsigned resultReg = getReg (I);
191 unsigned comparisonWidth = var1->getType ()->getPrimitiveSize ();
192 unsigned unsignedComparison = var1->getType ()->isUnsigned ();
193 unsigned resultWidth = I.getType ()->getPrimitiveSize ();
194 bool fpComparison = var1->getType ()->isFloatingPoint ();
197 // Push the variables on the stack with fldl opcodes.
198 // FIXME: assuming var1, var2 are in memory, if not, spill to
200 switch (comparisonWidth)
203 BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1);
206 BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1);
209 visitInstruction (I);
212 switch (comparisonWidth)
215 BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2);
218 BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2);
221 visitInstruction (I);
224 // (Non-trapping) compare and pop twice.
225 BuildMI (BB, X86::FUCOMPP, 0);
226 // Move fp status word (concodes) to ax.
227 BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
228 // Load real concodes from ax.
229 BuildMI (BB, X86::SAHF, 1, X86::EFLAGS).addReg(X86::AH);
232 { // integer comparison
233 // Emit: cmp <var1>, <var2> (do the comparison). We can
234 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
236 switch (comparisonWidth)
239 BuildMI (BB, X86::CMPrr8, 2,
240 X86::EFLAGS).addReg (reg1).addReg (reg2);
243 BuildMI (BB, X86::CMPrr16, 2,
244 X86::EFLAGS).addReg (reg1).addReg (reg2);
247 BuildMI (BB, X86::CMPrr32, 2,
248 X86::EFLAGS).addReg (reg1).addReg (reg2);
252 visitInstruction (I);
256 // Emit setOp instruction (extract concode; clobbers ax),
257 // using the following mapping:
258 // LLVM -> X86 signed X86 unsigned
260 // seteq -> sete sete
261 // setne -> setne setne
262 // setlt -> setl setb
263 // setgt -> setg seta
264 // setle -> setle setbe
265 // setge -> setge setae
266 switch (I.getOpcode ())
268 case Instruction::SetEQ:
269 BuildMI (BB, X86::SETE, 0, X86::AL);
271 case Instruction::SetGE:
272 if (unsignedComparison)
273 BuildMI (BB, X86::SETAE, 0, X86::AL);
275 BuildMI (BB, X86::SETGE, 0, X86::AL);
277 case Instruction::SetGT:
278 if (unsignedComparison)
279 BuildMI (BB, X86::SETA, 0, X86::AL);
281 BuildMI (BB, X86::SETG, 0, X86::AL);
283 case Instruction::SetLE:
284 if (unsignedComparison)
285 BuildMI (BB, X86::SETBE, 0, X86::AL);
287 BuildMI (BB, X86::SETLE, 0, X86::AL);
289 case Instruction::SetLT:
290 if (unsignedComparison)
291 BuildMI (BB, X86::SETB, 0, X86::AL);
293 BuildMI (BB, X86::SETL, 0, X86::AL);
295 case Instruction::SetNE:
296 BuildMI (BB, X86::SETNE, 0, X86::AL);
299 visitInstruction (I);
302 // Put it in the result using a move.
306 BuildMI (BB, X86::MOVrr8, 1, resultReg).addReg (X86::AL);
309 BuildMI (BB, X86::MOVZXr16r8, 1, resultReg).addReg (X86::AL);
312 BuildMI (BB, X86::MOVZXr32r8, 1, resultReg).addReg (X86::AL);
316 visitInstruction (I);
322 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
323 /// we have the following possibilities:
325 /// ret void: No return value, simply emit a 'ret' instruction
326 /// ret sbyte, ubyte : Extend value into EAX and return
327 /// ret short, ushort: Extend value into EAX and return
328 /// ret int, uint : Move value into EAX and return
329 /// ret pointer : Move value into EAX and return
330 /// ret long, ulong : Move value into EAX/EDX (?) and return
331 /// ret float/double : ? Top of FP stack? XMM0?
333 void ISel::visitReturnInst (ReturnInst &I) {
334 if (I.getNumOperands() == 0) {
335 // Emit a 'ret' instruction
336 BuildMI(BB, X86::RET, 0);
340 unsigned val = getReg(I.getOperand(0));
341 unsigned Class = getClass(I.getOperand(0)->getType());
342 bool isUnsigned = I.getOperand(0)->getType()->isUnsigned();
345 // ret sbyte, ubyte: Extend value into EAX and return
347 BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val);
349 BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val);
352 // ret short, ushort: Extend value into EAX and return
354 BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val);
356 BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val);
359 // ret int, uint, ptr: Move value into EAX and return
361 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(val);
364 // ret float/double: top of FP stack
366 case cFloat: // Floats
367 BuildMI(BB, X86::FLDr4, 1).addReg(val);
369 case cDouble: // Doubles
370 BuildMI(BB, X86::FLDr8, 1).addReg(val);
373 // ret long: use EAX(least significant 32 bits)/EDX (most
374 // significant 32)...uh, I think so Brain, but how do i call
375 // up the two parts of the value from inside this mouse
381 // Emit a 'ret' instruction
382 BuildMI(BB, X86::RET, 0);
385 /// visitBranchInst - Handle conditional and unconditional branches here. Note
386 /// that since code layout is frozen at this point, that if we are trying to
387 /// jump to a block that is the immediate successor of the current block, we can
388 /// just make a fall-through. (but we don't currently).
390 void ISel::visitBranchInst(BranchInst &BI) {
391 if (BI.isConditional()) // Only handles unconditional branches so far...
392 visitInstruction(BI);
394 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
398 /// visitSimpleBinary - Implement simple binary operators for integral types...
399 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
402 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
403 if (B.getType() == Type::BoolTy) // FIXME: Handle bools for logicals
406 unsigned Class = getClass(B.getType());
407 if (Class > 2) // FIXME: Handle longs
410 static const unsigned OpcodeTab[][4] = {
411 // Arithmetic operators
412 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, 0 }, // ADD
413 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, 0 }, // SUB
416 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
417 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
418 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
421 unsigned Opcode = OpcodeTab[OperatorClass][Class];
422 unsigned Op0r = getReg(B.getOperand(0));
423 unsigned Op1r = getReg(B.getOperand(1));
424 BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r);
427 /// visitMul - Multiplies are not simple binary operators because they must deal
428 /// with the EAX register explicitly.
430 void ISel::visitMul(BinaryOperator &I) {
431 unsigned Class = getClass(I.getType());
432 if (Class > 2) // FIXME: Handle longs
435 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
436 static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 };
437 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
439 unsigned Reg = Regs[Class];
440 unsigned Op0Reg = getReg(I.getOperand(0));
441 unsigned Op1Reg = getReg(I.getOperand(1));
443 // Put the first operand into one of the A registers...
444 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
446 // Emit the appropriate multiple instruction...
447 // FIXME: We need to mark that this modified AH, DX, or EDX also!!
448 BuildMI(BB, MulOpcode[Class], 2, Reg).addReg(Reg).addReg(Op1Reg);
450 // Put the result into the destination register...
451 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(Reg);
454 /// visitDivRem - Handle division and remainder instructions... these
455 /// instruction both require the same instructions to be generated, they just
456 /// select the result from a different register. Note that both of these
457 /// instructions work differently for signed and unsigned operands.
459 void ISel::visitDivRem(BinaryOperator &I) {
460 unsigned Class = getClass(I.getType());
461 if (Class > 2) // FIXME: Handle longs
464 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
465 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
466 static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
467 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
468 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
470 static const unsigned DivOpcode[][4] = {
471 { X86::DIVrr8 , X86::DIVrr16 , X86::DIVrr32 , 0 }, // Unsigned division
472 { X86::IDIVrr8, X86::IDIVrr16, X86::IDIVrr32, 0 }, // Signed division
475 bool isSigned = I.getType()->isSigned();
476 unsigned Reg = Regs[Class];
477 unsigned ExtReg = ExtRegs[Class];
478 unsigned Op0Reg = getReg(I.getOperand(0));
479 unsigned Op1Reg = getReg(I.getOperand(1));
481 // Put the first operand into one of the A registers...
482 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
485 // Emit a sign extension instruction...
486 BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg);
488 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
489 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
492 // Figure out which register we want to pick the result out of...
493 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
495 // Emit the appropriate divide or remainder instruction...
496 // FIXME: We need to mark that this modified AH, DX, or EDX also!!
497 BuildMI(BB,DivOpcode[isSigned][Class], 2, DestReg).addReg(Reg).addReg(Op1Reg);
499 // Put the result into the destination register...
500 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(DestReg);
503 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
504 /// for constant immediate shift values, and for constant immediate
505 /// shift values equal to 1. Even the general case is sort of special,
506 /// because the shift amount has to be in CL, not just any old register.
508 void ISel::visitShiftInst (ShiftInst &I) {
509 unsigned Op0r = getReg (I.getOperand(0));
510 unsigned DestReg = getReg(I);
511 bool isLeftShift = I.getOpcode() == Instruction::Shl;
512 bool isOperandSigned = I.getType()->isUnsigned();
513 unsigned OperandClass = getClass(I.getType());
515 if (OperandClass > 2)
516 visitInstruction(I); // Can't handle longs yet!
518 if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
520 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
521 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
522 unsigned char shAmt = CUI->getValue();
524 static const unsigned ConstantOperand[][4] = {
525 { X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
526 { X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
527 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
528 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
531 const unsigned *OpTab = // Figure out the operand table to use
532 ConstantOperand[isLeftShift*2+isOperandSigned];
534 // Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
535 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
539 // The shift amount is non-constant.
541 // In fact, you can only shift with a variable shift amount if
542 // that amount is already in the CL register, so we have to put it
546 // Emit: move cl, shiftAmount (put the shift amount in CL.)
547 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
549 // This is a shift right (SHR).
550 static const unsigned NonConstantOperand[][4] = {
551 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
552 { X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
553 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
554 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
557 const unsigned *OpTab = // Figure out the operand table to use
558 NonConstantOperand[isLeftShift*2+isOperandSigned];
560 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL);
564 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
567 void ISel::visitLoadInst(LoadInst &I) {
568 unsigned Class = getClass(I.getType());
569 if (Class > 2) // FIXME: Handle longs and others...
572 static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
574 unsigned AddressReg = getReg(I.getOperand(0));
575 addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg);
578 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
581 void ISel::visitStoreInst(StoreInst &I) {
582 unsigned Class = getClass(I.getOperand(0)->getType());
583 if (Class > 2) // FIXME: Handle longs and others...
586 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
588 unsigned ValReg = getReg(I.getOperand(0));
589 unsigned AddressReg = getReg(I.getOperand(1));
590 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
594 /// visitPHINode - Turn an LLVM PHI node into an X86 PHI node...
596 void ISel::visitPHINode(PHINode &PN) {
597 MachineInstr *MI = BuildMI(BB, X86::PHI, PN.getNumOperands(), getReg(PN));
599 for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
600 // FIXME: This will put constants after the PHI nodes in the block, which
601 // is invalid. They should be put inline into the PHI node eventually.
603 MI->addRegOperand(getReg(PN.getIncomingValue(i)));
604 MI->addPCDispOperand(PN.getIncomingBlock(i));
609 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
610 /// into a machine code representation is a very simple peep-hole fashion. The
611 /// generated code sucks but the implementation is nice and simple.
613 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {