1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 platform
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/iTerminators.h"
12 #include "llvm/iOperators.h"
13 #include "llvm/iOther.h"
14 #include "llvm/iPHINode.h"
15 #include "llvm/iMemory.h"
16 #include "llvm/Type.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Pass.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Support/InstVisitor.h"
24 #include "llvm/Target/MRegisterInfo.h"
27 using namespace MOTy; // Get Use, Def, UseAndDef
30 struct ISel : public FunctionPass, InstVisitor<ISel> {
32 MachineFunction *F; // The function we are compiling into
33 MachineBasicBlock *BB; // The current MBB we are compiling
36 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
38 ISel(TargetMachine &tm)
39 : TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
41 /// runOnFunction - Top level implementation of instruction selection for
42 /// the entire function.
44 bool runOnFunction(Function &Fn) {
45 F = &MachineFunction::construct(&Fn, TM);
48 CurReg = MRegisterInfo::FirstVirtualRegister;
50 return false; // We never modify the LLVM itself.
53 /// visitBasicBlock - This method is called when we are visiting a new basic
54 /// block. This simply creates a new MachineBasicBlock to emit code into
55 /// and adds it to the current MachineFunction. Subsequent visit* for
56 /// instructions will be invoked for all instructions in the basic block.
58 void visitBasicBlock(BasicBlock &LLVM_BB) {
59 BB = new MachineBasicBlock(&LLVM_BB);
60 // FIXME: Use the auto-insert form when it's available
61 F->getBasicBlockList().push_back(BB);
64 // Visitation methods for various instructions. These methods simply emit
65 // fixed X86 code for each instruction.
68 // Control flow operators
69 void visitReturnInst(ReturnInst &RI);
70 void visitBranchInst(BranchInst &BI);
71 void visitCallInst(CallInst &I);
73 // Arithmetic operators
74 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
75 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
76 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
77 void doMultiply(unsigned destReg, const Type *resultType,
78 unsigned op0Reg, unsigned op1Reg);
79 void visitMul(BinaryOperator &B);
81 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
82 void visitRem(BinaryOperator &B) { visitDivRem(B); }
83 void visitDivRem(BinaryOperator &B);
86 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
87 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
88 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
90 // Binary comparison operators
91 void visitSetCCInst(SetCondInst &I, unsigned OpNum);
92 void visitSetEQ(SetCondInst &I) { visitSetCCInst(I, 0); }
93 void visitSetNE(SetCondInst &I) { visitSetCCInst(I, 1); }
94 void visitSetLT(SetCondInst &I) { visitSetCCInst(I, 2); }
95 void visitSetGT(SetCondInst &I) { visitSetCCInst(I, 3); }
96 void visitSetLE(SetCondInst &I) { visitSetCCInst(I, 4); }
97 void visitSetGE(SetCondInst &I) { visitSetCCInst(I, 5); }
99 // Memory Instructions
100 void visitLoadInst(LoadInst &I);
101 void visitStoreInst(StoreInst &I);
102 void visitGetElementPtrInst(GetElementPtrInst &I);
103 void visitMallocInst(MallocInst &I);
104 void visitFreeInst(FreeInst &I);
105 void visitAllocaInst(AllocaInst &I);
108 void visitShiftInst(ShiftInst &I);
109 void visitPHINode(PHINode &I);
110 void visitCastInst(CastInst &I);
112 void visitInstruction(Instruction &I) {
113 std::cerr << "Cannot instruction select: " << I;
117 /// promote32 - Make a value 32-bits wide, and put it somewhere.
118 void promote32 (const unsigned targetReg, Value *v);
120 // emitGEPOperation - Common code shared between visitGetElementPtrInst and
121 // constant expression GEP support.
123 void emitGEPOperation(Value *Src, User::op_iterator IdxBegin,
124 User::op_iterator IdxEnd, unsigned TargetReg);
126 /// copyConstantToRegister - Output the instructions required to put the
127 /// specified constant into the specified register.
129 void copyConstantToRegister(Constant *C, unsigned Reg);
131 /// makeAnotherReg - This method returns the next register number
132 /// we haven't yet used.
133 unsigned makeAnotherReg(const Type *Ty) {
134 // Add the mapping of regnumber => reg class to MachineFunction
135 F->addRegMap(CurReg, TM.getRegisterInfo()->getRegClassForType(Ty));
139 /// getReg - This method turns an LLVM value into a register number. This
140 /// is guaranteed to produce the same register number for a particular value
141 /// every time it is queried.
143 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
144 unsigned getReg(Value *V) {
145 unsigned &Reg = RegMap[V];
147 Reg = makeAnotherReg(V->getType());
151 // If this operand is a constant, emit the code to copy the constant into
152 // the register here...
154 if (Constant *C = dyn_cast<Constant>(V)) {
155 copyConstantToRegister(C, Reg);
156 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
157 // Move the address of the global into the register
158 BuildMI(BB, X86::MOVir32, 1, Reg).addReg(GV);
159 } else if (Argument *A = dyn_cast<Argument>(V)) {
160 // Find the position of the argument in the argument list.
161 const Function *f = F->getFunction ();
162 // The function's arguments look like this:
163 // [EBP] -- copy of old EBP
164 // [EBP + 4] -- return address
165 // [EBP + 8] -- first argument (leftmost lexically)
166 // So we want to start with counter = 2.
167 int counter = 2, argPosition = -1;
168 for (Function::const_aiterator ai = f->abegin (), ae = f->aend ();
171 argPosition = counter;
172 break; // Only need to find it once. ;-)
176 assert (argPosition != -1
177 && "Argument not found in current function's argument list");
178 // Load it out of the stack frame at EBP + 4*argPosition.
179 addRegOffset (BuildMI (BB, X86::MOVmr32, 4, Reg), X86::EBP, 4*argPosition);
187 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
191 cByte, cShort, cInt, cLong, cFloat, cDouble
194 /// getClass - Turn a primitive type into a "class" number which is based on the
195 /// size of the type, and whether or not it is floating point.
197 static inline TypeClass getClass(const Type *Ty) {
198 switch (Ty->getPrimitiveID()) {
199 case Type::SByteTyID:
200 case Type::UByteTyID: return cByte; // Byte operands are class #0
201 case Type::ShortTyID:
202 case Type::UShortTyID: return cShort; // Short operands are class #1
205 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
208 case Type::ULongTyID: //return cLong; // Longs are class #3
209 return cInt; // FIXME: LONGS ARE TREATED AS INTS!
211 case Type::FloatTyID: return cFloat; // Float is class #4
212 case Type::DoubleTyID: return cDouble; // Doubles are class #5
214 assert(0 && "Invalid type to getClass!");
215 return cByte; // not reached
220 /// copyConstantToRegister - Output the instructions required to put the
221 /// specified constant into the specified register.
223 void ISel::copyConstantToRegister(Constant *C, unsigned R) {
224 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
225 if (CE->getOpcode() == Instruction::GetElementPtr) {
226 emitGEPOperation(CE->getOperand(0), CE->op_begin()+1, CE->op_end(), R);
230 std::cerr << "Offending expr: " << C << "\n";
231 assert (0 && "Constant expressions not yet handled!\n");
234 if (C->getType()->isIntegral()) {
235 unsigned Class = getClass(C->getType());
236 assert(Class != 3 && "Type not handled yet!");
238 static const unsigned IntegralOpcodeTab[] = {
239 X86::MOVir8, X86::MOVir16, X86::MOVir32
242 if (C->getType()->isSigned()) {
243 ConstantSInt *CSI = cast<ConstantSInt>(C);
244 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
246 ConstantUInt *CUI = cast<ConstantUInt>(C);
247 BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
249 } else if (isa <ConstantPointerNull> (C)) {
250 // Copy zero (null pointer) to the register.
251 BuildMI (BB, X86::MOVir32, 1, R).addZImm(0);
252 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
253 unsigned SrcReg = getReg(CPR->getValue());
254 BuildMI (BB, X86::MOVrr32, 1, R).addReg(SrcReg);
256 std::cerr << "Offending constant: " << C << "\n";
257 assert(0 && "Type not handled yet!");
262 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
263 /// register, then move it to wherever the result should be.
264 /// We handle FP setcc instructions by pushing them, doing a
265 /// compare-and-pop-twice, and then copying the concodes to the main
266 /// processor's concodes (I didn't make this up, it's in the Intel manual)
268 void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
269 // The arguments are already supposed to be of the same type.
270 const Type *CompTy = I.getOperand(0)->getType();
271 unsigned reg1 = getReg(I.getOperand(0));
272 unsigned reg2 = getReg(I.getOperand(1));
274 unsigned Class = getClass(CompTy);
276 // Emit: cmp <var1>, <var2> (do the comparison). We can
277 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
280 BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2);
283 BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2);
286 BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2);
289 // Push the variables on the stack with fldl opcodes.
290 // FIXME: assuming var1, var2 are in memory, if not, spill to
292 case cFloat: // Floats
293 BuildMI (BB, X86::FLDr32, 1).addReg (reg1);
294 BuildMI (BB, X86::FLDr32, 1).addReg (reg2);
296 case cDouble: // Doubles
297 BuildMI (BB, X86::FLDr64, 1).addReg (reg1);
298 BuildMI (BB, X86::FLDr64, 1).addReg (reg2);
305 if (CompTy->isFloatingPoint()) {
306 // (Non-trapping) compare and pop twice.
307 BuildMI (BB, X86::FUCOMPP, 0);
308 // Move fp status word (concodes) to ax.
309 BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
310 // Load real concodes from ax.
311 BuildMI (BB, X86::SAHF, 1).addReg(X86::AH);
314 // Emit setOp instruction (extract concode; clobbers ax),
315 // using the following mapping:
316 // LLVM -> X86 signed X86 unsigned
318 // seteq -> sete sete
319 // setne -> setne setne
320 // setlt -> setl setb
321 // setgt -> setg seta
322 // setle -> setle setbe
323 // setge -> setge setae
325 static const unsigned OpcodeTab[2][6] = {
326 {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAr, X86::SETBEr, X86::SETAEr},
327 {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGr, X86::SETLEr, X86::SETGEr},
330 BuildMI(BB, OpcodeTab[CompTy->isSigned()][OpNum], 0, X86::AL);
332 // Put it in the result using a move.
333 BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL);
336 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
337 /// operand, in the specified target register.
339 ISel::promote32 (unsigned targetReg, Value *v)
341 unsigned vReg = getReg (v);
342 unsigned Class = getClass (v->getType ());
343 bool isUnsigned = v->getType ()->isUnsigned ();
344 assert (((Class == cByte) || (Class == cShort) || (Class == cInt))
345 && "Unpromotable operand class in promote32");
349 // Extend value into target register (8->32)
351 BuildMI (BB, X86::MOVZXr32r8, 1, targetReg).addReg (vReg);
353 BuildMI (BB, X86::MOVSXr32r8, 1, targetReg).addReg (vReg);
356 // Extend value into target register (16->32)
358 BuildMI (BB, X86::MOVZXr32r16, 1, targetReg).addReg (vReg);
360 BuildMI (BB, X86::MOVSXr32r16, 1, targetReg).addReg (vReg);
363 // Move value into target register (32->32)
364 BuildMI (BB, X86::MOVrr32, 1, targetReg).addReg (vReg);
369 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
370 /// we have the following possibilities:
372 /// ret void: No return value, simply emit a 'ret' instruction
373 /// ret sbyte, ubyte : Extend value into EAX and return
374 /// ret short, ushort: Extend value into EAX and return
375 /// ret int, uint : Move value into EAX and return
376 /// ret pointer : Move value into EAX and return
377 /// ret long, ulong : Move value into EAX/EDX and return
378 /// ret float/double : Top of FP stack
381 ISel::visitReturnInst (ReturnInst &I)
383 if (I.getNumOperands () == 0)
385 // Emit a 'ret' instruction
386 BuildMI (BB, X86::RET, 0);
389 Value *rv = I.getOperand (0);
390 unsigned Class = getClass (rv->getType ());
393 // integral return values: extend or move into EAX and return.
397 promote32 (X86::EAX, rv);
399 // ret float/double: top of FP stack
401 case cFloat: // Floats
402 BuildMI (BB, X86::FLDr32, 1).addReg (getReg (rv));
404 case cDouble: // Doubles
405 BuildMI (BB, X86::FLDr64, 1).addReg (getReg (rv));
408 // ret long: use EAX(least significant 32 bits)/EDX (most
409 // significant 32)...uh, I think so Brain, but how do i call
410 // up the two parts of the value from inside this mouse
413 visitInstruction (I);
415 // Emit a 'ret' instruction
416 BuildMI (BB, X86::RET, 0);
419 /// visitBranchInst - Handle conditional and unconditional branches here. Note
420 /// that since code layout is frozen at this point, that if we are trying to
421 /// jump to a block that is the immediate successor of the current block, we can
422 /// just make a fall-through. (but we don't currently).
425 ISel::visitBranchInst (BranchInst & BI)
427 if (BI.isConditional ())
429 BasicBlock *ifTrue = BI.getSuccessor (0);
430 BasicBlock *ifFalse = BI.getSuccessor (1); // this is really unobvious
432 // simplest thing I can think of: compare condition with zero,
433 // followed by jump-if-equal to ifFalse, and jump-if-nonequal to
435 unsigned int condReg = getReg (BI.getCondition ());
436 BuildMI (BB, X86::CMPri8, 2).addReg (condReg).addZImm (0);
437 BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0));
438 BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1));
440 else // unconditional branch
442 BuildMI (BB, X86::JMP, 1).addPCDisp (BI.getSuccessor (0));
446 /// visitCallInst - Push args on stack and do a procedure call instruction.
448 ISel::visitCallInst (CallInst & CI)
450 // keep a counter of how many bytes we pushed on the stack
451 unsigned bytesPushed = 0;
453 // Push the arguments on the stack in reverse order, as specified by
455 for (unsigned i = CI.getNumOperands()-1; i >= 1; --i)
457 Value *v = CI.getOperand (i);
458 switch (getClass (v->getType ()))
462 // Promote V to 32 bits wide, and move the result into EAX,
464 promote32 (X86::EAX, v);
465 BuildMI (BB, X86::PUSHr32, 1).addReg (X86::EAX);
470 unsigned Reg = getReg(v);
471 BuildMI (BB, X86::PUSHr32, 1).addReg(Reg);
476 // FIXME: long/ulong/double args not handled.
477 visitInstruction (CI);
481 // Emit a CALL instruction with PC-relative displacement.
482 BuildMI (BB, X86::CALLpcrel32, 1).addPCDisp (CI.getCalledValue ());
484 // Adjust the stack by `bytesPushed' amount if non-zero
486 BuildMI (BB, X86::ADDri32, 2).addReg(X86::ESP).addZImm(bytesPushed);
488 // If there is a return value, scavenge the result from the location the call
491 if (CI.getType() != Type::VoidTy) {
492 unsigned resultTypeClass = getClass (CI.getType ());
493 switch (resultTypeClass) {
497 // Integral results are in %eax, or the appropriate portion
499 static const unsigned regRegMove[] = {
500 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
502 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
503 BuildMI (BB, regRegMove[resultTypeClass], 1,
504 getReg (CI)).addReg (AReg[resultTypeClass]);
508 // Floating-point return values live in %st(0) (i.e., the top of
509 // the FP stack.) The general way to approach this is to do a
510 // FSTP to save the top of the FP stack on the real stack, then
511 // do a MOV to load the top of the real stack into the target
513 visitInstruction (CI); // FIXME: add the right args for the calls below
514 // BuildMI (BB, X86::FSTPm32, 0);
515 // BuildMI (BB, X86::MOVmr32, 0);
518 std::cerr << "Cannot get return value for call of type '"
519 << *CI.getType() << "'\n";
520 visitInstruction(CI);
525 /// visitSimpleBinary - Implement simple binary operators for integral types...
526 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
529 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
530 if (B.getType() == Type::BoolTy) // FIXME: Handle bools for logicals
533 unsigned Class = getClass(B.getType());
534 if (Class > 2) // FIXME: Handle longs
537 static const unsigned OpcodeTab[][4] = {
538 // Arithmetic operators
539 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, 0 }, // ADD
540 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, 0 }, // SUB
543 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
544 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
545 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
548 unsigned Opcode = OpcodeTab[OperatorClass][Class];
549 unsigned Op0r = getReg(B.getOperand(0));
550 unsigned Op1r = getReg(B.getOperand(1));
551 BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r);
554 /// doMultiply - Emit appropriate instructions to multiply together
555 /// the registers op0Reg and op1Reg, and put the result in destReg.
556 /// The type of the result should be given as resultType.
558 ISel::doMultiply(unsigned destReg, const Type *resultType,
559 unsigned op0Reg, unsigned op1Reg)
561 unsigned Class = getClass (resultType);
564 assert (Class <= 2 && "Someday, we will learn how to multiply"
565 "longs and floating-point numbers. This is not that day.");
567 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
568 static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 };
569 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
570 unsigned Reg = Regs[Class];
572 // Emit a MOV to put the first operand into the appropriately-sized
574 BuildMI (BB, MovOpcode[Class], 1, Reg).addReg (op0Reg);
576 // Emit the appropriate multiply instruction.
577 BuildMI (BB, MulOpcode[Class], 1).addReg (op1Reg);
579 // Emit another MOV to put the result into the destination register.
580 BuildMI (BB, MovOpcode[Class], 1, destReg).addReg (Reg);
583 /// visitMul - Multiplies are not simple binary operators because they must deal
584 /// with the EAX register explicitly.
586 void ISel::visitMul(BinaryOperator &I) {
587 doMultiply (getReg (I), I.getType (),
588 getReg (I.getOperand (0)), getReg (I.getOperand (1)));
592 /// visitDivRem - Handle division and remainder instructions... these
593 /// instruction both require the same instructions to be generated, they just
594 /// select the result from a different register. Note that both of these
595 /// instructions work differently for signed and unsigned operands.
597 void ISel::visitDivRem(BinaryOperator &I) {
598 unsigned Class = getClass(I.getType());
599 if (Class > 2) // FIXME: Handle longs
602 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
603 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
604 static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
605 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
606 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
608 static const unsigned DivOpcode[][4] = {
609 { X86::DIVrr8 , X86::DIVrr16 , X86::DIVrr32 , 0 }, // Unsigned division
610 { X86::IDIVrr8, X86::IDIVrr16, X86::IDIVrr32, 0 }, // Signed division
613 bool isSigned = I.getType()->isSigned();
614 unsigned Reg = Regs[Class];
615 unsigned ExtReg = ExtRegs[Class];
616 unsigned Op0Reg = getReg(I.getOperand(0));
617 unsigned Op1Reg = getReg(I.getOperand(1));
619 // Put the first operand into one of the A registers...
620 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
623 // Emit a sign extension instruction...
624 BuildMI(BB, ExtOpcode[Class], 0);
626 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
627 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
630 // Emit the appropriate divide or remainder instruction...
631 BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
633 // Figure out which register we want to pick the result out of...
634 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
636 // Put the result into the destination register...
637 BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(DestReg);
641 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
642 /// for constant immediate shift values, and for constant immediate
643 /// shift values equal to 1. Even the general case is sort of special,
644 /// because the shift amount has to be in CL, not just any old register.
646 void ISel::visitShiftInst (ShiftInst &I) {
647 unsigned Op0r = getReg (I.getOperand(0));
648 unsigned DestReg = getReg(I);
649 bool isLeftShift = I.getOpcode() == Instruction::Shl;
650 bool isOperandSigned = I.getType()->isUnsigned();
651 unsigned OperandClass = getClass(I.getType());
653 if (OperandClass > 2)
654 visitInstruction(I); // Can't handle longs yet!
656 if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
658 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
659 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
660 unsigned char shAmt = CUI->getValue();
662 static const unsigned ConstantOperand[][4] = {
663 { X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
664 { X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
665 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
666 { X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
669 const unsigned *OpTab = // Figure out the operand table to use
670 ConstantOperand[isLeftShift*2+isOperandSigned];
672 // Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
673 BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
677 // The shift amount is non-constant.
679 // In fact, you can only shift with a variable shift amount if
680 // that amount is already in the CL register, so we have to put it
684 // Emit: move cl, shiftAmount (put the shift amount in CL.)
685 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
687 // This is a shift right (SHR).
688 static const unsigned NonConstantOperand[][4] = {
689 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
690 { X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
691 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
692 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
695 const unsigned *OpTab = // Figure out the operand table to use
696 NonConstantOperand[isLeftShift*2+isOperandSigned];
698 BuildMI(BB, OpTab[OperandClass], 1, DestReg).addReg(Op0r);
703 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
706 void ISel::visitLoadInst(LoadInst &I) {
707 unsigned Class = getClass(I.getType());
708 if (Class > 2) // FIXME: Handle longs and others...
711 static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
713 unsigned AddressReg = getReg(I.getOperand(0));
714 addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg);
718 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
721 void ISel::visitStoreInst(StoreInst &I) {
722 unsigned Class = getClass(I.getOperand(0)->getType());
723 if (Class > 2) // FIXME: Handle longs and others...
726 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
728 unsigned ValReg = getReg(I.getOperand(0));
729 unsigned AddressReg = getReg(I.getOperand(1));
730 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
734 /// visitPHINode - Turn an LLVM PHI node into an X86 PHI node...
736 void ISel::visitPHINode(PHINode &PN) {
737 MachineInstr *MI = BuildMI(BB, X86::PHI, PN.getNumOperands(), getReg(PN));
739 for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
740 // FIXME: This will put constants after the PHI nodes in the block, which
741 // is invalid. They should be put inline into the PHI node eventually.
743 MI->addRegOperand(getReg(PN.getIncomingValue(i)));
744 MI->addPCDispOperand(PN.getIncomingBlock(i));
748 /// visitCastInst - Here we have various kinds of copying with or without
749 /// sign extension going on.
751 ISel::visitCastInst (CastInst &CI)
753 const Type *targetType = CI.getType ();
754 Value *operand = CI.getOperand (0);
755 unsigned int operandReg = getReg (operand);
756 const Type *sourceType = operand->getType ();
757 unsigned int destReg = getReg (CI);
759 // Currently we handle:
763 // 2) cast {sbyte, ubyte} to {sbyte, ubyte}
764 // cast {short, ushort} to {ushort, short}
765 // cast {int, uint, ptr} to {int, uint, ptr}
767 // 3) cast {sbyte, ubyte} to {ushort, short}
768 // cast {sbyte, ubyte} to {int, uint, ptr}
769 // cast {short, ushort} to {int, uint, ptr}
771 // 4) cast {int, uint, ptr} to {short, ushort}
772 // cast {int, uint, ptr} to {sbyte, ubyte}
773 // cast {short, ushort} to {sbyte, ubyte}
775 // 1) Implement casts to bool by using compare on the operand followed
776 // by set if not zero on the result.
777 if (targetType == Type::BoolTy)
779 BuildMI (BB, X86::CMPri8, 2).addReg (operandReg).addZImm (0);
780 BuildMI (BB, X86::SETNEr, 1, destReg);
783 // 2) Implement casts between values of the same type class (as determined
784 // by getClass) by using a register-to-register move.
785 unsigned int srcClass = getClass (sourceType);
786 unsigned int targClass = getClass (targetType);
787 static const unsigned regRegMove[] = {
788 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
790 if ((srcClass < 3) && (targClass < 3) && (srcClass == targClass))
792 BuildMI (BB, regRegMove[srcClass], 1, destReg).addReg (operandReg);
795 // 3) Handle cast of SMALLER int to LARGER int using a move with sign
796 // extension or zero extension, depending on whether the source type
798 if ((srcClass < 3) && (targClass < 3) && (srcClass < targClass))
800 static const unsigned ops[] = {
801 X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16,
802 X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16
804 unsigned srcSigned = sourceType->isSigned ();
805 BuildMI (BB, ops[3 * srcSigned + srcClass + targClass - 1], 1,
806 destReg).addReg (operandReg);
809 // 4) Handle cast of LARGER int to SMALLER int using a move to EAX
810 // followed by a move out of AX or AL.
811 if ((srcClass < 3) && (targClass < 3) && (srcClass > targClass))
813 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
814 BuildMI (BB, regRegMove[srcClass], 1,
815 AReg[srcClass]).addReg (operandReg);
816 BuildMI (BB, regRegMove[targClass], 1, destReg).addReg (AReg[srcClass]);
819 // Anything we haven't handled already, we can't (yet) handle at all.
821 // FP to integral casts can be handled with FISTP to store onto the
822 // stack while converting to integer, followed by a MOV to load from
823 // the stack into the result register. Integral to FP casts can be
824 // handled with MOV to store onto the stack, followed by a FILD to
825 // load from the stack while converting to FP. For the moment, I
826 // can't quite get straight in my head how to borrow myself some
827 // stack space and write on it. Otherwise, this would be trivial.
828 visitInstruction (CI);
831 /// visitGetElementPtrInst - I don't know, most programs don't have
832 /// getelementptr instructions, right? That means we can put off
833 /// implementing this, right? Right. This method emits machine
834 /// instructions to perform type-safe pointer arithmetic. I am
835 /// guessing this could be cleaned up somewhat to use fewer temporary
838 ISel::visitGetElementPtrInst (GetElementPtrInst &I)
840 emitGEPOperation(I.getOperand(0), I.op_begin()+1, I.op_end(), getReg(I));
843 void ISel::emitGEPOperation(Value *Src, User::op_iterator IdxBegin,
844 User::op_iterator IdxEnd, unsigned TargetReg) {
845 const TargetData &TD = TM.getTargetData();
846 const Type *Ty = Src->getType();
847 unsigned basePtrReg = getReg(Src);
849 // GEPs have zero or more indices; we must perform a struct access
850 // or array access for each one.
851 for (GetElementPtrInst::op_iterator oi = IdxBegin,
852 oe = IdxEnd; oi != oe; ++oi) {
854 unsigned nextBasePtrReg = makeAnotherReg(Type::UIntTy);
855 if (const StructType *StTy = dyn_cast <StructType> (Ty)) {
856 // It's a struct access. idx is the index into the structure,
857 // which names the field. This index must have ubyte type.
858 const ConstantUInt *CUI = cast <ConstantUInt> (idx);
859 assert (CUI->getType () == Type::UByteTy
860 && "Funny-looking structure index in GEP");
861 // Use the TargetData structure to pick out what the layout of
862 // the structure is in memory. Since the structure index must
863 // be constant, we can get its value and use it to find the
864 // right byte offset from the StructLayout class's list of
865 // structure member offsets.
866 unsigned idxValue = CUI->getValue ();
867 unsigned memberOffset =
868 TD.getStructLayout (StTy)->MemberOffsets[idxValue];
869 // Emit an ADD to add memberOffset to the basePtr.
870 BuildMI (BB, X86::ADDri32, 2,
871 nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
872 // The next type is the member of the structure selected by the
874 Ty = StTy->getElementTypes ()[idxValue];
875 } else if (const SequentialType *SqTy = cast <SequentialType> (Ty)) {
876 // It's an array or pointer access: [ArraySize x ElementType].
877 const Type *typeOfSequentialTypeIndex = SqTy->getIndexType ();
878 // idx is the index into the array. Unlike with structure
879 // indices, we may not know its actual value at code-generation
881 assert (idx->getType () == typeOfSequentialTypeIndex
882 && "Funny-looking array index in GEP");
883 // We want to add basePtrReg to (idxReg * sizeof
884 // ElementType). First, we must find the size of the pointed-to
885 // type. (Not coincidentally, the next type is the type of the
886 // elements in the array.)
887 Ty = SqTy->getElementType ();
888 unsigned elementSize = TD.getTypeSize (Ty);
889 unsigned elementSizeReg = makeAnotherReg(Type::UIntTy);
890 copyConstantToRegister (ConstantInt::get (typeOfSequentialTypeIndex,
893 unsigned idxReg = getReg (idx);
894 // Emit a MUL to multiply the register holding the index by
895 // elementSize, putting the result in memberOffsetReg.
896 unsigned memberOffsetReg = makeAnotherReg(Type::UIntTy);
897 doMultiply (memberOffsetReg, typeOfSequentialTypeIndex,
898 elementSizeReg, idxReg);
899 // Emit an ADD to add memberOffsetReg to the basePtr.
900 BuildMI (BB, X86::ADDrr32, 2,
901 nextBasePtrReg).addReg (basePtrReg).addReg (memberOffsetReg);
903 // Now that we are here, further indices refer to subtypes of this
904 // one, so we don't need to worry about basePtrReg itself, anymore.
905 basePtrReg = nextBasePtrReg;
907 // After we have processed all the indices, the result is left in
908 // basePtrReg. Move it to the register where we were expected to
909 // put the answer. A 32-bit move should do it, because we are in
911 BuildMI (BB, X86::MOVrr32, 1, TargetReg).addReg (basePtrReg);
915 /// visitMallocInst - I know that personally, whenever I want to remember
916 /// something, I have to clear off some space in my brain.
918 ISel::visitMallocInst (MallocInst &I)
920 // We assume that by this point, malloc instructions have been
921 // lowered to calls, and dlsym will magically find malloc for us.
922 // So we do not want to see malloc instructions here.
923 visitInstruction (I);
927 /// visitFreeInst - same story as MallocInst
929 ISel::visitFreeInst (FreeInst &I)
931 // We assume that by this point, free instructions have been
932 // lowered to calls, and dlsym will magically find free for us.
933 // So we do not want to see free instructions here.
934 visitInstruction (I);
938 /// visitAllocaInst - I want some stack space. Come on, man, I said I
939 /// want some freakin' stack space.
941 ISel::visitAllocaInst (AllocaInst &I)
943 // Find the data size of the alloca inst's getAllocatedType.
944 const Type *allocatedType = I.getAllocatedType ();
945 const TargetData &TD = TM.DataLayout;
946 unsigned allocatedTypeSize = TD.getTypeSize (allocatedType);
947 // Keep stack 32-bit aligned.
948 unsigned int allocatedTypeWords = allocatedTypeSize / 4;
949 if (allocatedTypeSize % 4 != 0) { allocatedTypeWords++; }
950 // Subtract size from stack pointer, thereby allocating some space.
951 BuildMI (BB, X86::SUBri32, 1, X86::ESP).addZImm (allocatedTypeWords * 4);
952 // Put a pointer to the space into the result register, by copying
953 // the stack pointer.
954 BuildMI (BB, X86::MOVrr32, 1, getReg (I)).addReg (X86::ESP);
958 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
959 /// into a machine code representation is a very simple peep-hole fashion. The
960 /// generated code sucks but the implementation is nice and simple.
962 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {