1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the x86 target
12 //===----------------------------------------------------------------------===//
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Function.h"
20 #include "llvm/Instructions.h"
21 #include "llvm/IntrinsicLowering.h"
22 #include "llvm/Pass.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Target/MRegisterInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Support/GetElementPtrTypeIterator.h"
30 #include "llvm/Support/InstVisitor.h"
31 #include "llvm/Support/CFG.h"
32 #include "Support/Statistic.h"
37 NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
40 /// BMI - A special BuildMI variant that takes an iterator to insert the
41 /// instruction at as well as a basic block. This is the version for when you
42 /// have a destination register in mind.
43 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
44 MachineBasicBlock::iterator I,
45 int Opcode, unsigned NumOperands,
47 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
49 return MachineInstrBuilder(MI).addReg(DestReg, MachineOperand::Def);
52 /// BMI - A special BuildMI variant that takes an iterator to insert the
53 /// instruction at as well as a basic block.
54 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
55 MachineBasicBlock::iterator I,
56 int Opcode, unsigned NumOperands) {
57 MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
59 return MachineInstrBuilder(MI);
64 struct ISel : public FunctionPass, InstVisitor<ISel> {
66 MachineFunction *F; // The function we are compiling into
67 MachineBasicBlock *BB; // The current MBB we are compiling
68 int VarArgsFrameIndex; // FrameIndex for start of varargs area
69 int ReturnAddressIndex; // FrameIndex for the return address
71 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
73 // MBBMap - Mapping between LLVM BB -> Machine BB
74 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
76 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
78 /// runOnFunction - Top level implementation of instruction selection for
79 /// the entire function.
81 bool runOnFunction(Function &Fn) {
82 // First pass over the function, lower any unknown intrinsic functions
83 // with the IntrinsicLowering class.
84 LowerUnknownIntrinsicFunctionCalls(Fn);
86 F = &MachineFunction::construct(&Fn, TM);
88 // Create all of the machine basic blocks for the function...
89 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
90 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
94 // Set up a frame object for the return address. This is used by the
95 // llvm.returnaddress & llvm.frameaddress intrinisics.
96 ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
98 // Copy incoming arguments off of the stack...
99 LoadArgumentsToVirtualRegs(Fn);
101 // Instruction select everything except PHI nodes
104 // Select the PHI nodes
107 // Insert the FP_REG_KILL instructions into blocks that need them.
113 // We always build a machine code representation for the function
117 virtual const char *getPassName() const {
118 return "X86 Simple Instruction Selection";
121 /// visitBasicBlock - This method is called when we are visiting a new basic
122 /// block. This simply creates a new MachineBasicBlock to emit code into
123 /// and adds it to the current MachineFunction. Subsequent visit* for
124 /// instructions will be invoked for all instructions in the basic block.
126 void visitBasicBlock(BasicBlock &LLVM_BB) {
127 BB = MBBMap[&LLVM_BB];
130 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
131 /// function, lowering any calls to unknown intrinsic functions into the
132 /// equivalent LLVM code.
133 void LowerUnknownIntrinsicFunctionCalls(Function &F);
135 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
136 /// from the stack into virtual registers.
138 void LoadArgumentsToVirtualRegs(Function &F);
140 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
141 /// because we have to generate our sources into the source basic blocks,
142 /// not the current one.
144 void SelectPHINodes();
146 /// InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks
147 /// that need them. This only occurs due to the floating point stackifier
148 /// not being aggressive enough to handle arbitrary global stackification.
150 void InsertFPRegKills();
152 // Visitation methods for various instructions. These methods simply emit
153 // fixed X86 code for each instruction.
156 // Control flow operators
157 void visitReturnInst(ReturnInst &RI);
158 void visitBranchInst(BranchInst &BI);
164 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
165 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
167 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
168 const std::vector<ValueRecord> &Args);
169 void visitCallInst(CallInst &I);
170 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
172 // Arithmetic operators
173 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
174 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
175 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
176 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
177 unsigned DestReg, const Type *DestTy,
178 unsigned Op0Reg, unsigned Op1Reg);
179 void doMultiplyConst(MachineBasicBlock *MBB,
180 MachineBasicBlock::iterator MBBI,
181 unsigned DestReg, const Type *DestTy,
182 unsigned Op0Reg, unsigned Op1Val);
183 void visitMul(BinaryOperator &B);
185 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
186 void visitRem(BinaryOperator &B) { visitDivRem(B); }
187 void visitDivRem(BinaryOperator &B);
190 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
191 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
192 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
194 // Comparison operators...
195 void visitSetCondInst(SetCondInst &I);
196 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
197 MachineBasicBlock *MBB,
198 MachineBasicBlock::iterator MBBI);
200 // Memory Instructions
201 void visitLoadInst(LoadInst &I);
202 void visitStoreInst(StoreInst &I);
203 void visitGetElementPtrInst(GetElementPtrInst &I);
204 void visitAllocaInst(AllocaInst &I);
205 void visitMallocInst(MallocInst &I);
206 void visitFreeInst(FreeInst &I);
209 void visitShiftInst(ShiftInst &I);
210 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
211 void visitCastInst(CastInst &I);
212 void visitVANextInst(VANextInst &I);
213 void visitVAArgInst(VAArgInst &I);
215 void visitInstruction(Instruction &I) {
216 std::cerr << "Cannot instruction select: " << I;
220 /// promote32 - Make a value 32-bits wide, and put it somewhere.
222 void promote32(unsigned targetReg, const ValueRecord &VR);
224 // getGEPIndex - This is used to fold GEP instructions into X86 addressing
226 void getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
227 std::vector<Value*> &GEPOps,
228 std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
229 unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
231 /// isGEPFoldable - Return true if the specified GEP can be completely
232 /// folded into the addressing mode of a load/store or lea instruction.
233 bool isGEPFoldable(MachineBasicBlock *MBB,
234 Value *Src, User::op_iterator IdxBegin,
235 User::op_iterator IdxEnd, unsigned &BaseReg,
236 unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
238 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
239 /// constant expression GEP support.
241 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
242 Value *Src, User::op_iterator IdxBegin,
243 User::op_iterator IdxEnd, unsigned TargetReg);
245 /// emitCastOperation - Common code shared between visitCastInst and
246 /// constant expression cast support.
247 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
248 Value *Src, const Type *DestTy, unsigned TargetReg);
250 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
251 /// and constant expression support.
252 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
253 MachineBasicBlock::iterator IP,
254 Value *Op0, Value *Op1,
255 unsigned OperatorClass, unsigned TargetReg);
257 void emitDivRemOperation(MachineBasicBlock *BB,
258 MachineBasicBlock::iterator IP,
259 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
260 const Type *Ty, unsigned TargetReg);
262 /// emitSetCCOperation - Common code shared between visitSetCondInst and
263 /// constant expression support.
264 void emitSetCCOperation(MachineBasicBlock *BB,
265 MachineBasicBlock::iterator IP,
266 Value *Op0, Value *Op1, unsigned Opcode,
269 /// emitShiftOperation - Common code shared between visitShiftInst and
270 /// constant expression support.
271 void emitShiftOperation(MachineBasicBlock *MBB,
272 MachineBasicBlock::iterator IP,
273 Value *Op, Value *ShiftAmount, bool isLeftShift,
274 const Type *ResultTy, unsigned DestReg);
277 /// copyConstantToRegister - Output the instructions required to put the
278 /// specified constant into the specified register.
280 void copyConstantToRegister(MachineBasicBlock *MBB,
281 MachineBasicBlock::iterator MBBI,
282 Constant *C, unsigned Reg);
284 /// makeAnotherReg - This method returns the next register number we haven't
287 /// Long values are handled somewhat specially. They are always allocated
288 /// as pairs of 32 bit integer values. The register number returned is the
289 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
290 /// of the long value.
292 unsigned makeAnotherReg(const Type *Ty) {
293 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
294 "Current target doesn't have X86 reg info??");
295 const X86RegisterInfo *MRI =
296 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
297 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
298 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
299 // Create the lower part
300 F->getSSARegMap()->createVirtualRegister(RC);
301 // Create the upper part.
302 return F->getSSARegMap()->createVirtualRegister(RC)-1;
305 // Add the mapping of regnumber => reg class to MachineFunction
306 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
307 return F->getSSARegMap()->createVirtualRegister(RC);
310 /// getReg - This method turns an LLVM value into a register number. This
311 /// is guaranteed to produce the same register number for a particular value
312 /// every time it is queried.
314 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
315 unsigned getReg(Value *V) {
316 // Just append to the end of the current bb.
317 MachineBasicBlock::iterator It = BB->end();
318 return getReg(V, BB, It);
320 unsigned getReg(Value *V, MachineBasicBlock *MBB,
321 MachineBasicBlock::iterator IPt) {
322 unsigned &Reg = RegMap[V];
324 Reg = makeAnotherReg(V->getType());
328 // If this operand is a constant, emit the code to copy the constant into
329 // the register here...
331 if (Constant *C = dyn_cast<Constant>(V)) {
332 copyConstantToRegister(MBB, IPt, C, Reg);
333 RegMap.erase(V); // Assign a new name to this constant if ref'd again
334 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
335 // Move the address of the global into the register
336 BMI(MBB, IPt, X86::MOVri32, 1, Reg).addGlobalAddress(GV);
337 RegMap.erase(V); // Assign a new name to this address if ref'd again
345 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
349 cByte, cShort, cInt, cFP, cLong
352 /// getClass - Turn a primitive type into a "class" number which is based on the
353 /// size of the type, and whether or not it is floating point.
355 static inline TypeClass getClass(const Type *Ty) {
356 switch (Ty->getPrimitiveID()) {
357 case Type::SByteTyID:
358 case Type::UByteTyID: return cByte; // Byte operands are class #0
359 case Type::ShortTyID:
360 case Type::UShortTyID: return cShort; // Short operands are class #1
363 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
365 case Type::FloatTyID:
366 case Type::DoubleTyID: return cFP; // Floating Point is #3
369 case Type::ULongTyID: return cLong; // Longs are class #4
371 assert(0 && "Invalid type to getClass!");
372 return cByte; // not reached
376 // getClassB - Just like getClass, but treat boolean values as bytes.
377 static inline TypeClass getClassB(const Type *Ty) {
378 if (Ty == Type::BoolTy) return cByte;
383 /// copyConstantToRegister - Output the instructions required to put the
384 /// specified constant into the specified register.
386 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
387 MachineBasicBlock::iterator IP,
388 Constant *C, unsigned R) {
389 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
391 switch (CE->getOpcode()) {
392 case Instruction::GetElementPtr:
393 emitGEPOperation(MBB, IP, CE->getOperand(0),
394 CE->op_begin()+1, CE->op_end(), R);
396 case Instruction::Cast:
397 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
400 case Instruction::Xor: ++Class; // FALL THROUGH
401 case Instruction::Or: ++Class; // FALL THROUGH
402 case Instruction::And: ++Class; // FALL THROUGH
403 case Instruction::Sub: ++Class; // FALL THROUGH
404 case Instruction::Add:
405 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
409 case Instruction::Mul: {
410 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
411 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
412 doMultiply(MBB, IP, R, CE->getType(), Op0Reg, Op1Reg);
415 case Instruction::Div:
416 case Instruction::Rem: {
417 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
418 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
419 emitDivRemOperation(MBB, IP, Op0Reg, Op1Reg,
420 CE->getOpcode() == Instruction::Div,
425 case Instruction::SetNE:
426 case Instruction::SetEQ:
427 case Instruction::SetLT:
428 case Instruction::SetGT:
429 case Instruction::SetLE:
430 case Instruction::SetGE:
431 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
435 case Instruction::Shl:
436 case Instruction::Shr:
437 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
438 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
442 std::cerr << "Offending expr: " << C << "\n";
443 assert(0 && "Constant expression not yet handled!\n");
447 if (C->getType()->isIntegral()) {
448 unsigned Class = getClassB(C->getType());
450 if (Class == cLong) {
451 // Copy the value into the register pair.
452 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
453 BMI(MBB, IP, X86::MOVri32, 1, R).addZImm(Val & 0xFFFFFFFF);
454 BMI(MBB, IP, X86::MOVri32, 1, R+1).addZImm(Val >> 32);
458 assert(Class <= cInt && "Type not handled yet!");
460 static const unsigned IntegralOpcodeTab[] = {
461 X86::MOVri8, X86::MOVri16, X86::MOVri32
464 if (C->getType() == Type::BoolTy) {
465 BMI(MBB, IP, X86::MOVri8, 1, R).addZImm(C == ConstantBool::True);
467 ConstantInt *CI = cast<ConstantInt>(C);
468 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CI->getRawValue());
470 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
471 if (CFP->isExactlyValue(+0.0))
472 BMI(MBB, IP, X86::FLD0, 0, R);
473 else if (CFP->isExactlyValue(+1.0))
474 BMI(MBB, IP, X86::FLD1, 0, R);
476 // Otherwise we need to spill the constant to memory...
477 MachineConstantPool *CP = F->getConstantPool();
478 unsigned CPI = CP->getConstantPoolIndex(CFP);
479 const Type *Ty = CFP->getType();
481 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
482 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDm32 : X86::FLDm64;
483 addConstantPoolReference(BMI(MBB, IP, LoadOpcode, 4, R), CPI);
486 } else if (isa<ConstantPointerNull>(C)) {
487 // Copy zero (null pointer) to the register.
488 BMI(MBB, IP, X86::MOVri32, 1, R).addZImm(0);
489 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
490 BMI(MBB, IP, X86::MOVri32, 1, R).addGlobalAddress(CPR->getValue());
492 std::cerr << "Offending constant: " << C << "\n";
493 assert(0 && "Type not handled yet!");
497 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
498 /// the stack into virtual registers.
500 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
501 // Emit instructions to load the arguments... On entry to a function on the
502 // X86, the stack frame looks like this:
504 // [ESP] -- return address
505 // [ESP + 4] -- first argument (leftmost lexically)
506 // [ESP + 8] -- second argument, if first argument is four bytes in size
509 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
510 MachineFrameInfo *MFI = F->getFrameInfo();
512 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
513 unsigned Reg = getReg(*I);
515 int FI; // Frame object index
516 switch (getClassB(I->getType())) {
518 FI = MFI->CreateFixedObject(1, ArgOffset);
519 addFrameReference(BuildMI(BB, X86::MOVrm8, 4, Reg), FI);
522 FI = MFI->CreateFixedObject(2, ArgOffset);
523 addFrameReference(BuildMI(BB, X86::MOVrm16, 4, Reg), FI);
526 FI = MFI->CreateFixedObject(4, ArgOffset);
527 addFrameReference(BuildMI(BB, X86::MOVrm32, 4, Reg), FI);
530 FI = MFI->CreateFixedObject(8, ArgOffset);
531 addFrameReference(BuildMI(BB, X86::MOVrm32, 4, Reg), FI);
532 addFrameReference(BuildMI(BB, X86::MOVrm32, 4, Reg+1), FI, 4);
533 ArgOffset += 4; // longs require 4 additional bytes
537 if (I->getType() == Type::FloatTy) {
538 Opcode = X86::FLDm32;
539 FI = MFI->CreateFixedObject(4, ArgOffset);
541 Opcode = X86::FLDm64;
542 FI = MFI->CreateFixedObject(8, ArgOffset);
543 ArgOffset += 4; // doubles require 4 additional bytes
545 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
548 assert(0 && "Unhandled argument type!");
550 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
553 // If the function takes variable number of arguments, add a frame offset for
554 // the start of the first vararg value... this is used to expand
556 if (Fn.getFunctionType()->isVarArg())
557 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
561 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
562 /// because we have to generate our sources into the source basic blocks, not
565 void ISel::SelectPHINodes() {
566 const TargetInstrInfo &TII = TM.getInstrInfo();
567 const Function &LF = *F->getFunction(); // The LLVM function...
568 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
569 const BasicBlock *BB = I;
570 MachineBasicBlock &MBB = *MBBMap[I];
572 // Loop over all of the PHI nodes in the LLVM basic block...
573 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
574 for (BasicBlock::const_iterator I = BB->begin();
575 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
577 // Create a new machine instr PHI node, and insert it.
578 unsigned PHIReg = getReg(*PN);
579 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
580 X86::PHI, PN->getNumOperands(), PHIReg);
582 MachineInstr *LongPhiMI = 0;
583 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
584 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
585 X86::PHI, PN->getNumOperands(), PHIReg+1);
587 // PHIValues - Map of blocks to incoming virtual registers. We use this
588 // so that we only initialize one incoming value for a particular block,
589 // even if the block has multiple entries in the PHI node.
591 std::map<MachineBasicBlock*, unsigned> PHIValues;
593 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
594 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
596 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
597 PHIValues.lower_bound(PredMBB);
599 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
600 // We already inserted an initialization of the register for this
601 // predecessor. Recycle it.
602 ValReg = EntryIt->second;
605 // Get the incoming value into a virtual register.
607 Value *Val = PN->getIncomingValue(i);
609 // If this is a constant or GlobalValue, we may have to insert code
610 // into the basic block to compute it into a virtual register.
611 if (isa<Constant>(Val) || isa<GlobalValue>(Val)) {
612 // Because we don't want to clobber any values which might be in
613 // physical registers with the computation of this constant (which
614 // might be arbitrarily complex if it is a constant expression),
615 // just insert the computation at the top of the basic block.
616 MachineBasicBlock::iterator PI = PredMBB->begin();
618 // Skip over any PHI nodes though!
619 while (PI != PredMBB->end() && PI->getOpcode() == X86::PHI)
622 ValReg = getReg(Val, PredMBB, PI);
624 ValReg = getReg(Val);
627 // Remember that we inserted a value for this PHI for this predecessor
628 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
631 PhiMI->addRegOperand(ValReg);
632 PhiMI->addMachineBasicBlockOperand(PredMBB);
634 LongPhiMI->addRegOperand(ValReg+1);
635 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
639 // Now that we emitted all of the incoming values for the PHI node, make
640 // sure to reposition the InsertPoint after the PHI that we just added.
641 // This is needed because we might have inserted a constant into this
642 // block, right after the PHI's which is before the old insert point!
643 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
649 /// RequiresFPRegKill - The floating point stackifier pass cannot insert
650 /// compensation code on critical edges. As such, it requires that we kill all
651 /// FP registers on the exit from any blocks that either ARE critical edges, or
652 /// branch to a block that has incoming critical edges.
654 /// Note that this kill instruction will eventually be eliminated when
655 /// restrictions in the stackifier are relaxed.
657 static bool RequiresFPRegKill(const BasicBlock *BB) {
659 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB); SI!=E; ++SI) {
660 const BasicBlock *Succ = *SI;
661 pred_const_iterator PI = pred_begin(Succ), PE = pred_end(Succ);
662 ++PI; // Block have at least one predecessory
663 if (PI != PE) { // If it has exactly one, this isn't crit edge
664 // If this block has more than one predecessor, check all of the
665 // predecessors to see if they have multiple successors. If so, then the
666 // block we are analyzing needs an FPRegKill.
667 for (PI = pred_begin(Succ); PI != PE; ++PI) {
668 const BasicBlock *Pred = *PI;
669 succ_const_iterator SI2 = succ_begin(Pred);
670 ++SI2; // There must be at least one successor of this block.
671 if (SI2 != succ_end(Pred))
672 return true; // Yes, we must insert the kill on this edge.
676 // If we got this far, there is no need to insert the kill instruction.
683 // InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks that
684 // need them. This only occurs due to the floating point stackifier not being
685 // aggressive enough to handle arbitrary global stackification.
687 // Currently we insert an FP_REG_KILL instruction into each block that uses or
688 // defines a floating point virtual register.
690 // When the global register allocators (like linear scan) finally update live
691 // variable analysis, we can keep floating point values in registers across
692 // portions of the CFG that do not involve critical edges. This will be a big
693 // win, but we are waiting on the global allocators before we can do this.
695 // With a bit of work, the floating point stackifier pass can be enhanced to
696 // break critical edges as needed (to make a place to put compensation code),
697 // but this will require some infrastructure improvements as well.
699 void ISel::InsertFPRegKills() {
700 SSARegMap &RegMap = *F->getSSARegMap();
702 for (MachineFunction::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
703 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I!=E; ++I)
704 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
705 MachineOperand& MO = I->getOperand(i);
706 if (MO.isRegister() && MO.getReg()) {
707 unsigned Reg = MO.getReg();
708 if (MRegisterInfo::isVirtualRegister(Reg))
709 if (RegMap.getRegClass(Reg)->getSize() == 10)
713 // If we haven't found an FP register use or def in this basic block, check
714 // to see if any of our successors has an FP PHI node, which will cause a
715 // copy to be inserted into this block.
716 for (succ_const_iterator SI = succ_begin(BB->getBasicBlock()),
717 E = succ_end(BB->getBasicBlock()); SI != E; ++SI) {
718 MachineBasicBlock *SBB = MBBMap[*SI];
719 for (MachineBasicBlock::iterator I = SBB->begin();
720 I != SBB->end() && I->getOpcode() == X86::PHI; ++I) {
721 if (RegMap.getRegClass(I->getOperand(0).getReg())->getSize() == 10)
727 // Okay, this block uses an FP register. If the block has successors (ie,
728 // it's not an unwind/return), insert the FP_REG_KILL instruction.
729 if (BB->getBasicBlock()->getTerminator()->getNumSuccessors() &&
730 RequiresFPRegKill(BB->getBasicBlock())) {
731 BMI(BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
738 // canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
739 // the conditional branch instruction which is the only user of the cc
740 // instruction. This is the case if the conditional branch is the only user of
741 // the setcc, and if the setcc is in the same basic block as the conditional
742 // branch. We also don't handle long arguments below, so we reject them here as
745 static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
746 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
747 if (SCI->hasOneUse() && isa<BranchInst>(SCI->use_back()) &&
748 SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
749 const Type *Ty = SCI->getOperand(0)->getType();
750 if (Ty != Type::LongTy && Ty != Type::ULongTy)
756 // Return a fixed numbering for setcc instructions which does not depend on the
757 // order of the opcodes.
759 static unsigned getSetCCNumber(unsigned Opcode) {
761 default: assert(0 && "Unknown setcc instruction!");
762 case Instruction::SetEQ: return 0;
763 case Instruction::SetNE: return 1;
764 case Instruction::SetLT: return 2;
765 case Instruction::SetGE: return 3;
766 case Instruction::SetGT: return 4;
767 case Instruction::SetLE: return 5;
771 // LLVM -> X86 signed X86 unsigned
772 // ----- ---------- ------------
773 // seteq -> sete sete
774 // setne -> setne setne
775 // setlt -> setl setb
776 // setge -> setge setae
777 // setgt -> setg seta
778 // setle -> setle setbe
780 // sets // Used by comparison with 0 optimization
782 static const unsigned SetCCOpcodeTab[2][8] = {
783 { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
785 { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
786 X86::SETSr, X86::SETNSr },
789 // EmitComparison - This function emits a comparison of the two operands,
790 // returning the extended setcc code to use.
791 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
792 MachineBasicBlock *MBB,
793 MachineBasicBlock::iterator IP) {
794 // The arguments are already supposed to be of the same type.
795 const Type *CompTy = Op0->getType();
796 unsigned Class = getClassB(CompTy);
797 unsigned Op0r = getReg(Op0, MBB, IP);
799 // Special case handling of: cmp R, i
800 if (Class == cByte || Class == cShort || Class == cInt)
801 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
802 uint64_t Op1v = cast<ConstantInt>(CI)->getRawValue();
804 // Mask off any upper bits of the constant, if there are any...
805 Op1v &= (1ULL << (8 << Class)) - 1;
807 // If this is a comparison against zero, emit more efficient code. We
808 // can't handle unsigned comparisons against zero unless they are == or
809 // !=. These should have been strength reduced already anyway.
810 if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
811 static const unsigned TESTTab[] = {
812 X86::TESTrr8, X86::TESTrr16, X86::TESTrr32
814 BMI(MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
816 if (OpNum == 2) return 6; // Map jl -> js
817 if (OpNum == 3) return 7; // Map jg -> jns
821 static const unsigned CMPTab[] = {
822 X86::CMPri8, X86::CMPri16, X86::CMPri32
825 BMI(MBB, IP, CMPTab[Class], 2).addReg(Op0r).addZImm(Op1v);
829 // Special case handling of comparison against +/- 0.0
830 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op1))
831 if (CFP->isExactlyValue(+0.0) || CFP->isExactlyValue(-0.0)) {
832 BMI(MBB, IP, X86::FTST, 1).addReg(Op0r);
833 BMI(MBB, IP, X86::FNSTSWr8, 0);
834 BMI(MBB, IP, X86::SAHF, 1);
838 unsigned Op1r = getReg(Op1, MBB, IP);
840 default: assert(0 && "Unknown type class!");
841 // Emit: cmp <var1>, <var2> (do the comparison). We can
842 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
845 BMI(MBB, IP, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r);
848 BMI(MBB, IP, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r);
851 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
854 BMI(MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
855 BMI(MBB, IP, X86::FNSTSWr8, 0);
856 BMI(MBB, IP, X86::SAHF, 1);
860 if (OpNum < 2) { // seteq, setne
861 unsigned LoTmp = makeAnotherReg(Type::IntTy);
862 unsigned HiTmp = makeAnotherReg(Type::IntTy);
863 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
864 BMI(MBB, IP, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r);
865 BMI(MBB, IP, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
866 BMI(MBB, IP, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
867 break; // Allow the sete or setne to be generated from flags set by OR
869 // Emit a sequence of code which compares the high and low parts once
870 // each, then uses a conditional move to handle the overflow case. For
871 // example, a setlt for long would generate code like this:
873 // AL = lo(op1) < lo(op2) // Signedness depends on operands
874 // BL = hi(op1) < hi(op2) // Always unsigned comparison
875 // dest = hi(op1) == hi(op2) ? AL : BL;
878 // FIXME: This would be much better if we had hierarchical register
879 // classes! Until then, hardcode registers so that we can deal with their
880 // aliases (because we don't have conditional byte moves).
882 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
883 BMI(MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
884 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
885 BMI(MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
886 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
887 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
888 BMI(MBB, IP, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
889 // NOTE: visitSetCondInst knows that the value is dumped into the BL
890 // register at this point for long values...
898 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
899 /// register, then move it to wherever the result should be.
901 void ISel::visitSetCondInst(SetCondInst &I) {
902 if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
904 unsigned DestReg = getReg(I);
905 MachineBasicBlock::iterator MII = BB->end();
906 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
910 /// emitSetCCOperation - Common code shared between visitSetCondInst and
911 /// constant expression support.
912 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
913 MachineBasicBlock::iterator IP,
914 Value *Op0, Value *Op1, unsigned Opcode,
915 unsigned TargetReg) {
916 unsigned OpNum = getSetCCNumber(Opcode);
917 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
919 const Type *CompTy = Op0->getType();
920 unsigned CompClass = getClassB(CompTy);
921 bool isSigned = CompTy->isSigned() && CompClass != cFP;
923 if (CompClass != cLong || OpNum < 2) {
924 // Handle normal comparisons with a setcc instruction...
925 BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
927 // Handle long comparisons by copying the value which is already in BL into
928 // the register we want...
929 BMI(MBB, IP, X86::MOVrr8, 1, TargetReg).addReg(X86::BL);
936 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
937 /// operand, in the specified target register.
938 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
939 bool isUnsigned = VR.Ty->isUnsigned();
941 // Make sure we have the register number for this value...
942 unsigned Reg = VR.Val ? getReg(VR.Val) : VR.Reg;
944 switch (getClassB(VR.Ty)) {
946 // Extend value into target register (8->32)
948 BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(Reg);
950 BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(Reg);
953 // Extend value into target register (16->32)
955 BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(Reg);
957 BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(Reg);
960 // Move value into target register (32->32)
961 BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(Reg);
964 assert(0 && "Unpromotable operand class in promote32");
968 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
969 /// we have the following possibilities:
971 /// ret void: No return value, simply emit a 'ret' instruction
972 /// ret sbyte, ubyte : Extend value into EAX and return
973 /// ret short, ushort: Extend value into EAX and return
974 /// ret int, uint : Move value into EAX and return
975 /// ret pointer : Move value into EAX and return
976 /// ret long, ulong : Move value into EAX/EDX and return
977 /// ret float/double : Top of FP stack
979 void ISel::visitReturnInst(ReturnInst &I) {
980 if (I.getNumOperands() == 0) {
981 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
985 Value *RetVal = I.getOperand(0);
986 unsigned RetReg = getReg(RetVal);
987 switch (getClassB(RetVal->getType())) {
988 case cByte: // integral return values: extend or move into EAX and return
991 promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
992 // Declare that EAX is live on exit
993 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
995 case cFP: // Floats & Doubles: Return in ST(0)
996 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
997 // Declare that top-of-stack is live on exit
998 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
1001 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
1002 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
1003 // Declare that EAX & EDX are live on exit
1004 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
1008 visitInstruction(I);
1010 // Emit a 'ret' instruction
1011 BuildMI(BB, X86::RET, 0);
1014 // getBlockAfter - Return the basic block which occurs lexically after the
1016 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1017 Function::iterator I = BB; ++I; // Get iterator to next block
1018 return I != BB->getParent()->end() ? &*I : 0;
1021 /// visitBranchInst - Handle conditional and unconditional branches here. Note
1022 /// that since code layout is frozen at this point, that if we are trying to
1023 /// jump to a block that is the immediate successor of the current block, we can
1024 /// just make a fall-through (but we don't currently).
1026 void ISel::visitBranchInst(BranchInst &BI) {
1027 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1029 if (!BI.isConditional()) { // Unconditional branch?
1030 if (BI.getSuccessor(0) != NextBB)
1031 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
1035 // See if we can fold the setcc into the branch itself...
1036 SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
1038 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1039 // computed some other way...
1040 unsigned condReg = getReg(BI.getCondition());
1041 BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
1042 if (BI.getSuccessor(1) == NextBB) {
1043 if (BI.getSuccessor(0) != NextBB)
1044 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
1046 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
1048 if (BI.getSuccessor(0) != NextBB)
1049 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
1054 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1055 MachineBasicBlock::iterator MII = BB->end();
1056 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1058 const Type *CompTy = SCI->getOperand(0)->getType();
1059 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
1062 // LLVM -> X86 signed X86 unsigned
1063 // ----- ---------- ------------
1071 // js // Used by comparison with 0 optimization
1074 static const unsigned OpcodeTab[2][8] = {
1075 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
1076 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
1077 X86::JS, X86::JNS },
1080 if (BI.getSuccessor(0) != NextBB) {
1081 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
1082 if (BI.getSuccessor(1) != NextBB)
1083 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
1085 // Change to the inverse condition...
1086 if (BI.getSuccessor(1) != NextBB) {
1088 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
1094 /// doCall - This emits an abstract call instruction, setting up the arguments
1095 /// and the return value as appropriate. For the actual function call itself,
1096 /// it inserts the specified CallMI instruction into the stream.
1098 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1099 const std::vector<ValueRecord> &Args) {
1101 // Count how many bytes are to be pushed on the stack...
1102 unsigned NumBytes = 0;
1104 if (!Args.empty()) {
1105 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1106 switch (getClassB(Args[i].Ty)) {
1107 case cByte: case cShort: case cInt:
1108 NumBytes += 4; break;
1110 NumBytes += 8; break;
1112 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
1114 default: assert(0 && "Unknown class!");
1117 // Adjust the stack pointer for the new arguments...
1118 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes);
1120 // Arguments go on the stack in reverse order, as specified by the ABI.
1121 unsigned ArgOffset = 0;
1122 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1123 unsigned ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1124 switch (getClassB(Args[i].Ty)) {
1127 // Promote arg to 32 bits wide into a temporary register...
1128 unsigned R = makeAnotherReg(Type::UIntTy);
1129 promote32(R, Args[i]);
1130 addRegOffset(BuildMI(BB, X86::MOVmr32, 5),
1131 X86::ESP, ArgOffset).addReg(R);
1135 addRegOffset(BuildMI(BB, X86::MOVmr32, 5),
1136 X86::ESP, ArgOffset).addReg(ArgReg);
1139 addRegOffset(BuildMI(BB, X86::MOVmr32, 5),
1140 X86::ESP, ArgOffset).addReg(ArgReg);
1141 addRegOffset(BuildMI(BB, X86::MOVmr32, 5),
1142 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
1143 ArgOffset += 4; // 8 byte entry, not 4.
1147 if (Args[i].Ty == Type::FloatTy) {
1148 addRegOffset(BuildMI(BB, X86::FSTm32, 5),
1149 X86::ESP, ArgOffset).addReg(ArgReg);
1151 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
1152 addRegOffset(BuildMI(BB, X86::FSTm64, 5),
1153 X86::ESP, ArgOffset).addReg(ArgReg);
1154 ArgOffset += 4; // 8 byte entry, not 4.
1158 default: assert(0 && "Unknown class!");
1163 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(0);
1166 BB->push_back(CallMI);
1168 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes);
1170 // If there is a return value, scavenge the result from the location the call
1173 if (Ret.Ty != Type::VoidTy) {
1174 unsigned DestClass = getClassB(Ret.Ty);
1175 switch (DestClass) {
1179 // Integral results are in %eax, or the appropriate portion
1181 static const unsigned regRegMove[] = {
1182 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
1184 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
1185 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
1188 case cFP: // Floating-point return values live in %ST(0)
1189 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
1191 case cLong: // Long values are left in EDX:EAX
1192 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg).addReg(X86::EAX);
1193 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg+1).addReg(X86::EDX);
1195 default: assert(0 && "Unknown class!");
1201 /// visitCallInst - Push args on stack and do a procedure call instruction.
1202 void ISel::visitCallInst(CallInst &CI) {
1203 MachineInstr *TheCall;
1204 if (Function *F = CI.getCalledFunction()) {
1205 // Is it an intrinsic function call?
1206 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1207 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1211 // Emit a CALL instruction with PC-relative displacement.
1212 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
1213 } else { // Emit an indirect call...
1214 unsigned Reg = getReg(CI.getCalledValue());
1215 TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg);
1218 std::vector<ValueRecord> Args;
1219 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1220 Args.push_back(ValueRecord(CI.getOperand(i)));
1222 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1223 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1227 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1228 /// function, lowering any calls to unknown intrinsic functions into the
1229 /// equivalent LLVM code.
1230 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1231 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1232 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1233 if (CallInst *CI = dyn_cast<CallInst>(I++))
1234 if (Function *F = CI->getCalledFunction())
1235 switch (F->getIntrinsicID()) {
1236 case Intrinsic::not_intrinsic:
1237 case Intrinsic::va_start:
1238 case Intrinsic::va_copy:
1239 case Intrinsic::va_end:
1240 case Intrinsic::returnaddress:
1241 case Intrinsic::frameaddress:
1242 case Intrinsic::memcpy:
1243 case Intrinsic::memset:
1244 // We directly implement these intrinsics
1247 // All other intrinsic calls we must lower.
1248 Instruction *Before = CI->getPrev();
1249 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1250 if (Before) { // Move iterator to instruction after call
1259 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1260 unsigned TmpReg1, TmpReg2;
1262 case Intrinsic::va_start:
1263 // Get the address of the first vararg value...
1264 TmpReg1 = getReg(CI);
1265 addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
1268 case Intrinsic::va_copy:
1269 TmpReg1 = getReg(CI);
1270 TmpReg2 = getReg(CI.getOperand(1));
1271 BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2);
1273 case Intrinsic::va_end: return; // Noop on X86
1275 case Intrinsic::returnaddress:
1276 case Intrinsic::frameaddress:
1277 TmpReg1 = getReg(CI);
1278 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1279 if (ID == Intrinsic::returnaddress) {
1280 // Just load the return address
1281 addFrameReference(BuildMI(BB, X86::MOVrm32, 4, TmpReg1),
1282 ReturnAddressIndex);
1284 addFrameReference(BuildMI(BB, X86::LEAr32, 4, TmpReg1),
1285 ReturnAddressIndex, -4);
1288 // Values other than zero are not implemented yet.
1289 BuildMI(BB, X86::MOVri32, 1, TmpReg1).addZImm(0);
1293 case Intrinsic::memcpy: {
1294 assert(CI.getNumOperands() == 5 && "Illegal llvm.memcpy call!");
1296 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1297 Align = AlignC->getRawValue();
1298 if (Align == 0) Align = 1;
1301 // Turn the byte code into # iterations
1304 switch (Align & 3) {
1305 case 2: // WORD aligned
1306 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1307 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1309 CountReg = makeAnotherReg(Type::IntTy);
1310 unsigned ByteReg = getReg(CI.getOperand(3));
1311 BuildMI(BB, X86::SHRri32, 2, CountReg).addReg(ByteReg).addZImm(1);
1313 Opcode = X86::REP_MOVSW;
1315 case 0: // DWORD aligned
1316 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1317 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1319 CountReg = makeAnotherReg(Type::IntTy);
1320 unsigned ByteReg = getReg(CI.getOperand(3));
1321 BuildMI(BB, X86::SHRri32, 2, CountReg).addReg(ByteReg).addZImm(2);
1323 Opcode = X86::REP_MOVSD;
1325 default: // BYTE aligned
1326 CountReg = getReg(CI.getOperand(3));
1327 Opcode = X86::REP_MOVSB;
1331 // No matter what the alignment is, we put the source in ESI, the
1332 // destination in EDI, and the count in ECX.
1333 TmpReg1 = getReg(CI.getOperand(1));
1334 TmpReg2 = getReg(CI.getOperand(2));
1335 BuildMI(BB, X86::MOVrr32, 1, X86::ECX).addReg(CountReg);
1336 BuildMI(BB, X86::MOVrr32, 1, X86::EDI).addReg(TmpReg1);
1337 BuildMI(BB, X86::MOVrr32, 1, X86::ESI).addReg(TmpReg2);
1338 BuildMI(BB, Opcode, 0);
1341 case Intrinsic::memset: {
1342 assert(CI.getNumOperands() == 5 && "Illegal llvm.memset call!");
1344 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1345 Align = AlignC->getRawValue();
1346 if (Align == 0) Align = 1;
1349 // Turn the byte code into # iterations
1352 if (ConstantInt *ValC = dyn_cast<ConstantInt>(CI.getOperand(2))) {
1353 unsigned Val = ValC->getRawValue() & 255;
1355 // If the value is a constant, then we can potentially use larger copies.
1356 switch (Align & 3) {
1357 case 2: // WORD aligned
1358 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1359 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1361 CountReg = makeAnotherReg(Type::IntTy);
1362 unsigned ByteReg = getReg(CI.getOperand(3));
1363 BuildMI(BB, X86::SHRri32, 2, CountReg).addReg(ByteReg).addZImm(1);
1365 BuildMI(BB, X86::MOVri16, 1, X86::AX).addZImm((Val << 8) | Val);
1366 Opcode = X86::REP_STOSW;
1368 case 0: // DWORD aligned
1369 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1370 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1372 CountReg = makeAnotherReg(Type::IntTy);
1373 unsigned ByteReg = getReg(CI.getOperand(3));
1374 BuildMI(BB, X86::SHRri32, 2, CountReg).addReg(ByteReg).addZImm(2);
1376 Val = (Val << 8) | Val;
1377 BuildMI(BB, X86::MOVri32, 1, X86::EAX).addZImm((Val << 16) | Val);
1378 Opcode = X86::REP_STOSD;
1380 default: // BYTE aligned
1381 CountReg = getReg(CI.getOperand(3));
1382 BuildMI(BB, X86::MOVri8, 1, X86::AL).addZImm(Val);
1383 Opcode = X86::REP_STOSB;
1387 // If it's not a constant value we are storing, just fall back. We could
1388 // try to be clever to form 16 bit and 32 bit values, but we don't yet.
1389 unsigned ValReg = getReg(CI.getOperand(2));
1390 BuildMI(BB, X86::MOVrr8, 1, X86::AL).addReg(ValReg);
1391 CountReg = getReg(CI.getOperand(3));
1392 Opcode = X86::REP_STOSB;
1395 // No matter what the alignment is, we put the source in ESI, the
1396 // destination in EDI, and the count in ECX.
1397 TmpReg1 = getReg(CI.getOperand(1));
1398 //TmpReg2 = getReg(CI.getOperand(2));
1399 BuildMI(BB, X86::MOVrr32, 1, X86::ECX).addReg(CountReg);
1400 BuildMI(BB, X86::MOVrr32, 1, X86::EDI).addReg(TmpReg1);
1401 BuildMI(BB, Opcode, 0);
1405 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1410 /// visitSimpleBinary - Implement simple binary operators for integral types...
1411 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1413 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1414 unsigned DestReg = getReg(B);
1415 MachineBasicBlock::iterator MI = BB->end();
1416 emitSimpleBinaryOperation(BB, MI, B.getOperand(0), B.getOperand(1),
1417 OperatorClass, DestReg);
1420 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1421 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1424 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1425 /// and constant expression support.
1427 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1428 MachineBasicBlock::iterator IP,
1429 Value *Op0, Value *Op1,
1430 unsigned OperatorClass, unsigned DestReg) {
1431 unsigned Class = getClassB(Op0->getType());
1433 // sub 0, X -> neg X
1434 if (OperatorClass == 1 && Class != cLong)
1435 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0)) {
1436 if (CI->isNullValue()) {
1437 unsigned op1Reg = getReg(Op1, MBB, IP);
1439 default: assert(0 && "Unknown class for this function!");
1441 BMI(MBB, IP, X86::NEGr8, 1, DestReg).addReg(op1Reg);
1444 BMI(MBB, IP, X86::NEGr16, 1, DestReg).addReg(op1Reg);
1447 BMI(MBB, IP, X86::NEGr32, 1, DestReg).addReg(op1Reg);
1451 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
1452 if (CFP->isExactlyValue(-0.0)) {
1454 unsigned op1Reg = getReg(Op1, MBB, IP);
1455 BMI(MBB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg);
1459 if (!isa<ConstantInt>(Op1) || Class == cLong) {
1460 static const unsigned OpcodeTab[][4] = {
1461 // Arithmetic operators
1462 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
1463 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
1465 // Bitwise operators
1466 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
1467 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
1468 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
1471 bool isLong = false;
1472 if (Class == cLong) {
1474 Class = cInt; // Bottom 32 bits are handled just like ints
1477 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1478 assert(Opcode && "Floating point arguments to logical inst?");
1479 unsigned Op0r = getReg(Op0, MBB, IP);
1480 unsigned Op1r = getReg(Op1, MBB, IP);
1481 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1483 if (isLong) { // Handle the upper 32 bits of long values...
1484 static const unsigned TopTab[] = {
1485 X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
1487 BMI(MBB, IP, TopTab[OperatorClass], 2,
1488 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
1493 // Special case: op Reg, <const>
1494 ConstantInt *Op1C = cast<ConstantInt>(Op1);
1495 unsigned Op0r = getReg(Op0, MBB, IP);
1497 // xor X, -1 -> not X
1498 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1499 static unsigned const NOTTab[] = { X86::NOTr8, X86::NOTr16, X86::NOTr32 };
1500 BMI(MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
1504 // add X, -1 -> dec X
1505 if (OperatorClass == 0 && Op1C->isAllOnesValue()) {
1506 static unsigned const DECTab[] = { X86::DECr8, X86::DECr16, X86::DECr32 };
1507 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1511 // add X, 1 -> inc X
1512 if (OperatorClass == 0 && Op1C->equalsInt(1)) {
1513 static unsigned const DECTab[] = { X86::INCr8, X86::INCr16, X86::INCr32 };
1514 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1518 static const unsigned OpcodeTab[][3] = {
1519 // Arithmetic operators
1520 { X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
1521 { X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
1523 // Bitwise operators
1524 { X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
1525 { X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
1526 { X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
1529 assert(Class < 3 && "General code handles 64-bit integer types!");
1530 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1531 uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
1533 // Mask off any upper bits of the constant, if there are any...
1534 Op1v &= (1ULL << (8 << Class)) - 1;
1535 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addZImm(Op1v);
1538 /// doMultiply - Emit appropriate instructions to multiply together the
1539 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1540 /// result should be given as DestTy.
1542 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
1543 unsigned DestReg, const Type *DestTy,
1544 unsigned op0Reg, unsigned op1Reg) {
1545 unsigned Class = getClass(DestTy);
1547 case cFP: // Floating point multiply
1548 BMI(BB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1552 BMI(BB, MBBI, Class == cInt ? X86::IMULrr32 : X86::IMULrr16, 2, DestReg)
1553 .addReg(op0Reg).addReg(op1Reg);
1556 // Must use the MUL instruction, which forces use of AL...
1557 BMI(MBB, MBBI, X86::MOVrr8, 1, X86::AL).addReg(op0Reg);
1558 BMI(MBB, MBBI, X86::MULr8, 1).addReg(op1Reg);
1559 BMI(MBB, MBBI, X86::MOVrr8, 1, DestReg).addReg(X86::AL);
1562 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
1566 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1567 // returns zero when the input is not exactly a power of two.
1568 static unsigned ExactLog2(unsigned Val) {
1569 if (Val == 0) return 0;
1572 if (Val & 1) return 0;
1579 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
1580 MachineBasicBlock::iterator IP,
1581 unsigned DestReg, const Type *DestTy,
1582 unsigned op0Reg, unsigned ConstRHS) {
1583 unsigned Class = getClass(DestTy);
1585 // If the element size is exactly a power of 2, use a shift to get it.
1586 if (unsigned Shift = ExactLog2(ConstRHS)) {
1588 default: assert(0 && "Unknown class for this function!");
1590 BMI(MBB, IP, X86::SHLri32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1593 BMI(MBB, IP, X86::SHLri32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1596 BMI(MBB, IP, X86::SHLri32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1601 if (Class == cShort) {
1602 BMI(MBB, IP, X86::IMULrri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1604 } else if (Class == cInt) {
1605 BMI(MBB, IP, X86::IMULrri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1609 // Most general case, emit a normal multiply...
1610 static const unsigned MOVriTab[] = {
1611 X86::MOVri8, X86::MOVri16, X86::MOVri32
1614 unsigned TmpReg = makeAnotherReg(DestTy);
1615 BMI(MBB, IP, MOVriTab[Class], 1, TmpReg).addZImm(ConstRHS);
1617 // Emit a MUL to multiply the register holding the index by
1618 // elementSize, putting the result in OffsetReg.
1619 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
1622 /// visitMul - Multiplies are not simple binary operators because they must deal
1623 /// with the EAX register explicitly.
1625 void ISel::visitMul(BinaryOperator &I) {
1626 unsigned Op0Reg = getReg(I.getOperand(0));
1627 unsigned DestReg = getReg(I);
1629 // Simple scalar multiply?
1630 if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
1631 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1))) {
1632 unsigned Val = (unsigned)CI->getRawValue(); // Cannot be 64-bit constant
1633 MachineBasicBlock::iterator MBBI = BB->end();
1634 doMultiplyConst(BB, MBBI, DestReg, I.getType(), Op0Reg, Val);
1636 unsigned Op1Reg = getReg(I.getOperand(1));
1637 MachineBasicBlock::iterator MBBI = BB->end();
1638 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
1641 unsigned Op1Reg = getReg(I.getOperand(1));
1643 // Long value. We have to do things the hard way...
1644 // Multiply the two low parts... capturing carry into EDX
1645 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
1646 BuildMI(BB, X86::MULr32, 1).addReg(Op1Reg); // AL*BL
1648 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1649 BuildMI(BB, X86::MOVrr32, 1, DestReg).addReg(X86::EAX); // AL*BL
1650 BuildMI(BB, X86::MOVrr32, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32
1652 MachineBasicBlock::iterator MBBI = BB->end();
1653 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
1654 BMI(BB, MBBI, X86::IMULrr32, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
1656 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1657 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
1658 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1661 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1662 BMI(BB, MBBI, X86::IMULrr32, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
1664 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1665 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1670 /// visitDivRem - Handle division and remainder instructions... these
1671 /// instruction both require the same instructions to be generated, they just
1672 /// select the result from a different register. Note that both of these
1673 /// instructions work differently for signed and unsigned operands.
1675 void ISel::visitDivRem(BinaryOperator &I) {
1676 unsigned Op0Reg = getReg(I.getOperand(0));
1677 unsigned Op1Reg = getReg(I.getOperand(1));
1678 unsigned ResultReg = getReg(I);
1680 MachineBasicBlock::iterator IP = BB->end();
1681 emitDivRemOperation(BB, IP, Op0Reg, Op1Reg, I.getOpcode() == Instruction::Div,
1682 I.getType(), ResultReg);
1685 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1686 MachineBasicBlock::iterator IP,
1687 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
1688 const Type *Ty, unsigned ResultReg) {
1689 unsigned Class = getClass(Ty);
1691 case cFP: // Floating point divide
1693 BMI(BB, IP, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1694 } else { // Floating point remainder...
1695 MachineInstr *TheCall =
1696 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1697 std::vector<ValueRecord> Args;
1698 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1699 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1700 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1704 static const char *FnName[] =
1705 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1707 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
1708 MachineInstr *TheCall =
1709 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
1711 std::vector<ValueRecord> Args;
1712 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1713 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1714 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1717 case cByte: case cShort: case cInt:
1718 break; // Small integrals, handled below...
1719 default: assert(0 && "Unknown class!");
1722 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1723 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1724 static const unsigned SarOpcode[]={ X86::SARri8, X86::SARri16, X86::SARri32 };
1725 static const unsigned ClrOpcode[]={ X86::MOVri8, X86::MOVri16, X86::MOVri32 };
1726 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
1728 static const unsigned DivOpcode[][4] = {
1729 { X86::DIVr8 , X86::DIVr16 , X86::DIVr32 , 0 }, // Unsigned division
1730 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
1733 bool isSigned = Ty->isSigned();
1734 unsigned Reg = Regs[Class];
1735 unsigned ExtReg = ExtRegs[Class];
1737 // Put the first operand into one of the A registers...
1738 BMI(BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
1741 // Emit a sign extension instruction...
1742 unsigned ShiftResult = makeAnotherReg(Ty);
1743 BMI(BB, IP, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
1744 BMI(BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
1746 // If unsigned, emit a zeroing instruction... (reg = 0)
1747 BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addZImm(0);
1750 // Emit the appropriate divide or remainder instruction...
1751 BMI(BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
1753 // Figure out which register we want to pick the result out of...
1754 unsigned DestReg = isDiv ? Reg : ExtReg;
1756 // Put the result into the destination register...
1757 BMI(BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
1761 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1762 /// for constant immediate shift values, and for constant immediate
1763 /// shift values equal to 1. Even the general case is sort of special,
1764 /// because the shift amount has to be in CL, not just any old register.
1766 void ISel::visitShiftInst(ShiftInst &I) {
1767 MachineBasicBlock::iterator IP = BB->end ();
1768 emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1),
1769 I.getOpcode () == Instruction::Shl, I.getType (),
1773 /// emitShiftOperation - Common code shared between visitShiftInst and
1774 /// constant expression support.
1775 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
1776 MachineBasicBlock::iterator IP,
1777 Value *Op, Value *ShiftAmount, bool isLeftShift,
1778 const Type *ResultTy, unsigned DestReg) {
1779 unsigned SrcReg = getReg (Op, MBB, IP);
1780 bool isSigned = ResultTy->isSigned ();
1781 unsigned Class = getClass (ResultTy);
1783 static const unsigned ConstantOperand[][4] = {
1784 { X86::SHRri8, X86::SHRri16, X86::SHRri32, X86::SHRDrr32i8 }, // SHR
1785 { X86::SARri8, X86::SARri16, X86::SARri32, X86::SHRDrr32i8 }, // SAR
1786 { X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDrr32i8 }, // SHL
1787 { X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDrr32i8 }, // SAL = SHL
1790 static const unsigned NonConstantOperand[][4] = {
1791 { X86::SHRrCL8, X86::SHRrCL16, X86::SHRrCL32 }, // SHR
1792 { X86::SARrCL8, X86::SARrCL16, X86::SARrCL32 }, // SAR
1793 { X86::SHLrCL8, X86::SHLrCL16, X86::SHLrCL32 }, // SHL
1794 { X86::SHLrCL8, X86::SHLrCL16, X86::SHLrCL32 }, // SAL = SHL
1797 // Longs, as usual, are handled specially...
1798 if (Class == cLong) {
1799 // If we have a constant shift, we can generate much more efficient code
1800 // than otherwise...
1802 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
1803 unsigned Amount = CUI->getValue();
1805 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1807 BMI(MBB, IP, Opc[3], 3,
1808 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1809 BMI(MBB, IP, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1811 BMI(MBB, IP, Opc[3], 3,
1812 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1813 BMI(MBB, IP, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1815 } else { // Shifting more than 32 bits
1818 BMI(MBB, IP, X86::SHLri32, 2,
1819 DestReg + 1).addReg(SrcReg).addZImm(Amount);
1820 BMI(MBB, IP, X86::MOVri32, 1,
1821 DestReg).addZImm(0);
1823 unsigned Opcode = isSigned ? X86::SARri32 : X86::SHRri32;
1824 BMI(MBB, IP, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1825 BMI(MBB, IP, X86::MOVri32, 1, DestReg+1).addZImm(0);
1829 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1831 if (!isLeftShift && isSigned) {
1832 // If this is a SHR of a Long, then we need to do funny sign extension
1833 // stuff. TmpReg gets the value to use as the high-part if we are
1834 // shifting more than 32 bits.
1835 BMI(MBB, IP, X86::SARri32, 2, TmpReg).addReg(SrcReg).addZImm(31);
1837 // Other shifts use a fixed zero value if the shift is more than 32
1839 BMI(MBB, IP, X86::MOVri32, 1, TmpReg).addZImm(0);
1842 // Initialize CL with the shift amount...
1843 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
1844 BMI(MBB, IP, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmountReg);
1846 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
1847 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
1849 // TmpReg2 = shld inHi, inLo
1850 BMI(MBB, IP, X86::SHLDrrCL32,2,TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
1851 // TmpReg3 = shl inLo, CL
1852 BMI(MBB, IP, X86::SHLrCL32, 1, TmpReg3).addReg(SrcReg);
1854 // Set the flags to indicate whether the shift was by more than 32 bits.
1855 BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1857 // DestHi = (>32) ? TmpReg3 : TmpReg2;
1858 BMI(MBB, IP, X86::CMOVNErr32, 2,
1859 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
1860 // DestLo = (>32) ? TmpReg : TmpReg3;
1861 BMI(MBB, IP, X86::CMOVNErr32, 2,
1862 DestReg).addReg(TmpReg3).addReg(TmpReg);
1864 // TmpReg2 = shrd inLo, inHi
1865 BMI(MBB, IP, X86::SHRDrrCL32,2,TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
1866 // TmpReg3 = s[ah]r inHi, CL
1867 BMI(MBB, IP, isSigned ? X86::SARrCL32 : X86::SHRrCL32, 1, TmpReg3)
1870 // Set the flags to indicate whether the shift was by more than 32 bits.
1871 BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1873 // DestLo = (>32) ? TmpReg3 : TmpReg2;
1874 BMI(MBB, IP, X86::CMOVNErr32, 2,
1875 DestReg).addReg(TmpReg2).addReg(TmpReg3);
1877 // DestHi = (>32) ? TmpReg : TmpReg3;
1878 BMI(MBB, IP, X86::CMOVNErr32, 2,
1879 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
1885 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
1886 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
1887 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
1889 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1890 BMI(MBB, IP, Opc[Class], 2,
1891 DestReg).addReg(SrcReg).addZImm(CUI->getValue());
1892 } else { // The shift amount is non-constant.
1893 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
1894 BMI(MBB, IP, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmountReg);
1896 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
1897 BMI(MBB, IP, Opc[Class], 1, DestReg).addReg(SrcReg);
1902 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
1903 /// instruction. The load and store instructions are the only place where we
1904 /// need to worry about the memory layout of the target machine.
1906 void ISel::visitLoadInst(LoadInst &I) {
1907 unsigned DestReg = getReg(I);
1908 unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
1909 Value *Addr = I.getOperand(0);
1910 if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Addr)) {
1911 if (isGEPFoldable(BB, GEP->getOperand(0), GEP->op_begin()+1, GEP->op_end(),
1912 BaseReg, Scale, IndexReg, Disp))
1913 Addr = 0; // Address is consumed!
1914 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Addr)) {
1915 if (CE->getOpcode() == Instruction::GetElementPtr)
1916 if (isGEPFoldable(BB, CE->getOperand(0), CE->op_begin()+1, CE->op_end(),
1917 BaseReg, Scale, IndexReg, Disp))
1922 // If it's not foldable, reset addr mode.
1923 BaseReg = getReg(Addr);
1924 Scale = 1; IndexReg = 0; Disp = 0;
1927 unsigned Class = getClassB(I.getType());
1928 if (Class == cLong) {
1929 addFullAddress(BuildMI(BB, X86::MOVrm32, 4, DestReg),
1930 BaseReg, Scale, IndexReg, Disp);
1931 addFullAddress(BuildMI(BB, X86::MOVrm32, 4, DestReg+1),
1932 BaseReg, Scale, IndexReg, Disp+4);
1936 static const unsigned Opcodes[] = {
1937 X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FLDm32
1939 unsigned Opcode = Opcodes[Class];
1940 if (I.getType() == Type::DoubleTy) Opcode = X86::FLDm64;
1941 addFullAddress(BuildMI(BB, Opcode, 4, DestReg),
1942 BaseReg, Scale, IndexReg, Disp);
1945 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
1948 void ISel::visitStoreInst(StoreInst &I) {
1949 unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
1950 Value *Addr = I.getOperand(1);
1951 if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Addr)) {
1952 if (isGEPFoldable(BB, GEP->getOperand(0), GEP->op_begin()+1, GEP->op_end(),
1953 BaseReg, Scale, IndexReg, Disp))
1954 Addr = 0; // Address is consumed!
1955 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Addr)) {
1956 if (CE->getOpcode() == Instruction::GetElementPtr)
1957 if (isGEPFoldable(BB, CE->getOperand(0), CE->op_begin()+1, CE->op_end(),
1958 BaseReg, Scale, IndexReg, Disp))
1963 // If it's not foldable, reset addr mode.
1964 BaseReg = getReg(Addr);
1965 Scale = 1; IndexReg = 0; Disp = 0;
1968 const Type *ValTy = I.getOperand(0)->getType();
1969 unsigned Class = getClassB(ValTy);
1971 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(0))) {
1972 uint64_t Val = CI->getRawValue();
1973 if (Class == cLong) {
1974 addFullAddress(BuildMI(BB, X86::MOVmi32, 5),
1975 BaseReg, Scale, IndexReg, Disp).addZImm(Val & ~0U);
1976 addFullAddress(BuildMI(BB, X86::MOVmi32, 5),
1977 BaseReg, Scale, IndexReg, Disp+4).addZImm(Val>>32);
1979 static const unsigned Opcodes[] = {
1980 X86::MOVmi8, X86::MOVmi16, X86::MOVmi32
1982 unsigned Opcode = Opcodes[Class];
1983 addFullAddress(BuildMI(BB, Opcode, 5),
1984 BaseReg, Scale, IndexReg, Disp).addZImm(Val);
1986 } else if (ConstantBool *CB = dyn_cast<ConstantBool>(I.getOperand(0))) {
1987 addFullAddress(BuildMI(BB, X86::MOVmi8, 5),
1988 BaseReg, Scale, IndexReg, Disp).addZImm(CB->getValue());
1990 if (Class == cLong) {
1991 unsigned ValReg = getReg(I.getOperand(0));
1992 addFullAddress(BuildMI(BB, X86::MOVmr32, 5),
1993 BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
1994 addFullAddress(BuildMI(BB, X86::MOVmr32, 5),
1995 BaseReg, Scale, IndexReg, Disp+4).addReg(ValReg+1);
1997 unsigned ValReg = getReg(I.getOperand(0));
1998 static const unsigned Opcodes[] = {
1999 X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FSTm32
2001 unsigned Opcode = Opcodes[Class];
2002 if (ValTy == Type::DoubleTy) Opcode = X86::FSTm64;
2003 addFullAddress(BuildMI(BB, Opcode, 1+4),
2004 BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
2010 /// visitCastInst - Here we have various kinds of copying with or without
2011 /// sign extension going on.
2012 void ISel::visitCastInst(CastInst &CI) {
2013 Value *Op = CI.getOperand(0);
2014 // If this is a cast from a 32-bit integer to a Long type, and the only uses
2015 // of the case are GEP instructions, then the cast does not need to be
2016 // generated explicitly, it will be folded into the GEP.
2017 if (CI.getType() == Type::LongTy &&
2018 (Op->getType() == Type::IntTy || Op->getType() == Type::UIntTy)) {
2019 bool AllUsesAreGEPs = true;
2020 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
2021 if (!isa<GetElementPtrInst>(*I)) {
2022 AllUsesAreGEPs = false;
2026 // No need to codegen this cast if all users are getelementptr instrs...
2027 if (AllUsesAreGEPs) return;
2030 unsigned DestReg = getReg(CI);
2031 MachineBasicBlock::iterator MI = BB->end();
2032 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
2035 /// emitCastOperation - Common code shared between visitCastInst and
2036 /// constant expression cast support.
2037 void ISel::emitCastOperation(MachineBasicBlock *BB,
2038 MachineBasicBlock::iterator IP,
2039 Value *Src, const Type *DestTy,
2041 unsigned SrcReg = getReg(Src, BB, IP);
2042 const Type *SrcTy = Src->getType();
2043 unsigned SrcClass = getClassB(SrcTy);
2044 unsigned DestClass = getClassB(DestTy);
2046 // Implement casts to bool by using compare on the operand followed by set if
2047 // not zero on the result.
2048 if (DestTy == Type::BoolTy) {
2051 BMI(BB, IP, X86::TESTrr8, 2).addReg(SrcReg).addReg(SrcReg);
2054 BMI(BB, IP, X86::TESTrr16, 2).addReg(SrcReg).addReg(SrcReg);
2057 BMI(BB, IP, X86::TESTrr32, 2).addReg(SrcReg).addReg(SrcReg);
2060 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2061 BMI(BB, IP, X86::ORrr32, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
2065 BMI(BB, IP, X86::FTST, 1).addReg(SrcReg);
2066 BMI(BB, IP, X86::FNSTSWr8, 0);
2067 BMI(BB, IP, X86::SAHF, 1);
2071 // If the zero flag is not set, then the value is true, set the byte to
2073 BMI(BB, IP, X86::SETNEr, 1, DestReg);
2077 static const unsigned RegRegMove[] = {
2078 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV, X86::MOVrr32
2081 // Implement casts between values of the same type class (as determined by
2082 // getClass) by using a register-to-register move.
2083 if (SrcClass == DestClass) {
2084 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
2085 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
2086 } else if (SrcClass == cFP) {
2087 if (SrcTy == Type::FloatTy) { // double -> float
2088 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
2089 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
2090 } else { // float -> double
2091 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
2092 "Unknown cFP member!");
2093 // Truncate from double to float by storing to memory as short, then
2095 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
2096 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
2097 addFrameReference(BMI(BB, IP, X86::FSTm32, 5), FrameIdx).addReg(SrcReg);
2098 addFrameReference(BMI(BB, IP, X86::FLDm32, 5, DestReg), FrameIdx);
2100 } else if (SrcClass == cLong) {
2101 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
2102 BMI(BB, IP, X86::MOVrr32, 1, DestReg+1).addReg(SrcReg+1);
2104 assert(0 && "Cannot handle this type of cast instruction!");
2110 // Handle cast of SMALLER int to LARGER int using a move with sign extension
2111 // or zero extension, depending on whether the source type was signed.
2112 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
2113 SrcClass < DestClass) {
2114 bool isLong = DestClass == cLong;
2115 if (isLong) DestClass = cInt;
2117 static const unsigned Opc[][4] = {
2118 { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, X86::MOVrr32 }, // s
2119 { X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16, X86::MOVrr32 } // u
2122 bool isUnsigned = SrcTy->isUnsigned();
2123 BMI(BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
2124 DestReg).addReg(SrcReg);
2126 if (isLong) { // Handle upper 32 bits as appropriate...
2127 if (isUnsigned) // Zero out top bits...
2128 BMI(BB, IP, X86::MOVri32, 1, DestReg+1).addZImm(0);
2129 else // Sign extend bottom half...
2130 BMI(BB, IP, X86::SARri32, 2, DestReg+1).addReg(DestReg).addZImm(31);
2135 // Special case long -> int ...
2136 if (SrcClass == cLong && DestClass == cInt) {
2137 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
2141 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
2142 // move out of AX or AL.
2143 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
2144 && SrcClass > DestClass) {
2145 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
2146 BMI(BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
2147 BMI(BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
2151 // Handle casts from integer to floating point now...
2152 if (DestClass == cFP) {
2153 // Promote the integer to a type supported by FLD. We do this because there
2154 // are no unsigned FLD instructions, so we must promote an unsigned value to
2155 // a larger signed value, then use FLD on the larger value.
2157 const Type *PromoteType = 0;
2158 unsigned PromoteOpcode;
2159 unsigned RealDestReg = DestReg;
2160 switch (SrcTy->getPrimitiveID()) {
2161 case Type::BoolTyID:
2162 case Type::SByteTyID:
2163 // We don't have the facilities for directly loading byte sized data from
2164 // memory (even signed). Promote it to 16 bits.
2165 PromoteType = Type::ShortTy;
2166 PromoteOpcode = X86::MOVSXr16r8;
2168 case Type::UByteTyID:
2169 PromoteType = Type::ShortTy;
2170 PromoteOpcode = X86::MOVZXr16r8;
2172 case Type::UShortTyID:
2173 PromoteType = Type::IntTy;
2174 PromoteOpcode = X86::MOVZXr32r16;
2176 case Type::UIntTyID: {
2177 // Make a 64 bit temporary... and zero out the top of it...
2178 unsigned TmpReg = makeAnotherReg(Type::LongTy);
2179 BMI(BB, IP, X86::MOVrr32, 1, TmpReg).addReg(SrcReg);
2180 BMI(BB, IP, X86::MOVri32, 1, TmpReg+1).addZImm(0);
2181 SrcTy = Type::LongTy;
2186 case Type::ULongTyID:
2187 // Don't fild into the read destination.
2188 DestReg = makeAnotherReg(Type::DoubleTy);
2190 default: // No promotion needed...
2195 unsigned TmpReg = makeAnotherReg(PromoteType);
2196 unsigned Opc = SrcTy->isSigned() ? X86::MOVSXr16r8 : X86::MOVZXr16r8;
2197 BMI(BB, IP, Opc, 1, TmpReg).addReg(SrcReg);
2198 SrcTy = PromoteType;
2199 SrcClass = getClass(PromoteType);
2203 // Spill the integer to memory and reload it from there...
2205 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
2207 if (SrcClass == cLong) {
2208 addFrameReference(BMI(BB, IP, X86::MOVmr32, 5), FrameIdx).addReg(SrcReg);
2209 addFrameReference(BMI(BB, IP, X86::MOVmr32, 5),
2210 FrameIdx, 4).addReg(SrcReg+1);
2212 static const unsigned Op1[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
2213 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
2216 static const unsigned Op2[] =
2217 { 0/*byte*/, X86::FILDm16, X86::FILDm32, 0/*FP*/, X86::FILDm64 };
2218 addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
2220 // We need special handling for unsigned 64-bit integer sources. If the
2221 // input number has the "sign bit" set, then we loaded it incorrectly as a
2222 // negative 64-bit number. In this case, add an offset value.
2223 if (SrcTy == Type::ULongTy) {
2224 // Emit a test instruction to see if the dynamic input value was signed.
2225 BMI(BB, IP, X86::TESTrr32, 2).addReg(SrcReg+1).addReg(SrcReg+1);
2227 // If the sign bit is set, get a pointer to an offset, otherwise get a
2228 // pointer to a zero.
2229 MachineConstantPool *CP = F->getConstantPool();
2230 unsigned Zero = makeAnotherReg(Type::IntTy);
2231 Constant *Null = Constant::getNullValue(Type::UIntTy);
2232 addConstantPoolReference(BMI(BB, IP, X86::LEAr32, 5, Zero),
2233 CP->getConstantPoolIndex(Null));
2234 unsigned Offset = makeAnotherReg(Type::IntTy);
2235 Constant *OffsetCst = ConstantUInt::get(Type::UIntTy, 0x5f800000);
2237 addConstantPoolReference(BMI(BB, IP, X86::LEAr32, 5, Offset),
2238 CP->getConstantPoolIndex(OffsetCst));
2239 unsigned Addr = makeAnotherReg(Type::IntTy);
2240 BMI(BB, IP, X86::CMOVSrr32, 2, Addr).addReg(Zero).addReg(Offset);
2242 // Load the constant for an add. FIXME: this could make an 'fadd' that
2243 // reads directly from memory, but we don't support these yet.
2244 unsigned ConstReg = makeAnotherReg(Type::DoubleTy);
2245 addDirectMem(BMI(BB, IP, X86::FLDm32, 4, ConstReg), Addr);
2247 BMI(BB, IP, X86::FpADD, 2, RealDestReg).addReg(ConstReg).addReg(DestReg);
2253 // Handle casts from floating point to integer now...
2254 if (SrcClass == cFP) {
2255 // Change the floating point control register to use "round towards zero"
2256 // mode when truncating to an integer value.
2258 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
2259 addFrameReference(BMI(BB, IP, X86::FNSTCWm16, 4), CWFrameIdx);
2261 // Load the old value of the high byte of the control word...
2262 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
2263 addFrameReference(BMI(BB, IP, X86::MOVrm8, 4, HighPartOfCW), CWFrameIdx, 1);
2265 // Set the high part to be round to zero...
2266 addFrameReference(BMI(BB, IP, X86::MOVmi8, 5), CWFrameIdx, 1).addZImm(12);
2268 // Reload the modified control word now...
2269 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
2271 // Restore the memory image of control word to original value
2272 addFrameReference(BMI(BB, IP, X86::MOVmr8, 5),
2273 CWFrameIdx, 1).addReg(HighPartOfCW);
2275 // We don't have the facilities for directly storing byte sized data to
2276 // memory. Promote it to 16 bits. We also must promote unsigned values to
2277 // larger classes because we only have signed FP stores.
2278 unsigned StoreClass = DestClass;
2279 const Type *StoreTy = DestTy;
2280 if (StoreClass == cByte || DestTy->isUnsigned())
2281 switch (StoreClass) {
2282 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
2283 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
2284 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
2285 // The following treatment of cLong may not be perfectly right,
2286 // but it survives chains of casts of the form
2287 // double->ulong->double.
2288 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
2289 default: assert(0 && "Unknown store class!");
2292 // Spill the integer to memory and reload it from there...
2294 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
2296 static const unsigned Op1[] =
2297 { 0, X86::FISTm16, X86::FISTm32, 0, X86::FISTPm64 };
2298 addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg);
2300 if (DestClass == cLong) {
2301 addFrameReference(BMI(BB, IP, X86::MOVrm32, 4, DestReg), FrameIdx);
2302 addFrameReference(BMI(BB, IP, X86::MOVrm32, 4, DestReg+1), FrameIdx, 4);
2304 static const unsigned Op2[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
2305 addFrameReference(BMI(BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
2308 // Reload the original control word now...
2309 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
2313 // Anything we haven't handled already, we can't (yet) handle at all.
2314 assert(0 && "Unhandled cast instruction!");
2318 /// visitVANextInst - Implement the va_next instruction...
2320 void ISel::visitVANextInst(VANextInst &I) {
2321 unsigned VAList = getReg(I.getOperand(0));
2322 unsigned DestReg = getReg(I);
2325 switch (I.getArgType()->getPrimitiveID()) {
2328 assert(0 && "Error: bad type for va_next instruction!");
2330 case Type::PointerTyID:
2331 case Type::UIntTyID:
2335 case Type::ULongTyID:
2336 case Type::LongTyID:
2337 case Type::DoubleTyID:
2342 // Increment the VAList pointer...
2343 BuildMI(BB, X86::ADDri32, 2, DestReg).addReg(VAList).addZImm(Size);
2346 void ISel::visitVAArgInst(VAArgInst &I) {
2347 unsigned VAList = getReg(I.getOperand(0));
2348 unsigned DestReg = getReg(I);
2350 switch (I.getType()->getPrimitiveID()) {
2353 assert(0 && "Error: bad type for va_next instruction!");
2355 case Type::PointerTyID:
2356 case Type::UIntTyID:
2358 addDirectMem(BuildMI(BB, X86::MOVrm32, 4, DestReg), VAList);
2360 case Type::ULongTyID:
2361 case Type::LongTyID:
2362 addDirectMem(BuildMI(BB, X86::MOVrm32, 4, DestReg), VAList);
2363 addRegOffset(BuildMI(BB, X86::MOVrm32, 4, DestReg+1), VAList, 4);
2365 case Type::DoubleTyID:
2366 addDirectMem(BuildMI(BB, X86::FLDm64, 4, DestReg), VAList);
2372 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
2373 // If this GEP instruction will be folded into all of its users, we don't need
2374 // to explicitly calculate it!
2375 unsigned A, B, C, D;
2376 if (isGEPFoldable(0, I.getOperand(0), I.op_begin()+1, I.op_end(), A,B,C,D)) {
2377 // Check all of the users of the instruction to see if they are loads and
2379 bool AllWillFold = true;
2380 for (Value::use_iterator UI = I.use_begin(), E = I.use_end(); UI != E; ++UI)
2381 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Load)
2382 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Store ||
2383 cast<Instruction>(*UI)->getOperand(0) == &I) {
2384 AllWillFold = false;
2388 // If the instruction is foldable, and will be folded into all users, don't
2390 if (AllWillFold) return;
2393 unsigned outputReg = getReg(I);
2394 emitGEPOperation(BB, BB->end(), I.getOperand(0),
2395 I.op_begin()+1, I.op_end(), outputReg);
2398 /// getGEPIndex - Inspect the getelementptr operands specified with GEPOps and
2399 /// GEPTypes (the derived types being stepped through at each level). On return
2400 /// from this function, if some indexes of the instruction are representable as
2401 /// an X86 lea instruction, the machine operands are put into the Ops
2402 /// instruction and the consumed indexes are poped from the GEPOps/GEPTypes
2403 /// lists. Otherwise, GEPOps.size() is returned. If this returns a an
2404 /// addressing mode that only partially consumes the input, the BaseReg input of
2405 /// the addressing mode must be left free.
2407 /// Note that there is one fewer entry in GEPTypes than there is in GEPOps.
2409 void ISel::getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
2410 std::vector<Value*> &GEPOps,
2411 std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
2412 unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
2413 const TargetData &TD = TM.getTargetData();
2415 // Clear out the state we are working with...
2416 BaseReg = 0; // No base register
2417 Scale = 1; // Unit scale
2418 IndexReg = 0; // No index register
2419 Disp = 0; // No displacement
2421 // While there are GEP indexes that can be folded into the current address,
2422 // keep processing them.
2423 while (!GEPTypes.empty()) {
2424 if (const StructType *StTy = dyn_cast<StructType>(GEPTypes.back())) {
2425 // It's a struct access. CUI is the index into the structure,
2426 // which names the field. This index must have unsigned type.
2427 const ConstantUInt *CUI = cast<ConstantUInt>(GEPOps.back());
2429 // Use the TargetData structure to pick out what the layout of the
2430 // structure is in memory. Since the structure index must be constant, we
2431 // can get its value and use it to find the right byte offset from the
2432 // StructLayout class's list of structure member offsets.
2433 Disp += TD.getStructLayout(StTy)->MemberOffsets[CUI->getValue()];
2434 GEPOps.pop_back(); // Consume a GEP operand
2435 GEPTypes.pop_back();
2437 // It's an array or pointer access: [ArraySize x ElementType].
2438 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
2439 Value *idx = GEPOps.back();
2441 // idx is the index into the array. Unlike with structure
2442 // indices, we may not know its actual value at code-generation
2444 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
2446 // If idx is a constant, fold it into the offset.
2447 unsigned TypeSize = TD.getTypeSize(SqTy->getElementType());
2448 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
2449 Disp += TypeSize*CSI->getValue();
2451 // If the index reg is already taken, we can't handle this index.
2452 if (IndexReg) return;
2454 // If this is a size that we can handle, then add the index as
2456 case 1: case 2: case 4: case 8:
2457 // These are all acceptable scales on X86.
2461 // Otherwise, we can't handle this scale
2465 if (CastInst *CI = dyn_cast<CastInst>(idx))
2466 if (CI->getOperand(0)->getType() == Type::IntTy ||
2467 CI->getOperand(0)->getType() == Type::UIntTy)
2468 idx = CI->getOperand(0);
2470 IndexReg = MBB ? getReg(idx, MBB, IP) : 1;
2473 GEPOps.pop_back(); // Consume a GEP operand
2474 GEPTypes.pop_back();
2478 // GEPTypes is empty, which means we have a single operand left. See if we
2479 // can set it as the base register.
2481 // FIXME: When addressing modes are more powerful/correct, we could load
2482 // global addresses directly as 32-bit immediates.
2483 assert(BaseReg == 0);
2484 BaseReg = MBB ? getReg(GEPOps[0], MBB, IP) : 1;
2485 GEPOps.pop_back(); // Consume the last GEP operand
2489 /// isGEPFoldable - Return true if the specified GEP can be completely
2490 /// folded into the addressing mode of a load/store or lea instruction.
2491 bool ISel::isGEPFoldable(MachineBasicBlock *MBB,
2492 Value *Src, User::op_iterator IdxBegin,
2493 User::op_iterator IdxEnd, unsigned &BaseReg,
2494 unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
2495 if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
2496 Src = CPR->getValue();
2498 std::vector<Value*> GEPOps;
2499 GEPOps.resize(IdxEnd-IdxBegin+1);
2501 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
2503 std::vector<const Type*> GEPTypes;
2504 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
2505 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
2507 MachineBasicBlock::iterator IP;
2508 if (MBB) IP = MBB->end();
2509 getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
2511 // We can fold it away iff the getGEPIndex call eliminated all operands.
2512 return GEPOps.empty();
2515 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
2516 MachineBasicBlock::iterator IP,
2517 Value *Src, User::op_iterator IdxBegin,
2518 User::op_iterator IdxEnd, unsigned TargetReg) {
2519 const TargetData &TD = TM.getTargetData();
2520 if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
2521 Src = CPR->getValue();
2523 std::vector<Value*> GEPOps;
2524 GEPOps.resize(IdxEnd-IdxBegin+1);
2526 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
2528 std::vector<const Type*> GEPTypes;
2529 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
2530 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
2532 // Keep emitting instructions until we consume the entire GEP instruction.
2533 while (!GEPOps.empty()) {
2534 unsigned OldSize = GEPOps.size();
2535 unsigned BaseReg, Scale, IndexReg, Disp;
2536 getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
2538 if (GEPOps.size() != OldSize) {
2539 // getGEPIndex consumed some of the input. Build an LEA instruction here.
2540 unsigned NextTarget = 0;
2541 if (!GEPOps.empty()) {
2542 assert(BaseReg == 0 &&
2543 "getGEPIndex should have left the base register open for chaining!");
2544 NextTarget = BaseReg = makeAnotherReg(Type::UIntTy);
2547 if (IndexReg == 0 && Disp == 0)
2548 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
2550 addFullAddress(BMI(MBB, IP, X86::LEAr32, 5, TargetReg),
2551 BaseReg, Scale, IndexReg, Disp);
2553 TargetReg = NextTarget;
2554 } else if (GEPTypes.empty()) {
2555 // The getGEPIndex operation didn't want to build an LEA. Check to see if
2556 // all operands are consumed but the base pointer. If so, just load it
2557 // into the register.
2558 if (GlobalValue *GV = dyn_cast<GlobalValue>(GEPOps[0])) {
2559 BMI(MBB, IP, X86::MOVri32, 1, TargetReg).addGlobalAddress(GV);
2561 unsigned BaseReg = getReg(GEPOps[0], MBB, IP);
2562 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
2564 break; // we are now done
2567 // It's an array or pointer access: [ArraySize x ElementType].
2568 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
2569 Value *idx = GEPOps.back();
2570 GEPOps.pop_back(); // Consume a GEP operand
2571 GEPTypes.pop_back();
2573 // idx is the index into the array. Unlike with structure
2574 // indices, we may not know its actual value at code-generation
2576 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
2578 // Most GEP instructions use a [cast (int/uint) to LongTy] as their
2579 // operand on X86. Handle this case directly now...
2580 if (CastInst *CI = dyn_cast<CastInst>(idx))
2581 if (CI->getOperand(0)->getType() == Type::IntTy ||
2582 CI->getOperand(0)->getType() == Type::UIntTy)
2583 idx = CI->getOperand(0);
2585 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
2586 // must find the size of the pointed-to type (Not coincidentally, the next
2587 // type is the type of the elements in the array).
2588 const Type *ElTy = SqTy->getElementType();
2589 unsigned elementSize = TD.getTypeSize(ElTy);
2591 // If idxReg is a constant, we don't need to perform the multiply!
2592 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
2593 if (!CSI->isNullValue()) {
2594 unsigned Offset = elementSize*CSI->getValue();
2595 unsigned Reg = makeAnotherReg(Type::UIntTy);
2596 BMI(MBB, IP, X86::ADDri32, 2, TargetReg).addReg(Reg).addZImm(Offset);
2597 --IP; // Insert the next instruction before this one.
2598 TargetReg = Reg; // Codegen the rest of the GEP into this
2600 } else if (elementSize == 1) {
2601 // If the element size is 1, we don't have to multiply, just add
2602 unsigned idxReg = getReg(idx, MBB, IP);
2603 unsigned Reg = makeAnotherReg(Type::UIntTy);
2604 BMI(MBB, IP, X86::ADDrr32, 2, TargetReg).addReg(Reg).addReg(idxReg);
2605 --IP; // Insert the next instruction before this one.
2606 TargetReg = Reg; // Codegen the rest of the GEP into this
2608 unsigned idxReg = getReg(idx, MBB, IP);
2609 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
2611 // Make sure we can back the iterator up to point to the first
2612 // instruction emitted.
2613 MachineBasicBlock::iterator BeforeIt = IP;
2614 if (IP == MBB->begin())
2615 BeforeIt = MBB->end();
2618 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
2620 // Emit an ADD to add OffsetReg to the basePtr.
2621 unsigned Reg = makeAnotherReg(Type::UIntTy);
2622 BMI(MBB, IP, X86::ADDrr32, 2, TargetReg).addReg(Reg).addReg(OffsetReg);
2624 // Step to the first instruction of the multiply.
2625 if (BeforeIt == MBB->end())
2630 TargetReg = Reg; // Codegen the rest of the GEP into this
2637 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2638 /// frame manager, otherwise do it the hard way.
2640 void ISel::visitAllocaInst(AllocaInst &I) {
2641 // Find the data size of the alloca inst's getAllocatedType.
2642 const Type *Ty = I.getAllocatedType();
2643 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2645 // If this is a fixed size alloca in the entry block for the function,
2646 // statically stack allocate the space.
2648 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
2649 if (I.getParent() == I.getParent()->getParent()->begin()) {
2650 TySize *= CUI->getValue(); // Get total allocated size...
2651 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
2653 // Create a new stack object using the frame manager...
2654 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
2655 addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx);
2660 // Create a register to hold the temporary result of multiplying the type size
2661 // constant by the variable amount.
2662 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2663 unsigned SrcReg1 = getReg(I.getArraySize());
2665 // TotalSizeReg = mul <numelements>, <TypeSize>
2666 MachineBasicBlock::iterator MBBI = BB->end();
2667 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
2669 // AddedSize = add <TotalSizeReg>, 15
2670 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2671 BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15);
2673 // AlignedSize = and <AddedSize>, ~15
2674 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2675 BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15);
2677 // Subtract size from stack pointer, thereby allocating some space.
2678 BuildMI(BB, X86::SUBrr32, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
2680 // Put a pointer to the space into the result register, by copying
2681 // the stack pointer.
2682 BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP);
2684 // Inform the Frame Information that we have just allocated a variable-sized
2686 F->getFrameInfo()->CreateVariableSizedObject();
2689 /// visitMallocInst - Malloc instructions are code generated into direct calls
2690 /// to the library malloc.
2692 void ISel::visitMallocInst(MallocInst &I) {
2693 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2696 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2697 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2699 Arg = makeAnotherReg(Type::UIntTy);
2700 unsigned Op0Reg = getReg(I.getOperand(0));
2701 MachineBasicBlock::iterator MBBI = BB->end();
2702 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
2705 std::vector<ValueRecord> Args;
2706 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2707 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2708 1).addExternalSymbol("malloc", true);
2709 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
2713 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2716 void ISel::visitFreeInst(FreeInst &I) {
2717 std::vector<ValueRecord> Args;
2718 Args.push_back(ValueRecord(I.getOperand(0)));
2719 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2720 1).addExternalSymbol("free", true);
2721 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
2724 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
2725 /// into a machine code representation is a very simple peep-hole fashion. The
2726 /// generated code sucks but the implementation is nice and simple.
2728 FunctionPass *llvm::createX86SimpleInstructionSelector(TargetMachine &TM) {
2729 return new ISel(TM);