1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the x86 target
12 //===----------------------------------------------------------------------===//
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Function.h"
20 #include "llvm/Instructions.h"
21 #include "llvm/IntrinsicLowering.h"
22 #include "llvm/Pass.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/InstVisitor.h"
33 /// BMI - A special BuildMI variant that takes an iterator to insert the
34 /// instruction at as well as a basic block. This is the version for when you
35 /// have a destination register in mind.
36 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
37 MachineBasicBlock::iterator &I,
38 int Opcode, unsigned NumOperands,
40 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
41 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
42 I = MBB->insert(I, MI)+1;
43 return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
46 /// BMI - A special BuildMI variant that takes an iterator to insert the
47 /// instruction at as well as a basic block.
48 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
49 MachineBasicBlock::iterator &I,
50 int Opcode, unsigned NumOperands) {
51 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
52 MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
53 I = MBB->insert(I, MI)+1;
54 return MachineInstrBuilder(MI);
59 struct ISel : public FunctionPass, InstVisitor<ISel> {
61 MachineFunction *F; // The function we are compiling into
62 MachineBasicBlock *BB; // The current MBB we are compiling
63 int VarArgsFrameIndex; // FrameIndex for start of varargs area
65 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
67 // MBBMap - Mapping between LLVM BB -> Machine BB
68 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
70 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
72 /// runOnFunction - Top level implementation of instruction selection for
73 /// the entire function.
75 bool runOnFunction(Function &Fn) {
76 // First pass over the function, lower any unknown intrinsic functions
77 // with the IntrinsicLowering class.
78 LowerUnknownIntrinsicFunctionCalls(Fn);
80 F = &MachineFunction::construct(&Fn, TM);
82 // Create all of the machine basic blocks for the function...
83 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
84 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
88 // Copy incoming arguments off of the stack...
89 LoadArgumentsToVirtualRegs(Fn);
91 // Instruction select everything except PHI nodes
94 // Select the PHI nodes
100 // We always build a machine code representation for the function
104 virtual const char *getPassName() const {
105 return "X86 Simple Instruction Selection";
108 /// visitBasicBlock - This method is called when we are visiting a new basic
109 /// block. This simply creates a new MachineBasicBlock to emit code into
110 /// and adds it to the current MachineFunction. Subsequent visit* for
111 /// instructions will be invoked for all instructions in the basic block.
113 void visitBasicBlock(BasicBlock &LLVM_BB) {
114 BB = MBBMap[&LLVM_BB];
117 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
118 /// function, lowering any calls to unknown intrinsic functions into the
119 /// equivalent LLVM code.
120 void LowerUnknownIntrinsicFunctionCalls(Function &F);
122 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
123 /// from the stack into virtual registers.
125 void LoadArgumentsToVirtualRegs(Function &F);
127 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
128 /// because we have to generate our sources into the source basic blocks,
129 /// not the current one.
131 void SelectPHINodes();
133 // Visitation methods for various instructions. These methods simply emit
134 // fixed X86 code for each instruction.
137 // Control flow operators
138 void visitReturnInst(ReturnInst &RI);
139 void visitBranchInst(BranchInst &BI);
145 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
146 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
148 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
149 const std::vector<ValueRecord> &Args);
150 void visitCallInst(CallInst &I);
151 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
153 // Arithmetic operators
154 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
155 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
156 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
157 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
158 unsigned DestReg, const Type *DestTy,
159 unsigned Op0Reg, unsigned Op1Reg);
160 void doMultiplyConst(MachineBasicBlock *MBB,
161 MachineBasicBlock::iterator &MBBI,
162 unsigned DestReg, const Type *DestTy,
163 unsigned Op0Reg, unsigned Op1Val);
164 void visitMul(BinaryOperator &B);
166 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
167 void visitRem(BinaryOperator &B) { visitDivRem(B); }
168 void visitDivRem(BinaryOperator &B);
171 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
172 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
173 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
175 // Comparison operators...
176 void visitSetCondInst(SetCondInst &I);
177 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
178 MachineBasicBlock *MBB,
179 MachineBasicBlock::iterator &MBBI);
181 // Memory Instructions
182 void visitLoadInst(LoadInst &I);
183 void visitStoreInst(StoreInst &I);
184 void visitGetElementPtrInst(GetElementPtrInst &I);
185 void visitAllocaInst(AllocaInst &I);
186 void visitMallocInst(MallocInst &I);
187 void visitFreeInst(FreeInst &I);
190 void visitShiftInst(ShiftInst &I);
191 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
192 void visitCastInst(CastInst &I);
193 void visitVANextInst(VANextInst &I);
194 void visitVAArgInst(VAArgInst &I);
196 void visitInstruction(Instruction &I) {
197 std::cerr << "Cannot instruction select: " << I;
201 /// promote32 - Make a value 32-bits wide, and put it somewhere.
203 void promote32(unsigned targetReg, const ValueRecord &VR);
205 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
206 /// constant expression GEP support.
208 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator&IP,
209 Value *Src, User::op_iterator IdxBegin,
210 User::op_iterator IdxEnd, unsigned TargetReg);
212 /// emitCastOperation - Common code shared between visitCastInst and
213 /// constant expression cast support.
214 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
215 Value *Src, const Type *DestTy, unsigned TargetReg);
217 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
218 /// and constant expression support.
219 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
220 MachineBasicBlock::iterator &IP,
221 Value *Op0, Value *Op1,
222 unsigned OperatorClass, unsigned TargetReg);
224 void emitDivRemOperation(MachineBasicBlock *BB,
225 MachineBasicBlock::iterator &IP,
226 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
227 const Type *Ty, unsigned TargetReg);
229 /// emitSetCCOperation - Common code shared between visitSetCondInst and
230 /// constant expression support.
231 void emitSetCCOperation(MachineBasicBlock *BB,
232 MachineBasicBlock::iterator &IP,
233 Value *Op0, Value *Op1, unsigned Opcode,
236 /// emitShiftOperation - Common code shared between visitShiftInst and
237 /// constant expression support.
238 void emitShiftOperation(MachineBasicBlock *MBB,
239 MachineBasicBlock::iterator &IP,
240 Value *Op, Value *ShiftAmount, bool isLeftShift,
241 const Type *ResultTy, unsigned DestReg);
244 /// copyConstantToRegister - Output the instructions required to put the
245 /// specified constant into the specified register.
247 void copyConstantToRegister(MachineBasicBlock *MBB,
248 MachineBasicBlock::iterator &MBBI,
249 Constant *C, unsigned Reg);
251 /// makeAnotherReg - This method returns the next register number we haven't
254 /// Long values are handled somewhat specially. They are always allocated
255 /// as pairs of 32 bit integer values. The register number returned is the
256 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
257 /// of the long value.
259 unsigned makeAnotherReg(const Type *Ty) {
260 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
261 "Current target doesn't have X86 reg info??");
262 const X86RegisterInfo *MRI =
263 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
264 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
265 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
266 // Create the lower part
267 F->getSSARegMap()->createVirtualRegister(RC);
268 // Create the upper part.
269 return F->getSSARegMap()->createVirtualRegister(RC)-1;
272 // Add the mapping of regnumber => reg class to MachineFunction
273 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
274 return F->getSSARegMap()->createVirtualRegister(RC);
277 /// getReg - This method turns an LLVM value into a register number. This
278 /// is guaranteed to produce the same register number for a particular value
279 /// every time it is queried.
281 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
282 unsigned getReg(Value *V) {
283 // Just append to the end of the current bb.
284 MachineBasicBlock::iterator It = BB->end();
285 return getReg(V, BB, It);
287 unsigned getReg(Value *V, MachineBasicBlock *MBB,
288 MachineBasicBlock::iterator &IPt) {
289 unsigned &Reg = RegMap[V];
291 Reg = makeAnotherReg(V->getType());
295 // If this operand is a constant, emit the code to copy the constant into
296 // the register here...
298 if (Constant *C = dyn_cast<Constant>(V)) {
299 copyConstantToRegister(MBB, IPt, C, Reg);
300 RegMap.erase(V); // Assign a new name to this constant if ref'd again
301 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
302 // Move the address of the global into the register
303 BMI(MBB, IPt, X86::MOVir32, 1, Reg).addGlobalAddress(GV);
304 RegMap.erase(V); // Assign a new name to this address if ref'd again
312 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
316 cByte, cShort, cInt, cFP, cLong
319 /// getClass - Turn a primitive type into a "class" number which is based on the
320 /// size of the type, and whether or not it is floating point.
322 static inline TypeClass getClass(const Type *Ty) {
323 switch (Ty->getPrimitiveID()) {
324 case Type::SByteTyID:
325 case Type::UByteTyID: return cByte; // Byte operands are class #0
326 case Type::ShortTyID:
327 case Type::UShortTyID: return cShort; // Short operands are class #1
330 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
332 case Type::FloatTyID:
333 case Type::DoubleTyID: return cFP; // Floating Point is #3
336 case Type::ULongTyID: return cLong; // Longs are class #4
338 assert(0 && "Invalid type to getClass!");
339 return cByte; // not reached
343 // getClassB - Just like getClass, but treat boolean values as bytes.
344 static inline TypeClass getClassB(const Type *Ty) {
345 if (Ty == Type::BoolTy) return cByte;
350 /// copyConstantToRegister - Output the instructions required to put the
351 /// specified constant into the specified register.
353 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
354 MachineBasicBlock::iterator &IP,
355 Constant *C, unsigned R) {
356 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
358 switch (CE->getOpcode()) {
359 case Instruction::GetElementPtr:
360 emitGEPOperation(MBB, IP, CE->getOperand(0),
361 CE->op_begin()+1, CE->op_end(), R);
363 case Instruction::Cast:
364 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
367 case Instruction::Xor: ++Class; // FALL THROUGH
368 case Instruction::Or: ++Class; // FALL THROUGH
369 case Instruction::And: ++Class; // FALL THROUGH
370 case Instruction::Sub: ++Class; // FALL THROUGH
371 case Instruction::Add:
372 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
376 case Instruction::Mul: {
377 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
378 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
379 doMultiply(MBB, IP, R, CE->getType(), Op0Reg, Op1Reg);
382 case Instruction::Div:
383 case Instruction::Rem: {
384 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
385 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
386 emitDivRemOperation(MBB, IP, Op0Reg, Op1Reg,
387 CE->getOpcode() == Instruction::Div,
392 case Instruction::SetNE:
393 case Instruction::SetEQ:
394 case Instruction::SetLT:
395 case Instruction::SetGT:
396 case Instruction::SetLE:
397 case Instruction::SetGE:
398 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
402 case Instruction::Shl:
403 case Instruction::Shr:
404 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
405 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
409 std::cerr << "Offending expr: " << C << "\n";
410 assert(0 && "Constant expression not yet handled!\n");
414 if (C->getType()->isIntegral()) {
415 unsigned Class = getClassB(C->getType());
417 if (Class == cLong) {
418 // Copy the value into the register pair.
419 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
420 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(Val & 0xFFFFFFFF);
421 BMI(MBB, IP, X86::MOVir32, 1, R+1).addZImm(Val >> 32);
425 assert(Class <= cInt && "Type not handled yet!");
427 static const unsigned IntegralOpcodeTab[] = {
428 X86::MOVir8, X86::MOVir16, X86::MOVir32
431 if (C->getType() == Type::BoolTy) {
432 BMI(MBB, IP, X86::MOVir8, 1, R).addZImm(C == ConstantBool::True);
434 ConstantInt *CI = cast<ConstantInt>(C);
435 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CI->getRawValue());
437 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
438 double Value = CFP->getValue();
440 BMI(MBB, IP, X86::FLD0, 0, R);
441 else if (Value == +1.0)
442 BMI(MBB, IP, X86::FLD1, 0, R);
444 // Otherwise we need to spill the constant to memory...
445 MachineConstantPool *CP = F->getConstantPool();
446 unsigned CPI = CP->getConstantPoolIndex(CFP);
447 const Type *Ty = CFP->getType();
449 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
450 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
451 addConstantPoolReference(BMI(MBB, IP, LoadOpcode, 4, R), CPI);
454 } else if (isa<ConstantPointerNull>(C)) {
455 // Copy zero (null pointer) to the register.
456 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0);
457 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
458 unsigned SrcReg = getReg(CPR->getValue(), MBB, IP);
459 BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg);
461 std::cerr << "Offending constant: " << C << "\n";
462 assert(0 && "Type not handled yet!");
466 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
467 /// the stack into virtual registers.
469 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
470 // Emit instructions to load the arguments... On entry to a function on the
471 // X86, the stack frame looks like this:
473 // [ESP] -- return address
474 // [ESP + 4] -- first argument (leftmost lexically)
475 // [ESP + 8] -- second argument, if first argument is four bytes in size
478 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
479 MachineFrameInfo *MFI = F->getFrameInfo();
481 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
482 unsigned Reg = getReg(*I);
484 int FI; // Frame object index
485 switch (getClassB(I->getType())) {
487 FI = MFI->CreateFixedObject(1, ArgOffset);
488 addFrameReference(BuildMI(BB, X86::MOVmr8, 4, Reg), FI);
491 FI = MFI->CreateFixedObject(2, ArgOffset);
492 addFrameReference(BuildMI(BB, X86::MOVmr16, 4, Reg), FI);
495 FI = MFI->CreateFixedObject(4, ArgOffset);
496 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
499 FI = MFI->CreateFixedObject(8, ArgOffset);
500 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
501 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg+1), FI, 4);
502 ArgOffset += 4; // longs require 4 additional bytes
506 if (I->getType() == Type::FloatTy) {
507 Opcode = X86::FLDr32;
508 FI = MFI->CreateFixedObject(4, ArgOffset);
510 Opcode = X86::FLDr64;
511 FI = MFI->CreateFixedObject(8, ArgOffset);
512 ArgOffset += 4; // doubles require 4 additional bytes
514 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
517 assert(0 && "Unhandled argument type!");
519 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
522 // If the function takes variable number of arguments, add a frame offset for
523 // the start of the first vararg value... this is used to expand
525 if (Fn.getFunctionType()->isVarArg())
526 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
530 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
531 /// because we have to generate our sources into the source basic blocks, not
534 void ISel::SelectPHINodes() {
535 const TargetInstrInfo &TII = TM.getInstrInfo();
536 const Function &LF = *F->getFunction(); // The LLVM function...
537 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
538 const BasicBlock *BB = I;
539 MachineBasicBlock *MBB = MBBMap[I];
541 // Loop over all of the PHI nodes in the LLVM basic block...
542 unsigned NumPHIs = 0;
543 for (BasicBlock::const_iterator I = BB->begin();
544 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
546 // Create a new machine instr PHI node, and insert it.
547 unsigned PHIReg = getReg(*PN);
548 MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
549 MBB->insert(MBB->begin()+NumPHIs++, PhiMI);
551 MachineInstr *LongPhiMI = 0;
552 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
553 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
554 MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
557 // PHIValues - Map of blocks to incoming virtual registers. We use this
558 // so that we only initialize one incoming value for a particular block,
559 // even if the block has multiple entries in the PHI node.
561 std::map<MachineBasicBlock*, unsigned> PHIValues;
563 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
564 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
566 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
567 PHIValues.lower_bound(PredMBB);
569 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
570 // We already inserted an initialization of the register for this
571 // predecessor. Recycle it.
572 ValReg = EntryIt->second;
575 // Get the incoming value into a virtual register.
577 Value *Val = PN->getIncomingValue(i);
579 // If this is a constant or GlobalValue, we may have to insert code
580 // into the basic block to compute it into a virtual register.
581 if (isa<Constant>(Val) || isa<GlobalValue>(Val)) {
582 // Because we don't want to clobber any values which might be in
583 // physical registers with the computation of this constant (which
584 // might be arbitrarily complex if it is a constant expression),
585 // just insert the computation at the top of the basic block.
586 MachineBasicBlock::iterator PI = PredMBB->begin();
588 // Skip over any PHI nodes though!
589 while (PI != PredMBB->end() && (*PI)->getOpcode() == X86::PHI)
592 ValReg = getReg(Val, PredMBB, PI);
594 ValReg = getReg(Val);
597 // Remember that we inserted a value for this PHI for this predecessor
598 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
601 PhiMI->addRegOperand(ValReg);
602 PhiMI->addMachineBasicBlockOperand(PredMBB);
604 LongPhiMI->addRegOperand(ValReg+1);
605 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
612 // canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
613 // the conditional branch instruction which is the only user of the cc
614 // instruction. This is the case if the conditional branch is the only user of
615 // the setcc, and if the setcc is in the same basic block as the conditional
616 // branch. We also don't handle long arguments below, so we reject them here as
619 static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
620 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
621 if (SCI->hasOneUse() && isa<BranchInst>(SCI->use_back()) &&
622 SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
623 const Type *Ty = SCI->getOperand(0)->getType();
624 if (Ty != Type::LongTy && Ty != Type::ULongTy)
630 // Return a fixed numbering for setcc instructions which does not depend on the
631 // order of the opcodes.
633 static unsigned getSetCCNumber(unsigned Opcode) {
635 default: assert(0 && "Unknown setcc instruction!");
636 case Instruction::SetEQ: return 0;
637 case Instruction::SetNE: return 1;
638 case Instruction::SetLT: return 2;
639 case Instruction::SetGE: return 3;
640 case Instruction::SetGT: return 4;
641 case Instruction::SetLE: return 5;
645 // LLVM -> X86 signed X86 unsigned
646 // ----- ---------- ------------
647 // seteq -> sete sete
648 // setne -> setne setne
649 // setlt -> setl setb
650 // setge -> setge setae
651 // setgt -> setg seta
652 // setle -> setle setbe
654 // sets // Used by comparison with 0 optimization
656 static const unsigned SetCCOpcodeTab[2][8] = {
657 { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
659 { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
660 X86::SETSr, X86::SETNSr },
663 // EmitComparison - This function emits a comparison of the two operands,
664 // returning the extended setcc code to use.
665 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
666 MachineBasicBlock *MBB,
667 MachineBasicBlock::iterator &IP) {
668 // The arguments are already supposed to be of the same type.
669 const Type *CompTy = Op0->getType();
670 unsigned Class = getClassB(CompTy);
671 unsigned Op0r = getReg(Op0, MBB, IP);
673 // Special case handling of: cmp R, i
674 if (Class == cByte || Class == cShort || Class == cInt)
675 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
676 uint64_t Op1v = cast<ConstantInt>(CI)->getRawValue();
678 // Mask off any upper bits of the constant, if there are any...
679 Op1v &= (1ULL << (8 << Class)) - 1;
681 // If this is a comparison against zero, emit more efficient code. We
682 // can't handle unsigned comparisons against zero unless they are == or
683 // !=. These should have been strength reduced already anyway.
684 if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
685 static const unsigned TESTTab[] = {
686 X86::TESTrr8, X86::TESTrr16, X86::TESTrr32
688 BMI(MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
690 if (OpNum == 2) return 6; // Map jl -> js
691 if (OpNum == 3) return 7; // Map jg -> jns
695 static const unsigned CMPTab[] = {
696 X86::CMPri8, X86::CMPri16, X86::CMPri32
699 BMI(MBB, IP, CMPTab[Class], 2).addReg(Op0r).addZImm(Op1v);
703 unsigned Op1r = getReg(Op1, MBB, IP);
705 default: assert(0 && "Unknown type class!");
706 // Emit: cmp <var1>, <var2> (do the comparison). We can
707 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
710 BMI(MBB, IP, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r);
713 BMI(MBB, IP, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r);
716 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
719 BMI(MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
720 BMI(MBB, IP, X86::FNSTSWr8, 0);
721 BMI(MBB, IP, X86::SAHF, 1);
725 if (OpNum < 2) { // seteq, setne
726 unsigned LoTmp = makeAnotherReg(Type::IntTy);
727 unsigned HiTmp = makeAnotherReg(Type::IntTy);
728 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
729 BMI(MBB, IP, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r);
730 BMI(MBB, IP, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
731 BMI(MBB, IP, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
732 break; // Allow the sete or setne to be generated from flags set by OR
734 // Emit a sequence of code which compares the high and low parts once
735 // each, then uses a conditional move to handle the overflow case. For
736 // example, a setlt for long would generate code like this:
738 // AL = lo(op1) < lo(op2) // Signedness depends on operands
739 // BL = hi(op1) < hi(op2) // Always unsigned comparison
740 // dest = hi(op1) == hi(op2) ? AL : BL;
743 // FIXME: This would be much better if we had hierarchical register
744 // classes! Until then, hardcode registers so that we can deal with their
745 // aliases (because we don't have conditional byte moves).
747 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
748 BMI(MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
749 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
750 BMI(MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
751 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
752 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
753 BMI(MBB, IP, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
754 // NOTE: visitSetCondInst knows that the value is dumped into the BL
755 // register at this point for long values...
763 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
764 /// register, then move it to wherever the result should be.
766 void ISel::visitSetCondInst(SetCondInst &I) {
767 if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
769 unsigned DestReg = getReg(I);
770 MachineBasicBlock::iterator MII = BB->end();
771 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
775 /// emitSetCCOperation - Common code shared between visitSetCondInst and
776 /// constant expression support.
777 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
778 MachineBasicBlock::iterator &IP,
779 Value *Op0, Value *Op1, unsigned Opcode,
780 unsigned TargetReg) {
781 unsigned OpNum = getSetCCNumber(Opcode);
782 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
784 const Type *CompTy = Op0->getType();
785 unsigned CompClass = getClassB(CompTy);
786 bool isSigned = CompTy->isSigned() && CompClass != cFP;
788 if (CompClass != cLong || OpNum < 2) {
789 // Handle normal comparisons with a setcc instruction...
790 BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
792 // Handle long comparisons by copying the value which is already in BL into
793 // the register we want...
794 BMI(MBB, IP, X86::MOVrr8, 1, TargetReg).addReg(X86::BL);
801 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
802 /// operand, in the specified target register.
803 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
804 bool isUnsigned = VR.Ty->isUnsigned();
806 // Make sure we have the register number for this value...
807 unsigned Reg = VR.Val ? getReg(VR.Val) : VR.Reg;
809 switch (getClassB(VR.Ty)) {
811 // Extend value into target register (8->32)
813 BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(Reg);
815 BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(Reg);
818 // Extend value into target register (16->32)
820 BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(Reg);
822 BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(Reg);
825 // Move value into target register (32->32)
826 BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(Reg);
829 assert(0 && "Unpromotable operand class in promote32");
833 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
834 /// we have the following possibilities:
836 /// ret void: No return value, simply emit a 'ret' instruction
837 /// ret sbyte, ubyte : Extend value into EAX and return
838 /// ret short, ushort: Extend value into EAX and return
839 /// ret int, uint : Move value into EAX and return
840 /// ret pointer : Move value into EAX and return
841 /// ret long, ulong : Move value into EAX/EDX and return
842 /// ret float/double : Top of FP stack
844 void ISel::visitReturnInst(ReturnInst &I) {
845 if (I.getNumOperands() == 0) {
846 BuildMI(BB, X86::FP_REG_KILL, 0);
847 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
851 Value *RetVal = I.getOperand(0);
852 unsigned RetReg = getReg(RetVal);
853 switch (getClassB(RetVal->getType())) {
854 case cByte: // integral return values: extend or move into EAX and return
857 promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
858 // Declare that EAX is live on exit
859 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
861 case cFP: // Floats & Doubles: Return in ST(0)
862 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
863 // Declare that top-of-stack is live on exit
864 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
867 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
868 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
869 // Declare that EAX & EDX are live on exit
870 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
876 // Emit a 'ret' instruction
877 BuildMI(BB, X86::FP_REG_KILL, 0);
878 BuildMI(BB, X86::RET, 0);
881 // getBlockAfter - Return the basic block which occurs lexically after the
883 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
884 Function::iterator I = BB; ++I; // Get iterator to next block
885 return I != BB->getParent()->end() ? &*I : 0;
888 /// visitBranchInst - Handle conditional and unconditional branches here. Note
889 /// that since code layout is frozen at this point, that if we are trying to
890 /// jump to a block that is the immediate successor of the current block, we can
891 /// just make a fall-through (but we don't currently).
893 void ISel::visitBranchInst(BranchInst &BI) {
894 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
896 if (!BI.isConditional()) { // Unconditional branch?
897 if (BI.getSuccessor(0) != NextBB) {
898 BuildMI(BB, X86::FP_REG_KILL, 0);
899 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
904 // See if we can fold the setcc into the branch itself...
905 SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
907 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
908 // computed some other way...
909 unsigned condReg = getReg(BI.getCondition());
910 BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
911 BuildMI(BB, X86::FP_REG_KILL, 0);
912 if (BI.getSuccessor(1) == NextBB) {
913 if (BI.getSuccessor(0) != NextBB)
914 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
916 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
918 if (BI.getSuccessor(0) != NextBB)
919 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
924 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
925 MachineBasicBlock::iterator MII = BB->end();
926 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
928 const Type *CompTy = SCI->getOperand(0)->getType();
929 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
932 // LLVM -> X86 signed X86 unsigned
933 // ----- ---------- ------------
941 // js // Used by comparison with 0 optimization
944 static const unsigned OpcodeTab[2][8] = {
945 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
946 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
950 BuildMI(BB, X86::FP_REG_KILL, 0);
951 if (BI.getSuccessor(0) != NextBB) {
952 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
953 if (BI.getSuccessor(1) != NextBB)
954 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
956 // Change to the inverse condition...
957 if (BI.getSuccessor(1) != NextBB) {
959 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
965 /// doCall - This emits an abstract call instruction, setting up the arguments
966 /// and the return value as appropriate. For the actual function call itself,
967 /// it inserts the specified CallMI instruction into the stream.
969 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
970 const std::vector<ValueRecord> &Args) {
972 // Count how many bytes are to be pushed on the stack...
973 unsigned NumBytes = 0;
976 for (unsigned i = 0, e = Args.size(); i != e; ++i)
977 switch (getClassB(Args[i].Ty)) {
978 case cByte: case cShort: case cInt:
979 NumBytes += 4; break;
981 NumBytes += 8; break;
983 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
985 default: assert(0 && "Unknown class!");
988 // Adjust the stack pointer for the new arguments...
989 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes);
991 // Arguments go on the stack in reverse order, as specified by the ABI.
992 unsigned ArgOffset = 0;
993 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
994 unsigned ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
995 switch (getClassB(Args[i].Ty)) {
998 // Promote arg to 32 bits wide into a temporary register...
999 unsigned R = makeAnotherReg(Type::UIntTy);
1000 promote32(R, Args[i]);
1001 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1002 X86::ESP, ArgOffset).addReg(R);
1006 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1007 X86::ESP, ArgOffset).addReg(ArgReg);
1010 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1011 X86::ESP, ArgOffset).addReg(ArgReg);
1012 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1013 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
1014 ArgOffset += 4; // 8 byte entry, not 4.
1018 if (Args[i].Ty == Type::FloatTy) {
1019 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
1020 X86::ESP, ArgOffset).addReg(ArgReg);
1022 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
1023 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
1024 X86::ESP, ArgOffset).addReg(ArgReg);
1025 ArgOffset += 4; // 8 byte entry, not 4.
1029 default: assert(0 && "Unknown class!");
1034 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(0);
1037 BB->push_back(CallMI);
1039 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes);
1041 // If there is a return value, scavenge the result from the location the call
1044 if (Ret.Ty != Type::VoidTy) {
1045 unsigned DestClass = getClassB(Ret.Ty);
1046 switch (DestClass) {
1050 // Integral results are in %eax, or the appropriate portion
1052 static const unsigned regRegMove[] = {
1053 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
1055 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
1056 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
1059 case cFP: // Floating-point return values live in %ST(0)
1060 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
1062 case cLong: // Long values are left in EDX:EAX
1063 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg).addReg(X86::EAX);
1064 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg+1).addReg(X86::EDX);
1066 default: assert(0 && "Unknown class!");
1072 /// visitCallInst - Push args on stack and do a procedure call instruction.
1073 void ISel::visitCallInst(CallInst &CI) {
1074 MachineInstr *TheCall;
1075 if (Function *F = CI.getCalledFunction()) {
1076 // Is it an intrinsic function call?
1077 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1078 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1082 // Emit a CALL instruction with PC-relative displacement.
1083 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
1084 } else { // Emit an indirect call...
1085 unsigned Reg = getReg(CI.getCalledValue());
1086 TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg);
1089 std::vector<ValueRecord> Args;
1090 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1091 Args.push_back(ValueRecord(CI.getOperand(i)));
1093 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1094 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1098 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1099 /// function, lowering any calls to unknown intrinsic functions into the
1100 /// equivalent LLVM code.
1101 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1102 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1103 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1104 if (CallInst *CI = dyn_cast<CallInst>(I++))
1105 if (Function *F = CI->getCalledFunction())
1106 switch (F->getIntrinsicID()) {
1107 case Intrinsic::not_intrinsic:
1108 case Intrinsic::va_start:
1109 case Intrinsic::va_copy:
1110 case Intrinsic::va_end:
1111 // We directly implement these intrinsics
1114 // All other intrinsic calls we must lower.
1115 Instruction *Before = CI->getPrev();
1116 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1117 if (Before) { // Move iterator to instruction after call
1126 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1127 unsigned TmpReg1, TmpReg2;
1129 case Intrinsic::va_start:
1130 // Get the address of the first vararg value...
1131 TmpReg1 = getReg(CI);
1132 addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
1135 case Intrinsic::va_copy:
1136 TmpReg1 = getReg(CI);
1137 TmpReg2 = getReg(CI.getOperand(1));
1138 BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2);
1140 case Intrinsic::va_end: return; // Noop on X86
1142 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1147 /// visitSimpleBinary - Implement simple binary operators for integral types...
1148 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1150 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1151 unsigned DestReg = getReg(B);
1152 MachineBasicBlock::iterator MI = BB->end();
1153 emitSimpleBinaryOperation(BB, MI, B.getOperand(0), B.getOperand(1),
1154 OperatorClass, DestReg);
1157 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1158 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1161 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1162 /// and constant expression support.
1164 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1165 MachineBasicBlock::iterator &IP,
1166 Value *Op0, Value *Op1,
1167 unsigned OperatorClass, unsigned DestReg) {
1168 unsigned Class = getClassB(Op0->getType());
1170 // sub 0, X -> neg X
1171 if (OperatorClass == 1 && Class != cLong)
1172 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
1173 if (CI->isNullValue()) {
1174 unsigned op1Reg = getReg(Op1, MBB, IP);
1176 default: assert(0 && "Unknown class for this function!");
1178 BMI(MBB, IP, X86::NEGr8, 1, DestReg).addReg(op1Reg);
1181 BMI(MBB, IP, X86::NEGr16, 1, DestReg).addReg(op1Reg);
1184 BMI(MBB, IP, X86::NEGr32, 1, DestReg).addReg(op1Reg);
1189 if (!isa<ConstantInt>(Op1) || Class == cLong) {
1190 static const unsigned OpcodeTab[][4] = {
1191 // Arithmetic operators
1192 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
1193 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
1195 // Bitwise operators
1196 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
1197 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
1198 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
1201 bool isLong = false;
1202 if (Class == cLong) {
1204 Class = cInt; // Bottom 32 bits are handled just like ints
1207 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1208 assert(Opcode && "Floating point arguments to logical inst?");
1209 unsigned Op0r = getReg(Op0, MBB, IP);
1210 unsigned Op1r = getReg(Op1, MBB, IP);
1211 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1213 if (isLong) { // Handle the upper 32 bits of long values...
1214 static const unsigned TopTab[] = {
1215 X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
1217 BMI(MBB, IP, TopTab[OperatorClass], 2,
1218 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
1223 // Special case: op Reg, <const>
1224 ConstantInt *Op1C = cast<ConstantInt>(Op1);
1225 unsigned Op0r = getReg(Op0, MBB, IP);
1227 // xor X, -1 -> not X
1228 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1229 static unsigned const NOTTab[] = { X86::NOTr8, X86::NOTr16, X86::NOTr32 };
1230 BMI(MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
1234 // add X, -1 -> dec X
1235 if (OperatorClass == 0 && Op1C->isAllOnesValue()) {
1236 static unsigned const DECTab[] = { X86::DECr8, X86::DECr16, X86::DECr32 };
1237 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1241 // add X, 1 -> inc X
1242 if (OperatorClass == 0 && Op1C->equalsInt(1)) {
1243 static unsigned const DECTab[] = { X86::INCr8, X86::INCr16, X86::INCr32 };
1244 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1248 static const unsigned OpcodeTab[][3] = {
1249 // Arithmetic operators
1250 { X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
1251 { X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
1253 // Bitwise operators
1254 { X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
1255 { X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
1256 { X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
1259 assert(Class < 3 && "General code handles 64-bit integer types!");
1260 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1261 uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
1263 // Mask off any upper bits of the constant, if there are any...
1264 Op1v &= (1ULL << (8 << Class)) - 1;
1265 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addZImm(Op1v);
1268 /// doMultiply - Emit appropriate instructions to multiply together the
1269 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1270 /// result should be given as DestTy.
1272 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
1273 unsigned DestReg, const Type *DestTy,
1274 unsigned op0Reg, unsigned op1Reg) {
1275 unsigned Class = getClass(DestTy);
1277 case cFP: // Floating point multiply
1278 BMI(BB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1282 BMI(BB, MBBI, Class == cInt ? X86::IMULrr32 : X86::IMULrr16, 2, DestReg)
1283 .addReg(op0Reg).addReg(op1Reg);
1286 // Must use the MUL instruction, which forces use of AL...
1287 BMI(MBB, MBBI, X86::MOVrr8, 1, X86::AL).addReg(op0Reg);
1288 BMI(MBB, MBBI, X86::MULr8, 1).addReg(op1Reg);
1289 BMI(MBB, MBBI, X86::MOVrr8, 1, DestReg).addReg(X86::AL);
1292 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
1296 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1297 // returns zero when the input is not exactly a power of two.
1298 static unsigned ExactLog2(unsigned Val) {
1299 if (Val == 0) return 0;
1302 if (Val & 1) return 0;
1309 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
1310 MachineBasicBlock::iterator &IP,
1311 unsigned DestReg, const Type *DestTy,
1312 unsigned op0Reg, unsigned ConstRHS) {
1313 unsigned Class = getClass(DestTy);
1315 // If the element size is exactly a power of 2, use a shift to get it.
1316 if (unsigned Shift = ExactLog2(ConstRHS)) {
1318 default: assert(0 && "Unknown class for this function!");
1320 BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1323 BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1326 BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1331 if (Class == cShort) {
1332 BMI(MBB, IP, X86::IMULri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1334 } else if (Class == cInt) {
1335 BMI(MBB, IP, X86::IMULri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1339 // Most general case, emit a normal multiply...
1340 static const unsigned MOVirTab[] = {
1341 X86::MOVir8, X86::MOVir16, X86::MOVir32
1344 unsigned TmpReg = makeAnotherReg(DestTy);
1345 BMI(MBB, IP, MOVirTab[Class], 1, TmpReg).addZImm(ConstRHS);
1347 // Emit a MUL to multiply the register holding the index by
1348 // elementSize, putting the result in OffsetReg.
1349 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
1352 /// visitMul - Multiplies are not simple binary operators because they must deal
1353 /// with the EAX register explicitly.
1355 void ISel::visitMul(BinaryOperator &I) {
1356 unsigned Op0Reg = getReg(I.getOperand(0));
1357 unsigned DestReg = getReg(I);
1359 // Simple scalar multiply?
1360 if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
1361 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1))) {
1362 unsigned Val = (unsigned)CI->getRawValue(); // Cannot be 64-bit constant
1363 MachineBasicBlock::iterator MBBI = BB->end();
1364 doMultiplyConst(BB, MBBI, DestReg, I.getType(), Op0Reg, Val);
1366 unsigned Op1Reg = getReg(I.getOperand(1));
1367 MachineBasicBlock::iterator MBBI = BB->end();
1368 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
1371 unsigned Op1Reg = getReg(I.getOperand(1));
1373 // Long value. We have to do things the hard way...
1374 // Multiply the two low parts... capturing carry into EDX
1375 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
1376 BuildMI(BB, X86::MULr32, 1).addReg(Op1Reg); // AL*BL
1378 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1379 BuildMI(BB, X86::MOVrr32, 1, DestReg).addReg(X86::EAX); // AL*BL
1380 BuildMI(BB, X86::MOVrr32, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32
1382 MachineBasicBlock::iterator MBBI = BB->end();
1383 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
1384 BMI(BB, MBBI, X86::IMULrr32, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
1386 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1387 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
1388 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1391 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1392 BMI(BB, MBBI, X86::IMULrr32, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
1394 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1395 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1400 /// visitDivRem - Handle division and remainder instructions... these
1401 /// instruction both require the same instructions to be generated, they just
1402 /// select the result from a different register. Note that both of these
1403 /// instructions work differently for signed and unsigned operands.
1405 void ISel::visitDivRem(BinaryOperator &I) {
1406 unsigned Op0Reg = getReg(I.getOperand(0));
1407 unsigned Op1Reg = getReg(I.getOperand(1));
1408 unsigned ResultReg = getReg(I);
1410 MachineBasicBlock::iterator IP = BB->end();
1411 emitDivRemOperation(BB, IP, Op0Reg, Op1Reg, I.getOpcode() == Instruction::Div,
1412 I.getType(), ResultReg);
1415 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1416 MachineBasicBlock::iterator &IP,
1417 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
1418 const Type *Ty, unsigned ResultReg) {
1419 unsigned Class = getClass(Ty);
1421 case cFP: // Floating point divide
1423 BMI(BB, IP, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1424 } else { // Floating point remainder...
1425 MachineInstr *TheCall =
1426 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1427 std::vector<ValueRecord> Args;
1428 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1429 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1430 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1434 static const char *FnName[] =
1435 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1437 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
1438 MachineInstr *TheCall =
1439 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
1441 std::vector<ValueRecord> Args;
1442 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1443 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1444 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1447 case cByte: case cShort: case cInt:
1448 break; // Small integrals, handled below...
1449 default: assert(0 && "Unknown class!");
1452 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1453 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1454 static const unsigned SarOpcode[]={ X86::SARir8, X86::SARir16, X86::SARir32 };
1455 static const unsigned ClrOpcode[]={ X86::MOVir8, X86::MOVir16, X86::MOVir32 };
1456 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
1458 static const unsigned DivOpcode[][4] = {
1459 { X86::DIVr8 , X86::DIVr16 , X86::DIVr32 , 0 }, // Unsigned division
1460 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
1463 bool isSigned = Ty->isSigned();
1464 unsigned Reg = Regs[Class];
1465 unsigned ExtReg = ExtRegs[Class];
1467 // Put the first operand into one of the A registers...
1468 BMI(BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
1471 // Emit a sign extension instruction...
1472 unsigned ShiftResult = makeAnotherReg(Ty);
1473 BMI(BB, IP, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
1474 BMI(BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
1476 // If unsigned, emit a zeroing instruction... (reg = 0)
1477 BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addZImm(0);
1480 // Emit the appropriate divide or remainder instruction...
1481 BMI(BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
1483 // Figure out which register we want to pick the result out of...
1484 unsigned DestReg = isDiv ? Reg : ExtReg;
1486 // Put the result into the destination register...
1487 BMI(BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
1491 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1492 /// for constant immediate shift values, and for constant immediate
1493 /// shift values equal to 1. Even the general case is sort of special,
1494 /// because the shift amount has to be in CL, not just any old register.
1496 void ISel::visitShiftInst(ShiftInst &I) {
1497 MachineBasicBlock::iterator IP = BB->end ();
1498 emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1),
1499 I.getOpcode () == Instruction::Shl, I.getType (),
1503 /// emitShiftOperation - Common code shared between visitShiftInst and
1504 /// constant expression support.
1505 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
1506 MachineBasicBlock::iterator &IP,
1507 Value *Op, Value *ShiftAmount, bool isLeftShift,
1508 const Type *ResultTy, unsigned DestReg) {
1509 unsigned SrcReg = getReg (Op, MBB, IP);
1510 bool isSigned = ResultTy->isSigned ();
1511 unsigned Class = getClass (ResultTy);
1513 static const unsigned ConstantOperand[][4] = {
1514 { X86::SHRir8, X86::SHRir16, X86::SHRir32, X86::SHRDir32 }, // SHR
1515 { X86::SARir8, X86::SARir16, X86::SARir32, X86::SHRDir32 }, // SAR
1516 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SHL
1517 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SAL = SHL
1520 static const unsigned NonConstantOperand[][4] = {
1521 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
1522 { X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
1523 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
1524 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
1527 // Longs, as usual, are handled specially...
1528 if (Class == cLong) {
1529 // If we have a constant shift, we can generate much more efficient code
1530 // than otherwise...
1532 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
1533 unsigned Amount = CUI->getValue();
1535 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1537 BMI(MBB, IP, Opc[3], 3,
1538 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1539 BMI(MBB, IP, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1541 BMI(MBB, IP, Opc[3], 3,
1542 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1543 BMI(MBB, IP, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1545 } else { // Shifting more than 32 bits
1548 BMI(MBB, IP, X86::SHLir32, 2,
1549 DestReg + 1).addReg(SrcReg).addZImm(Amount);
1550 BMI(MBB, IP, X86::MOVir32, 1,
1551 DestReg).addZImm(0);
1553 unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32;
1554 BMI(MBB, IP, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1555 BMI(MBB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1559 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1561 if (!isLeftShift && isSigned) {
1562 // If this is a SHR of a Long, then we need to do funny sign extension
1563 // stuff. TmpReg gets the value to use as the high-part if we are
1564 // shifting more than 32 bits.
1565 BMI(MBB, IP, X86::SARir32, 2, TmpReg).addReg(SrcReg).addZImm(31);
1567 // Other shifts use a fixed zero value if the shift is more than 32
1569 BMI(MBB, IP, X86::MOVir32, 1, TmpReg).addZImm(0);
1572 // Initialize CL with the shift amount...
1573 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
1574 BMI(MBB, IP, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmountReg);
1576 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
1577 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
1579 // TmpReg2 = shld inHi, inLo
1580 BMI(MBB, IP, X86::SHLDrr32, 2, TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
1581 // TmpReg3 = shl inLo, CL
1582 BMI(MBB, IP, X86::SHLrr32, 1, TmpReg3).addReg(SrcReg);
1584 // Set the flags to indicate whether the shift was by more than 32 bits.
1585 BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1587 // DestHi = (>32) ? TmpReg3 : TmpReg2;
1588 BMI(MBB, IP, X86::CMOVNErr32, 2,
1589 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
1590 // DestLo = (>32) ? TmpReg : TmpReg3;
1591 BMI(MBB, IP, X86::CMOVNErr32, 2,
1592 DestReg).addReg(TmpReg3).addReg(TmpReg);
1594 // TmpReg2 = shrd inLo, inHi
1595 BMI(MBB, IP, X86::SHRDrr32, 2, TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
1596 // TmpReg3 = s[ah]r inHi, CL
1597 BMI(MBB, IP, isSigned ? X86::SARrr32 : X86::SHRrr32, 1, TmpReg3)
1600 // Set the flags to indicate whether the shift was by more than 32 bits.
1601 BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1603 // DestLo = (>32) ? TmpReg3 : TmpReg2;
1604 BMI(MBB, IP, X86::CMOVNErr32, 2,
1605 DestReg).addReg(TmpReg2).addReg(TmpReg3);
1607 // DestHi = (>32) ? TmpReg : TmpReg3;
1608 BMI(MBB, IP, X86::CMOVNErr32, 2,
1609 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
1615 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
1616 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
1617 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
1619 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1620 BMI(MBB, IP, Opc[Class], 2,
1621 DestReg).addReg(SrcReg).addZImm(CUI->getValue());
1622 } else { // The shift amount is non-constant.
1623 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
1624 BMI(MBB, IP, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmountReg);
1626 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
1627 BMI(MBB, IP, Opc[Class], 1, DestReg).addReg(SrcReg);
1632 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
1633 /// instruction. The load and store instructions are the only place where we
1634 /// need to worry about the memory layout of the target machine.
1636 void ISel::visitLoadInst(LoadInst &I) {
1637 unsigned SrcAddrReg = getReg(I.getOperand(0));
1638 unsigned DestReg = getReg(I);
1640 unsigned Class = getClassB(I.getType());
1642 if (Class == cLong) {
1643 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), SrcAddrReg);
1644 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
1648 static const unsigned Opcodes[] = {
1649 X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr32
1651 unsigned Opcode = Opcodes[Class];
1652 if (I.getType() == Type::DoubleTy) Opcode = X86::FLDr64;
1653 addDirectMem(BuildMI(BB, Opcode, 4, DestReg), SrcAddrReg);
1656 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
1659 void ISel::visitStoreInst(StoreInst &I) {
1660 unsigned ValReg = getReg(I.getOperand(0));
1661 unsigned AddressReg = getReg(I.getOperand(1));
1663 const Type *ValTy = I.getOperand(0)->getType();
1664 unsigned Class = getClassB(ValTy);
1666 if (Class == cLong) {
1667 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
1668 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg,4).addReg(ValReg+1);
1672 static const unsigned Opcodes[] = {
1673 X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTr32
1675 unsigned Opcode = Opcodes[Class];
1676 if (ValTy == Type::DoubleTy) Opcode = X86::FSTr64;
1677 addDirectMem(BuildMI(BB, Opcode, 1+4), AddressReg).addReg(ValReg);
1681 /// visitCastInst - Here we have various kinds of copying with or without
1682 /// sign extension going on.
1683 void ISel::visitCastInst(CastInst &CI) {
1684 Value *Op = CI.getOperand(0);
1685 // If this is a cast from a 32-bit integer to a Long type, and the only uses
1686 // of the case are GEP instructions, then the cast does not need to be
1687 // generated explicitly, it will be folded into the GEP.
1688 if (CI.getType() == Type::LongTy &&
1689 (Op->getType() == Type::IntTy || Op->getType() == Type::UIntTy)) {
1690 bool AllUsesAreGEPs = true;
1691 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
1692 if (!isa<GetElementPtrInst>(*I)) {
1693 AllUsesAreGEPs = false;
1697 // No need to codegen this cast if all users are getelementptr instrs...
1698 if (AllUsesAreGEPs) return;
1701 unsigned DestReg = getReg(CI);
1702 MachineBasicBlock::iterator MI = BB->end();
1703 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
1706 /// emitCastOperation - Common code shared between visitCastInst and
1707 /// constant expression cast support.
1708 void ISel::emitCastOperation(MachineBasicBlock *BB,
1709 MachineBasicBlock::iterator &IP,
1710 Value *Src, const Type *DestTy,
1712 unsigned SrcReg = getReg(Src, BB, IP);
1713 const Type *SrcTy = Src->getType();
1714 unsigned SrcClass = getClassB(SrcTy);
1715 unsigned DestClass = getClassB(DestTy);
1717 // Implement casts to bool by using compare on the operand followed by set if
1718 // not zero on the result.
1719 if (DestTy == Type::BoolTy) {
1722 BMI(BB, IP, X86::TESTrr8, 2).addReg(SrcReg).addReg(SrcReg);
1725 BMI(BB, IP, X86::TESTrr16, 2).addReg(SrcReg).addReg(SrcReg);
1728 BMI(BB, IP, X86::TESTrr32, 2).addReg(SrcReg).addReg(SrcReg);
1731 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1732 BMI(BB, IP, X86::ORrr32, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
1736 assert(0 && "FIXME: implement cast FP to bool");
1740 // If the zero flag is not set, then the value is true, set the byte to
1742 BMI(BB, IP, X86::SETNEr, 1, DestReg);
1746 static const unsigned RegRegMove[] = {
1747 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV, X86::MOVrr32
1750 // Implement casts between values of the same type class (as determined by
1751 // getClass) by using a register-to-register move.
1752 if (SrcClass == DestClass) {
1753 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
1754 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
1755 } else if (SrcClass == cFP) {
1756 if (SrcTy == Type::FloatTy) { // double -> float
1757 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1758 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
1759 } else { // float -> double
1760 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1761 "Unknown cFP member!");
1762 // Truncate from double to float by storing to memory as short, then
1764 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
1765 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
1766 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1767 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
1769 } else if (SrcClass == cLong) {
1770 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1771 BMI(BB, IP, X86::MOVrr32, 1, DestReg+1).addReg(SrcReg+1);
1773 assert(0 && "Cannot handle this type of cast instruction!");
1779 // Handle cast of SMALLER int to LARGER int using a move with sign extension
1780 // or zero extension, depending on whether the source type was signed.
1781 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
1782 SrcClass < DestClass) {
1783 bool isLong = DestClass == cLong;
1784 if (isLong) DestClass = cInt;
1786 static const unsigned Opc[][4] = {
1787 { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, X86::MOVrr32 }, // s
1788 { X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16, X86::MOVrr32 } // u
1791 bool isUnsigned = SrcTy->isUnsigned();
1792 BMI(BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
1793 DestReg).addReg(SrcReg);
1795 if (isLong) { // Handle upper 32 bits as appropriate...
1796 if (isUnsigned) // Zero out top bits...
1797 BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1798 else // Sign extend bottom half...
1799 BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31);
1804 // Special case long -> int ...
1805 if (SrcClass == cLong && DestClass == cInt) {
1806 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1810 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
1811 // move out of AX or AL.
1812 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
1813 && SrcClass > DestClass) {
1814 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
1815 BMI(BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
1816 BMI(BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
1820 // Handle casts from integer to floating point now...
1821 if (DestClass == cFP) {
1822 // Promote the integer to a type supported by FLD. We do this because there
1823 // are no unsigned FLD instructions, so we must promote an unsigned value to
1824 // a larger signed value, then use FLD on the larger value.
1826 const Type *PromoteType = 0;
1827 unsigned PromoteOpcode;
1828 switch (SrcTy->getPrimitiveID()) {
1829 case Type::BoolTyID:
1830 case Type::SByteTyID:
1831 // We don't have the facilities for directly loading byte sized data from
1832 // memory (even signed). Promote it to 16 bits.
1833 PromoteType = Type::ShortTy;
1834 PromoteOpcode = X86::MOVSXr16r8;
1836 case Type::UByteTyID:
1837 PromoteType = Type::ShortTy;
1838 PromoteOpcode = X86::MOVZXr16r8;
1840 case Type::UShortTyID:
1841 PromoteType = Type::IntTy;
1842 PromoteOpcode = X86::MOVZXr32r16;
1844 case Type::UIntTyID: {
1845 // Make a 64 bit temporary... and zero out the top of it...
1846 unsigned TmpReg = makeAnotherReg(Type::LongTy);
1847 BMI(BB, IP, X86::MOVrr32, 1, TmpReg).addReg(SrcReg);
1848 BMI(BB, IP, X86::MOVir32, 1, TmpReg+1).addZImm(0);
1849 SrcTy = Type::LongTy;
1854 case Type::ULongTyID:
1855 assert("FIXME: not implemented: cast ulong X to fp type!");
1856 default: // No promotion needed...
1861 unsigned TmpReg = makeAnotherReg(PromoteType);
1862 BMI(BB, IP, SrcTy->isSigned() ? X86::MOVSXr16r8 : X86::MOVZXr16r8,
1863 1, TmpReg).addReg(SrcReg);
1864 SrcTy = PromoteType;
1865 SrcClass = getClass(PromoteType);
1869 // Spill the integer to memory and reload it from there...
1871 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
1873 if (SrcClass == cLong) {
1874 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5), FrameIdx).addReg(SrcReg);
1875 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5),
1876 FrameIdx, 4).addReg(SrcReg+1);
1878 static const unsigned Op1[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1879 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
1882 static const unsigned Op2[] =
1883 { 0/*byte*/, X86::FILDr16, X86::FILDr32, 0/*FP*/, X86::FILDr64 };
1884 addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
1888 // Handle casts from floating point to integer now...
1889 if (SrcClass == cFP) {
1890 // Change the floating point control register to use "round towards zero"
1891 // mode when truncating to an integer value.
1893 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1894 addFrameReference(BMI(BB, IP, X86::FNSTCWm16, 4), CWFrameIdx);
1896 // Load the old value of the high byte of the control word...
1897 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
1898 addFrameReference(BMI(BB, IP, X86::MOVmr8, 4, HighPartOfCW), CWFrameIdx, 1);
1900 // Set the high part to be round to zero...
1901 addFrameReference(BMI(BB, IP, X86::MOVim8, 5), CWFrameIdx, 1).addZImm(12);
1903 // Reload the modified control word now...
1904 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1906 // Restore the memory image of control word to original value
1907 addFrameReference(BMI(BB, IP, X86::MOVrm8, 5),
1908 CWFrameIdx, 1).addReg(HighPartOfCW);
1910 // We don't have the facilities for directly storing byte sized data to
1911 // memory. Promote it to 16 bits. We also must promote unsigned values to
1912 // larger classes because we only have signed FP stores.
1913 unsigned StoreClass = DestClass;
1914 const Type *StoreTy = DestTy;
1915 if (StoreClass == cByte || DestTy->isUnsigned())
1916 switch (StoreClass) {
1917 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
1918 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
1919 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
1920 // The following treatment of cLong may not be perfectly right,
1921 // but it survives chains of casts of the form
1922 // double->ulong->double.
1923 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
1924 default: assert(0 && "Unknown store class!");
1927 // Spill the integer to memory and reload it from there...
1929 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
1931 static const unsigned Op1[] =
1932 { 0, X86::FISTr16, X86::FISTr32, 0, X86::FISTPr64 };
1933 addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg);
1935 if (DestClass == cLong) {
1936 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg), FrameIdx);
1937 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg+1), FrameIdx, 4);
1939 static const unsigned Op2[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
1940 addFrameReference(BMI(BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
1943 // Reload the original control word now...
1944 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1948 // Anything we haven't handled already, we can't (yet) handle at all.
1949 assert(0 && "Unhandled cast instruction!");
1953 /// visitVANextInst - Implement the va_next instruction...
1955 void ISel::visitVANextInst(VANextInst &I) {
1956 unsigned VAList = getReg(I.getOperand(0));
1957 unsigned DestReg = getReg(I);
1960 switch (I.getArgType()->getPrimitiveID()) {
1963 assert(0 && "Error: bad type for va_next instruction!");
1965 case Type::PointerTyID:
1966 case Type::UIntTyID:
1970 case Type::ULongTyID:
1971 case Type::LongTyID:
1972 case Type::DoubleTyID:
1977 // Increment the VAList pointer...
1978 BuildMI(BB, X86::ADDri32, 2, DestReg).addReg(VAList).addZImm(Size);
1981 void ISel::visitVAArgInst(VAArgInst &I) {
1982 unsigned VAList = getReg(I.getOperand(0));
1983 unsigned DestReg = getReg(I);
1985 switch (I.getType()->getPrimitiveID()) {
1988 assert(0 && "Error: bad type for va_next instruction!");
1990 case Type::PointerTyID:
1991 case Type::UIntTyID:
1993 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
1995 case Type::ULongTyID:
1996 case Type::LongTyID:
1997 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
1998 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), VAList, 4);
2000 case Type::DoubleTyID:
2001 addDirectMem(BuildMI(BB, X86::FLDr64, 4, DestReg), VAList);
2007 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
2008 unsigned outputReg = getReg(I);
2009 MachineBasicBlock::iterator MI = BB->end();
2010 emitGEPOperation(BB, MI, I.getOperand(0),
2011 I.op_begin()+1, I.op_end(), outputReg);
2014 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
2015 MachineBasicBlock::iterator &IP,
2016 Value *Src, User::op_iterator IdxBegin,
2017 User::op_iterator IdxEnd, unsigned TargetReg) {
2018 const TargetData &TD = TM.getTargetData();
2019 const Type *Ty = Src->getType();
2020 unsigned BaseReg = getReg(Src, MBB, IP);
2022 // GEPs have zero or more indices; we must perform a struct access
2023 // or array access for each one.
2024 for (GetElementPtrInst::op_iterator oi = IdxBegin,
2025 oe = IdxEnd; oi != oe; ++oi) {
2027 unsigned NextReg = BaseReg;
2028 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2029 // It's a struct access. idx is the index into the structure,
2030 // which names the field. This index must have ubyte type.
2031 const ConstantUInt *CUI = cast<ConstantUInt>(idx);
2032 assert(CUI->getType() == Type::UByteTy
2033 && "Funny-looking structure index in GEP");
2034 // Use the TargetData structure to pick out what the layout of
2035 // the structure is in memory. Since the structure index must
2036 // be constant, we can get its value and use it to find the
2037 // right byte offset from the StructLayout class's list of
2038 // structure member offsets.
2039 unsigned idxValue = CUI->getValue();
2040 unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue];
2042 NextReg = makeAnotherReg(Type::UIntTy);
2043 // Emit an ADD to add FieldOff to the basePtr.
2044 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff);
2046 // The next type is the member of the structure selected by the
2048 Ty = StTy->getElementTypes()[idxValue];
2049 } else if (const SequentialType *SqTy = cast<SequentialType>(Ty)) {
2050 // It's an array or pointer access: [ArraySize x ElementType].
2052 // idx is the index into the array. Unlike with structure
2053 // indices, we may not know its actual value at code-generation
2055 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
2057 // Most GEP instructions use a [cast (int/uint) to LongTy] as their
2058 // operand on X86. Handle this case directly now...
2059 if (CastInst *CI = dyn_cast<CastInst>(idx))
2060 if (CI->getOperand(0)->getType() == Type::IntTy ||
2061 CI->getOperand(0)->getType() == Type::UIntTy)
2062 idx = CI->getOperand(0);
2064 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
2065 // must find the size of the pointed-to type (Not coincidentally, the next
2066 // type is the type of the elements in the array).
2067 Ty = SqTy->getElementType();
2068 unsigned elementSize = TD.getTypeSize(Ty);
2070 // If idxReg is a constant, we don't need to perform the multiply!
2071 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
2072 if (!CSI->isNullValue()) {
2073 unsigned Offset = elementSize*CSI->getValue();
2074 NextReg = makeAnotherReg(Type::UIntTy);
2075 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(Offset);
2077 } else if (elementSize == 1) {
2078 // If the element size is 1, we don't have to multiply, just add
2079 unsigned idxReg = getReg(idx, MBB, IP);
2080 NextReg = makeAnotherReg(Type::UIntTy);
2081 BMI(MBB, IP, X86::ADDrr32, 2, NextReg).addReg(BaseReg).addReg(idxReg);
2083 unsigned idxReg = getReg(idx, MBB, IP);
2084 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
2086 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
2088 // Emit an ADD to add OffsetReg to the basePtr.
2089 NextReg = makeAnotherReg(Type::UIntTy);
2090 BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg);
2093 // Now that we are here, further indices refer to subtypes of this
2094 // one, so we don't need to worry about BaseReg itself, anymore.
2097 // After we have processed all the indices, the result is left in
2098 // BaseReg. Move it to the register where we were expected to
2099 // put the answer. A 32-bit move should do it, because we are in
2101 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
2105 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2106 /// frame manager, otherwise do it the hard way.
2108 void ISel::visitAllocaInst(AllocaInst &I) {
2109 // Find the data size of the alloca inst's getAllocatedType.
2110 const Type *Ty = I.getAllocatedType();
2111 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2113 // If this is a fixed size alloca in the entry block for the function,
2114 // statically stack allocate the space.
2116 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
2117 if (I.getParent() == I.getParent()->getParent()->begin()) {
2118 TySize *= CUI->getValue(); // Get total allocated size...
2119 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
2121 // Create a new stack object using the frame manager...
2122 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
2123 addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx);
2128 // Create a register to hold the temporary result of multiplying the type size
2129 // constant by the variable amount.
2130 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2131 unsigned SrcReg1 = getReg(I.getArraySize());
2133 // TotalSizeReg = mul <numelements>, <TypeSize>
2134 MachineBasicBlock::iterator MBBI = BB->end();
2135 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
2137 // AddedSize = add <TotalSizeReg>, 15
2138 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2139 BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15);
2141 // AlignedSize = and <AddedSize>, ~15
2142 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2143 BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15);
2145 // Subtract size from stack pointer, thereby allocating some space.
2146 BuildMI(BB, X86::SUBrr32, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
2148 // Put a pointer to the space into the result register, by copying
2149 // the stack pointer.
2150 BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP);
2152 // Inform the Frame Information that we have just allocated a variable-sized
2154 F->getFrameInfo()->CreateVariableSizedObject();
2157 /// visitMallocInst - Malloc instructions are code generated into direct calls
2158 /// to the library malloc.
2160 void ISel::visitMallocInst(MallocInst &I) {
2161 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2164 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2165 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2167 Arg = makeAnotherReg(Type::UIntTy);
2168 unsigned Op0Reg = getReg(I.getOperand(0));
2169 MachineBasicBlock::iterator MBBI = BB->end();
2170 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
2173 std::vector<ValueRecord> Args;
2174 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2175 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2176 1).addExternalSymbol("malloc", true);
2177 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
2181 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2184 void ISel::visitFreeInst(FreeInst &I) {
2185 std::vector<ValueRecord> Args;
2186 Args.push_back(ValueRecord(I.getOperand(0)));
2187 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2188 1).addExternalSymbol("free", true);
2189 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
2192 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
2193 /// into a machine code representation is a very simple peep-hole fashion. The
2194 /// generated code sucks but the implementation is nice and simple.
2196 FunctionPass *llvm::createX86SimpleInstructionSelector(TargetMachine &TM) {
2197 return new ISel(TM);