1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 target
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/Instructions.h"
12 #include "llvm/DerivedTypes.h"
13 #include "llvm/Constants.h"
14 #include "llvm/Pass.h"
15 #include "llvm/Intrinsics.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/SSARegMap.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "llvm/Support/InstVisitor.h"
25 /// BMI - A special BuildMI variant that takes an iterator to insert the
26 /// instruction at as well as a basic block. This is the version for when you
27 /// have a destination register in mind.
28 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
29 MachineBasicBlock::iterator &I,
30 int Opcode, unsigned NumOperands,
32 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
33 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
34 I = MBB->insert(I, MI)+1;
35 return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
38 /// BMI - A special BuildMI variant that takes an iterator to insert the
39 /// instruction at as well as a basic block.
40 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
41 MachineBasicBlock::iterator &I,
42 int Opcode, unsigned NumOperands) {
43 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
44 MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
45 I = MBB->insert(I, MI)+1;
46 return MachineInstrBuilder(MI);
51 struct ISel : public FunctionPass, InstVisitor<ISel> {
53 MachineFunction *F; // The function we are compiling into
54 MachineBasicBlock *BB; // The current MBB we are compiling
55 int VarArgsFrameIndex; // FrameIndex for start of varargs area
57 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
59 // MBBMap - Mapping between LLVM BB -> Machine BB
60 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
62 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
64 /// runOnFunction - Top level implementation of instruction selection for
65 /// the entire function.
67 bool runOnFunction(Function &Fn) {
68 F = &MachineFunction::construct(&Fn, TM);
70 // Create all of the machine basic blocks for the function...
71 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
72 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
76 // Copy incoming arguments off of the stack...
77 LoadArgumentsToVirtualRegs(Fn);
79 // Instruction select everything except PHI nodes
82 // Select the PHI nodes
88 // We always build a machine code representation for the function
92 virtual const char *getPassName() const {
93 return "X86 Simple Instruction Selection";
96 /// visitBasicBlock - This method is called when we are visiting a new basic
97 /// block. This simply creates a new MachineBasicBlock to emit code into
98 /// and adds it to the current MachineFunction. Subsequent visit* for
99 /// instructions will be invoked for all instructions in the basic block.
101 void visitBasicBlock(BasicBlock &LLVM_BB) {
102 BB = MBBMap[&LLVM_BB];
105 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
106 /// from the stack into virtual registers.
108 void LoadArgumentsToVirtualRegs(Function &F);
110 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
111 /// because we have to generate our sources into the source basic blocks,
112 /// not the current one.
114 void SelectPHINodes();
116 // Visitation methods for various instructions. These methods simply emit
117 // fixed X86 code for each instruction.
120 // Control flow operators
121 void visitReturnInst(ReturnInst &RI);
122 void visitBranchInst(BranchInst &BI);
128 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
129 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
131 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
132 const std::vector<ValueRecord> &Args);
133 void visitCallInst(CallInst &I);
134 void visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &I);
136 // Arithmetic operators
137 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
138 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
139 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
140 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
141 unsigned DestReg, const Type *DestTy,
142 unsigned Op0Reg, unsigned Op1Reg);
143 void visitMul(BinaryOperator &B);
145 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
146 void visitRem(BinaryOperator &B) { visitDivRem(B); }
147 void visitDivRem(BinaryOperator &B);
150 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
151 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
152 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
154 // Comparison operators...
155 void visitSetCondInst(SetCondInst &I);
156 bool EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1,
157 MachineBasicBlock *MBB,
158 MachineBasicBlock::iterator &MBBI);
160 // Memory Instructions
161 MachineInstr *doFPLoad(MachineBasicBlock *MBB,
162 MachineBasicBlock::iterator &MBBI,
163 const Type *Ty, unsigned DestReg);
164 void visitLoadInst(LoadInst &I);
165 void doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg);
166 void visitStoreInst(StoreInst &I);
167 void visitGetElementPtrInst(GetElementPtrInst &I);
168 void visitAllocaInst(AllocaInst &I);
169 void visitMallocInst(MallocInst &I);
170 void visitFreeInst(FreeInst &I);
173 void visitShiftInst(ShiftInst &I);
174 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
175 void visitCastInst(CastInst &I);
176 void visitVarArgInst(VarArgInst &I);
178 void visitInstruction(Instruction &I) {
179 std::cerr << "Cannot instruction select: " << I;
183 /// promote32 - Make a value 32-bits wide, and put it somewhere.
185 void promote32(unsigned targetReg, const ValueRecord &VR);
187 /// EmitByteSwap - Byteswap SrcReg into DestReg.
189 void EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class);
191 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
192 /// constant expression GEP support.
194 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator&IP,
195 Value *Src, User::op_iterator IdxBegin,
196 User::op_iterator IdxEnd, unsigned TargetReg);
198 /// emitCastOperation - Common code shared between visitCastInst and
199 /// constant expression cast support.
200 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
201 Value *Src, const Type *DestTy, unsigned TargetReg);
203 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
204 /// and constant expression support.
205 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
206 MachineBasicBlock::iterator &IP,
207 Value *Op0, Value *Op1,
208 unsigned OperatorClass, unsigned TargetReg);
210 /// emitSetCCOperation - Common code shared between visitSetCondInst and
211 /// constant expression support.
212 void emitSetCCOperation(MachineBasicBlock *BB,
213 MachineBasicBlock::iterator &IP,
214 Value *Op0, Value *Op1, unsigned Opcode,
218 /// copyConstantToRegister - Output the instructions required to put the
219 /// specified constant into the specified register.
221 void copyConstantToRegister(MachineBasicBlock *MBB,
222 MachineBasicBlock::iterator &MBBI,
223 Constant *C, unsigned Reg);
225 /// makeAnotherReg - This method returns the next register number we haven't
228 /// Long values are handled somewhat specially. They are always allocated
229 /// as pairs of 32 bit integer values. The register number returned is the
230 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
231 /// of the long value.
233 unsigned makeAnotherReg(const Type *Ty) {
234 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
235 "Current target doesn't have X86 reg info??");
236 const X86RegisterInfo *MRI =
237 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
238 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
239 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
240 // Create the lower part
241 F->getSSARegMap()->createVirtualRegister(RC);
242 // Create the upper part.
243 return F->getSSARegMap()->createVirtualRegister(RC)-1;
246 // Add the mapping of regnumber => reg class to MachineFunction
247 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
248 return F->getSSARegMap()->createVirtualRegister(RC);
251 /// getReg - This method turns an LLVM value into a register number. This
252 /// is guaranteed to produce the same register number for a particular value
253 /// every time it is queried.
255 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
256 unsigned getReg(Value *V) {
257 // Just append to the end of the current bb.
258 MachineBasicBlock::iterator It = BB->end();
259 return getReg(V, BB, It);
261 unsigned getReg(Value *V, MachineBasicBlock *MBB,
262 MachineBasicBlock::iterator &IPt) {
263 unsigned &Reg = RegMap[V];
265 Reg = makeAnotherReg(V->getType());
269 // If this operand is a constant, emit the code to copy the constant into
270 // the register here...
272 if (Constant *C = dyn_cast<Constant>(V)) {
273 copyConstantToRegister(MBB, IPt, C, Reg);
274 RegMap.erase(V); // Assign a new name to this constant if ref'd again
275 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
276 // Move the address of the global into the register
277 BMI(MBB, IPt, X86::MOVir32, 1, Reg).addGlobalAddress(GV);
278 RegMap.erase(V); // Assign a new name to this address if ref'd again
286 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
290 cByte, cShort, cInt, cFP, cLong
293 /// getClass - Turn a primitive type into a "class" number which is based on the
294 /// size of the type, and whether or not it is floating point.
296 static inline TypeClass getClass(const Type *Ty) {
297 switch (Ty->getPrimitiveID()) {
298 case Type::SByteTyID:
299 case Type::UByteTyID: return cByte; // Byte operands are class #0
300 case Type::ShortTyID:
301 case Type::UShortTyID: return cShort; // Short operands are class #1
304 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
306 case Type::FloatTyID:
307 case Type::DoubleTyID: return cFP; // Floating Point is #3
310 case Type::ULongTyID: return cLong; // Longs are class #4
312 assert(0 && "Invalid type to getClass!");
313 return cByte; // not reached
317 // getClassB - Just like getClass, but treat boolean values as bytes.
318 static inline TypeClass getClassB(const Type *Ty) {
319 if (Ty == Type::BoolTy) return cByte;
324 /// copyConstantToRegister - Output the instructions required to put the
325 /// specified constant into the specified register.
327 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
328 MachineBasicBlock::iterator &IP,
329 Constant *C, unsigned R) {
330 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
332 switch (CE->getOpcode()) {
333 case Instruction::GetElementPtr:
334 emitGEPOperation(MBB, IP, CE->getOperand(0),
335 CE->op_begin()+1, CE->op_end(), R);
337 case Instruction::Cast:
338 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
341 case Instruction::Xor: ++Class; // FALL THROUGH
342 case Instruction::Or: ++Class; // FALL THROUGH
343 case Instruction::And: ++Class; // FALL THROUGH
344 case Instruction::Sub: ++Class; // FALL THROUGH
345 case Instruction::Add:
346 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
350 case Instruction::SetNE:
351 case Instruction::SetEQ:
352 case Instruction::SetLT:
353 case Instruction::SetGT:
354 case Instruction::SetLE:
355 case Instruction::SetGE:
356 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
361 std::cerr << "Offending expr: " << C << "\n";
362 assert(0 && "Constant expressions not yet handled!\n");
366 if (C->getType()->isIntegral()) {
367 unsigned Class = getClassB(C->getType());
369 if (Class == cLong) {
370 // Copy the value into the register pair.
371 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
372 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(Val & 0xFFFFFFFF);
373 BMI(MBB, IP, X86::MOVir32, 1, R+1).addZImm(Val >> 32);
377 assert(Class <= cInt && "Type not handled yet!");
379 static const unsigned IntegralOpcodeTab[] = {
380 X86::MOVir8, X86::MOVir16, X86::MOVir32
383 if (C->getType() == Type::BoolTy) {
384 BMI(MBB, IP, X86::MOVir8, 1, R).addZImm(C == ConstantBool::True);
386 ConstantInt *CI = cast<ConstantInt>(C);
387 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CI->getRawValue());
389 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
390 double Value = CFP->getValue();
392 BMI(MBB, IP, X86::FLD0, 0, R);
393 else if (Value == +1.0)
394 BMI(MBB, IP, X86::FLD1, 0, R);
396 // Otherwise we need to spill the constant to memory...
397 MachineConstantPool *CP = F->getConstantPool();
398 unsigned CPI = CP->getConstantPoolIndex(CFP);
399 addConstantPoolReference(doFPLoad(MBB, IP, CFP->getType(), R), CPI);
402 } else if (isa<ConstantPointerNull>(C)) {
403 // Copy zero (null pointer) to the register.
404 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0);
405 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
406 unsigned SrcReg = getReg(CPR->getValue(), MBB, IP);
407 BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg);
409 std::cerr << "Offending constant: " << C << "\n";
410 assert(0 && "Type not handled yet!");
414 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
415 /// the stack into virtual registers.
417 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
418 // Emit instructions to load the arguments... On entry to a function on the
419 // X86, the stack frame looks like this:
421 // [ESP] -- return address
422 // [ESP + 4] -- first argument (leftmost lexically)
423 // [ESP + 8] -- second argument, if first argument is four bytes in size
426 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
427 MachineFrameInfo *MFI = F->getFrameInfo();
429 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
430 unsigned Reg = getReg(*I);
432 int FI; // Frame object index
433 switch (getClassB(I->getType())) {
435 FI = MFI->CreateFixedObject(1, ArgOffset);
436 addFrameReference(BuildMI(BB, X86::MOVmr8, 4, Reg), FI);
439 FI = MFI->CreateFixedObject(2, ArgOffset);
440 addFrameReference(BuildMI(BB, X86::MOVmr16, 4, Reg), FI);
443 FI = MFI->CreateFixedObject(4, ArgOffset);
444 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
447 FI = MFI->CreateFixedObject(8, ArgOffset);
448 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
449 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg+1), FI, 4);
450 ArgOffset += 4; // longs require 4 additional bytes
454 if (I->getType() == Type::FloatTy) {
455 Opcode = X86::FLDr32;
456 FI = MFI->CreateFixedObject(4, ArgOffset);
458 Opcode = X86::FLDr64;
459 FI = MFI->CreateFixedObject(8, ArgOffset);
460 ArgOffset += 4; // doubles require 4 additional bytes
462 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
465 assert(0 && "Unhandled argument type!");
467 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
470 // If the function takes variable number of arguments, add a frame offset for
471 // the start of the first vararg value... this is used to expand
473 if (Fn.getFunctionType()->isVarArg())
474 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
478 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
479 /// because we have to generate our sources into the source basic blocks, not
482 void ISel::SelectPHINodes() {
483 const TargetInstrInfo &TII = TM.getInstrInfo();
484 const Function &LF = *F->getFunction(); // The LLVM function...
485 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
486 const BasicBlock *BB = I;
487 MachineBasicBlock *MBB = MBBMap[I];
489 // Loop over all of the PHI nodes in the LLVM basic block...
490 unsigned NumPHIs = 0;
491 for (BasicBlock::const_iterator I = BB->begin();
492 PHINode *PN = (PHINode*)dyn_cast<PHINode>(I); ++I) {
494 // Create a new machine instr PHI node, and insert it.
495 unsigned PHIReg = getReg(*PN);
496 MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
497 MBB->insert(MBB->begin()+NumPHIs++, PhiMI);
499 MachineInstr *LongPhiMI = 0;
500 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
501 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
502 MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
505 // PHIValues - Map of blocks to incoming virtual registers. We use this
506 // so that we only initialize one incoming value for a particular block,
507 // even if the block has multiple entries in the PHI node.
509 std::map<MachineBasicBlock*, unsigned> PHIValues;
511 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
512 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
514 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
515 PHIValues.lower_bound(PredMBB);
517 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
518 // We already inserted an initialization of the register for this
519 // predecessor. Recycle it.
520 ValReg = EntryIt->second;
523 // Get the incoming value into a virtual register. If it is not
524 // already available in a virtual register, insert the computation
527 MachineBasicBlock::iterator PI = PredMBB->end();
528 while (PI != PredMBB->begin() &&
529 TII.isTerminatorInstr((*(PI-1))->getOpcode()))
531 ValReg = getReg(PN->getIncomingValue(i), PredMBB, PI);
533 // Remember that we inserted a value for this PHI for this predecessor
534 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
537 PhiMI->addRegOperand(ValReg);
538 PhiMI->addMachineBasicBlockOperand(PredMBB);
540 LongPhiMI->addRegOperand(ValReg+1);
541 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
548 // canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
549 // the conditional branch instruction which is the only user of the cc
550 // instruction. This is the case if the conditional branch is the only user of
551 // the setcc, and if the setcc is in the same basic block as the conditional
552 // branch. We also don't handle long arguments below, so we reject them here as
555 static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
556 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
557 if (SCI->hasOneUse() && isa<BranchInst>(SCI->use_back()) &&
558 SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
559 const Type *Ty = SCI->getOperand(0)->getType();
560 if (Ty != Type::LongTy && Ty != Type::ULongTy)
566 // Return a fixed numbering for setcc instructions which does not depend on the
567 // order of the opcodes.
569 static unsigned getSetCCNumber(unsigned Opcode) {
571 default: assert(0 && "Unknown setcc instruction!");
572 case Instruction::SetEQ: return 0;
573 case Instruction::SetNE: return 1;
574 case Instruction::SetLT: return 2;
575 case Instruction::SetGE: return 3;
576 case Instruction::SetGT: return 4;
577 case Instruction::SetLE: return 5;
581 // LLVM -> X86 signed X86 unsigned
582 // ----- ---------- ------------
583 // seteq -> sete sete
584 // setne -> setne setne
585 // setlt -> setl setb
586 // setge -> setge setae
587 // setgt -> setg seta
588 // setle -> setle setbe
589 static const unsigned SetCCOpcodeTab[2][6] = {
590 {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr},
591 {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr},
594 bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1,
595 MachineBasicBlock *MBB,
596 MachineBasicBlock::iterator &IP) {
597 // The arguments are already supposed to be of the same type.
598 const Type *CompTy = Op0->getType();
599 bool isSigned = CompTy->isSigned();
600 unsigned Class = getClassB(CompTy);
601 unsigned Op0r = getReg(Op0, MBB, IP);
603 // Special case handling of: cmp R, i
604 if (Class == cByte || Class == cShort || Class == cInt)
605 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
606 uint64_t Op1v = cast<ConstantInt>(CI)->getRawValue();
608 // Mask off any upper bits of the constant, if there are any...
609 Op1v &= (1ULL << (8 << Class)) - 1;
612 case cByte: BMI(MBB,IP, X86::CMPri8, 2).addReg(Op0r).addZImm(Op1v);break;
613 case cShort: BMI(MBB,IP, X86::CMPri16,2).addReg(Op0r).addZImm(Op1v);break;
614 case cInt: BMI(MBB,IP, X86::CMPri32,2).addReg(Op0r).addZImm(Op1v);break;
616 assert(0 && "Invalid class!");
621 unsigned Op1r = getReg(Op1, MBB, IP);
623 default: assert(0 && "Unknown type class!");
624 // Emit: cmp <var1>, <var2> (do the comparison). We can
625 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
628 BMI(MBB, IP, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r);
631 BMI(MBB, IP, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r);
634 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
637 BMI(MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
638 BMI(MBB, IP, X86::FNSTSWr8, 0);
639 BMI(MBB, IP, X86::SAHF, 1);
640 isSigned = false; // Compare with unsigned operators
644 if (OpNum < 2) { // seteq, setne
645 unsigned LoTmp = makeAnotherReg(Type::IntTy);
646 unsigned HiTmp = makeAnotherReg(Type::IntTy);
647 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
648 BMI(MBB, IP, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r);
649 BMI(MBB, IP, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
650 BMI(MBB, IP, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
651 break; // Allow the sete or setne to be generated from flags set by OR
653 // Emit a sequence of code which compares the high and low parts once
654 // each, then uses a conditional move to handle the overflow case. For
655 // example, a setlt for long would generate code like this:
657 // AL = lo(op1) < lo(op2) // Signedness depends on operands
658 // BL = hi(op1) < hi(op2) // Always unsigned comparison
659 // dest = hi(op1) == hi(op2) ? AL : BL;
662 // FIXME: This would be much better if we had hierarchical register
663 // classes! Until then, hardcode registers so that we can deal with their
664 // aliases (because we don't have conditional byte moves).
666 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
667 BMI(MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
668 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
669 BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
670 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
671 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
672 BMI(MBB, IP, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
673 // NOTE: visitSetCondInst knows that the value is dumped into the BL
674 // register at this point for long values...
682 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
683 /// register, then move it to wherever the result should be.
685 void ISel::visitSetCondInst(SetCondInst &I) {
686 if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
688 unsigned DestReg = getReg(I);
689 MachineBasicBlock::iterator MII = BB->end();
690 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
694 /// emitSetCCOperation - Common code shared between visitSetCondInst and
695 /// constant expression support.
696 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
697 MachineBasicBlock::iterator &IP,
698 Value *Op0, Value *Op1, unsigned Opcode,
699 unsigned TargetReg) {
700 unsigned OpNum = getSetCCNumber(Opcode);
701 bool isSigned = EmitComparisonGetSignedness(OpNum, Op0, Op1, MBB, IP);
703 if (getClassB(Op0->getType()) != cLong || OpNum < 2) {
704 // Handle normal comparisons with a setcc instruction...
705 BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
707 // Handle long comparisons by copying the value which is already in BL into
708 // the register we want...
709 BMI(MBB, IP, X86::MOVrr8, 1, TargetReg).addReg(X86::BL);
716 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
717 /// operand, in the specified target register.
718 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
719 bool isUnsigned = VR.Ty->isUnsigned();
721 // Make sure we have the register number for this value...
722 unsigned Reg = VR.Val ? getReg(VR.Val) : VR.Reg;
724 switch (getClassB(VR.Ty)) {
726 // Extend value into target register (8->32)
728 BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(Reg);
730 BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(Reg);
733 // Extend value into target register (16->32)
735 BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(Reg);
737 BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(Reg);
740 // Move value into target register (32->32)
741 BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(Reg);
744 assert(0 && "Unpromotable operand class in promote32");
748 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
749 /// we have the following possibilities:
751 /// ret void: No return value, simply emit a 'ret' instruction
752 /// ret sbyte, ubyte : Extend value into EAX and return
753 /// ret short, ushort: Extend value into EAX and return
754 /// ret int, uint : Move value into EAX and return
755 /// ret pointer : Move value into EAX and return
756 /// ret long, ulong : Move value into EAX/EDX and return
757 /// ret float/double : Top of FP stack
759 void ISel::visitReturnInst(ReturnInst &I) {
760 if (I.getNumOperands() == 0) {
761 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
765 Value *RetVal = I.getOperand(0);
766 unsigned RetReg = getReg(RetVal);
767 switch (getClassB(RetVal->getType())) {
768 case cByte: // integral return values: extend or move into EAX and return
771 promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
772 // Declare that EAX is live on exit
773 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
775 case cFP: // Floats & Doubles: Return in ST(0)
776 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
777 // Declare that top-of-stack is live on exit
778 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
781 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
782 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
783 // Declare that EAX & EDX are live on exit
784 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX).addReg(X86::ESP);
789 // Emit a 'ret' instruction
790 BuildMI(BB, X86::RET, 0);
793 // getBlockAfter - Return the basic block which occurs lexically after the
795 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
796 Function::iterator I = BB; ++I; // Get iterator to next block
797 return I != BB->getParent()->end() ? &*I : 0;
800 /// visitBranchInst - Handle conditional and unconditional branches here. Note
801 /// that since code layout is frozen at this point, that if we are trying to
802 /// jump to a block that is the immediate successor of the current block, we can
803 /// just make a fall-through (but we don't currently).
805 void ISel::visitBranchInst(BranchInst &BI) {
806 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
808 if (!BI.isConditional()) { // Unconditional branch?
809 if (BI.getSuccessor(0) != NextBB)
810 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
814 // See if we can fold the setcc into the branch itself...
815 SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
817 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
818 // computed some other way...
819 unsigned condReg = getReg(BI.getCondition());
820 BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
821 if (BI.getSuccessor(1) == NextBB) {
822 if (BI.getSuccessor(0) != NextBB)
823 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
825 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
827 if (BI.getSuccessor(0) != NextBB)
828 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
833 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
834 MachineBasicBlock::iterator MII = BB->end();
835 bool isSigned = EmitComparisonGetSignedness(OpNum, SCI->getOperand(0),
836 SCI->getOperand(1), BB, MII);
838 // LLVM -> X86 signed X86 unsigned
839 // ----- ---------- ------------
846 static const unsigned OpcodeTab[2][6] = {
847 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE },
848 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE },
851 if (BI.getSuccessor(0) != NextBB) {
852 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
853 if (BI.getSuccessor(1) != NextBB)
854 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
856 // Change to the inverse condition...
857 if (BI.getSuccessor(1) != NextBB) {
859 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
865 /// doCall - This emits an abstract call instruction, setting up the arguments
866 /// and the return value as appropriate. For the actual function call itself,
867 /// it inserts the specified CallMI instruction into the stream.
869 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
870 const std::vector<ValueRecord> &Args) {
872 // Count how many bytes are to be pushed on the stack...
873 unsigned NumBytes = 0;
876 for (unsigned i = 0, e = Args.size(); i != e; ++i)
877 switch (getClassB(Args[i].Ty)) {
878 case cByte: case cShort: case cInt:
879 NumBytes += 4; break;
881 NumBytes += 8; break;
883 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
885 default: assert(0 && "Unknown class!");
888 // Adjust the stack pointer for the new arguments...
889 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes);
891 // Arguments go on the stack in reverse order, as specified by the ABI.
892 unsigned ArgOffset = 0;
893 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
894 unsigned ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
895 switch (getClassB(Args[i].Ty)) {
898 // Promote arg to 32 bits wide into a temporary register...
899 unsigned R = makeAnotherReg(Type::UIntTy);
900 promote32(R, Args[i]);
901 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
902 X86::ESP, ArgOffset).addReg(R);
906 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
907 X86::ESP, ArgOffset).addReg(ArgReg);
910 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
911 X86::ESP, ArgOffset).addReg(ArgReg);
912 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
913 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
914 ArgOffset += 4; // 8 byte entry, not 4.
918 if (Args[i].Ty == Type::FloatTy) {
919 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
920 X86::ESP, ArgOffset).addReg(ArgReg);
922 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
923 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
924 X86::ESP, ArgOffset).addReg(ArgReg);
925 ArgOffset += 4; // 8 byte entry, not 4.
929 default: assert(0 && "Unknown class!");
934 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(0);
937 BB->push_back(CallMI);
939 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes);
941 // If there is a return value, scavenge the result from the location the call
944 if (Ret.Ty != Type::VoidTy) {
945 unsigned DestClass = getClassB(Ret.Ty);
950 // Integral results are in %eax, or the appropriate portion
952 static const unsigned regRegMove[] = {
953 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
955 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
956 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
959 case cFP: // Floating-point return values live in %ST(0)
960 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
962 case cLong: // Long values are left in EDX:EAX
963 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg).addReg(X86::EAX);
964 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg+1).addReg(X86::EDX);
966 default: assert(0 && "Unknown class!");
972 /// visitCallInst - Push args on stack and do a procedure call instruction.
973 void ISel::visitCallInst(CallInst &CI) {
974 MachineInstr *TheCall;
975 if (Function *F = CI.getCalledFunction()) {
976 // Is it an intrinsic function call?
977 if (LLVMIntrinsic::ID ID = (LLVMIntrinsic::ID)F->getIntrinsicID()) {
978 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
982 // Emit a CALL instruction with PC-relative displacement.
983 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
984 } else { // Emit an indirect call...
985 unsigned Reg = getReg(CI.getCalledValue());
986 TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg);
989 std::vector<ValueRecord> Args;
990 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
991 Args.push_back(ValueRecord(CI.getOperand(i)));
993 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
994 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
998 void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) {
999 unsigned TmpReg1, TmpReg2;
1001 case LLVMIntrinsic::va_start:
1002 // Get the address of the first vararg value...
1003 TmpReg1 = makeAnotherReg(Type::UIntTy);
1004 addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
1005 TmpReg2 = getReg(CI.getOperand(1));
1006 addDirectMem(BuildMI(BB, X86::MOVrm32, 5), TmpReg2).addReg(TmpReg1);
1009 case LLVMIntrinsic::va_end: return; // Noop on X86
1010 case LLVMIntrinsic::va_copy:
1011 TmpReg1 = getReg(CI.getOperand(2)); // Get existing va_list
1012 TmpReg2 = getReg(CI.getOperand(1)); // Get va_list* to store into
1013 addDirectMem(BuildMI(BB, X86::MOVrm32, 5), TmpReg2).addReg(TmpReg1);
1016 case LLVMIntrinsic::longjmp:
1017 case LLVMIntrinsic::siglongjmp:
1018 BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("abort", true);
1021 case LLVMIntrinsic::setjmp:
1022 case LLVMIntrinsic::sigsetjmp:
1023 // Setjmp always returns zero...
1024 BuildMI(BB, X86::MOVir32, 1, getReg(CI)).addZImm(0);
1026 default: assert(0 && "Unknown intrinsic for X86!");
1031 /// visitSimpleBinary - Implement simple binary operators for integral types...
1032 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1034 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1035 unsigned DestReg = getReg(B);
1036 MachineBasicBlock::iterator MI = BB->end();
1037 emitSimpleBinaryOperation(BB, MI, B.getOperand(0), B.getOperand(1),
1038 OperatorClass, DestReg);
1041 /// visitSimpleBinary - Implement simple binary operators for integral types...
1042 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
1045 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1046 /// and constant expression support.
1047 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *BB,
1048 MachineBasicBlock::iterator &IP,
1049 Value *Op0, Value *Op1,
1050 unsigned OperatorClass,unsigned TargetReg){
1051 unsigned Class = getClassB(Op0->getType());
1052 if (!isa<ConstantInt>(Op1) || Class == cLong) {
1053 static const unsigned OpcodeTab[][4] = {
1054 // Arithmetic operators
1055 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
1056 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
1058 // Bitwise operators
1059 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
1060 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
1061 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
1064 bool isLong = false;
1065 if (Class == cLong) {
1067 Class = cInt; // Bottom 32 bits are handled just like ints
1070 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1071 assert(Opcode && "Floating point arguments to logical inst?");
1072 unsigned Op0r = getReg(Op0, BB, IP);
1073 unsigned Op1r = getReg(Op1, BB, IP);
1074 BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addReg(Op1r);
1076 if (isLong) { // Handle the upper 32 bits of long values...
1077 static const unsigned TopTab[] = {
1078 X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
1080 BMI(BB, IP, TopTab[OperatorClass], 2,
1081 TargetReg+1).addReg(Op0r+1).addReg(Op1r+1);
1084 // Special case: op Reg, <const>
1085 ConstantInt *Op1C = cast<ConstantInt>(Op1);
1087 static const unsigned OpcodeTab[][3] = {
1088 // Arithmetic operators
1089 { X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
1090 { X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
1092 // Bitwise operators
1093 { X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
1094 { X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
1095 { X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
1098 assert(Class < 3 && "General code handles 64-bit integer types!");
1099 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1100 unsigned Op0r = getReg(Op0, BB, IP);
1101 uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
1103 // Mask off any upper bits of the constant, if there are any...
1104 Op1v &= (1ULL << (8 << Class)) - 1;
1105 BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addZImm(Op1v);
1109 /// doMultiply - Emit appropriate instructions to multiply together the
1110 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1111 /// result should be given as DestTy.
1113 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
1114 unsigned DestReg, const Type *DestTy,
1115 unsigned op0Reg, unsigned op1Reg) {
1116 unsigned Class = getClass(DestTy);
1118 case cFP: // Floating point multiply
1119 BMI(BB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1123 BMI(BB, MBBI, Class == cInt ? X86::IMULr32 : X86::IMULr16, 2, DestReg)
1124 .addReg(op0Reg).addReg(op1Reg);
1127 // Must use the MUL instruction, which forces use of AL...
1128 BMI(MBB, MBBI, X86::MOVrr8, 1, X86::AL).addReg(op0Reg);
1129 BMI(MBB, MBBI, X86::MULr8, 1).addReg(op1Reg);
1130 BMI(MBB, MBBI, X86::MOVrr8, 1, DestReg).addReg(X86::AL);
1133 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
1137 /// visitMul - Multiplies are not simple binary operators because they must deal
1138 /// with the EAX register explicitly.
1140 void ISel::visitMul(BinaryOperator &I) {
1141 unsigned Op0Reg = getReg(I.getOperand(0));
1142 unsigned Op1Reg = getReg(I.getOperand(1));
1143 unsigned DestReg = getReg(I);
1145 // Simple scalar multiply?
1146 if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
1147 MachineBasicBlock::iterator MBBI = BB->end();
1148 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
1150 // Long value. We have to do things the hard way...
1151 // Multiply the two low parts... capturing carry into EDX
1152 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
1153 BuildMI(BB, X86::MULr32, 1).addReg(Op1Reg); // AL*BL
1155 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1156 BuildMI(BB, X86::MOVrr32, 1, DestReg).addReg(X86::EAX); // AL*BL
1157 BuildMI(BB, X86::MOVrr32, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32
1159 MachineBasicBlock::iterator MBBI = BB->end();
1160 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
1161 BMI(BB, MBBI, X86::IMULr32, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
1163 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1164 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
1165 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1168 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1169 BMI(BB, MBBI, X86::IMULr32, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
1171 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1172 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1177 /// visitDivRem - Handle division and remainder instructions... these
1178 /// instruction both require the same instructions to be generated, they just
1179 /// select the result from a different register. Note that both of these
1180 /// instructions work differently for signed and unsigned operands.
1182 void ISel::visitDivRem(BinaryOperator &I) {
1183 unsigned Class = getClass(I.getType());
1184 unsigned Op0Reg, Op1Reg, ResultReg = getReg(I);
1187 case cFP: // Floating point divide
1188 if (I.getOpcode() == Instruction::Div) {
1189 Op0Reg = getReg(I.getOperand(0));
1190 Op1Reg = getReg(I.getOperand(1));
1191 BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1192 } else { // Floating point remainder...
1193 MachineInstr *TheCall =
1194 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1195 std::vector<ValueRecord> Args;
1196 Args.push_back(ValueRecord(I.getOperand(0)));
1197 Args.push_back(ValueRecord(I.getOperand(1)));
1198 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1202 static const char *FnName[] =
1203 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1205 unsigned NameIdx = I.getType()->isUnsigned()*2;
1206 NameIdx += I.getOpcode() == Instruction::Div;
1207 MachineInstr *TheCall =
1208 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
1210 std::vector<ValueRecord> Args;
1211 Args.push_back(ValueRecord(I.getOperand(0)));
1212 Args.push_back(ValueRecord(I.getOperand(1)));
1213 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1216 case cByte: case cShort: case cInt:
1217 break; // Small integrals, handled below...
1218 default: assert(0 && "Unknown class!");
1221 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1222 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1223 static const unsigned SarOpcode[]={ X86::SARir8, X86::SARir16, X86::SARir32 };
1224 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
1225 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
1227 static const unsigned DivOpcode[][4] = {
1228 { X86::DIVr8 , X86::DIVr16 , X86::DIVr32 , 0 }, // Unsigned division
1229 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
1232 bool isSigned = I.getType()->isSigned();
1233 unsigned Reg = Regs[Class];
1234 unsigned ExtReg = ExtRegs[Class];
1236 // Put the first operand into one of the A registers...
1237 Op0Reg = getReg(I.getOperand(0));
1238 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
1241 // Emit a sign extension instruction...
1242 unsigned ShiftResult = makeAnotherReg(I.getType());
1243 BuildMI(BB, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
1244 BuildMI(BB, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
1246 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
1247 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
1250 // Emit the appropriate divide or remainder instruction...
1251 Op1Reg = getReg(I.getOperand(1));
1252 BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
1254 // Figure out which register we want to pick the result out of...
1255 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
1257 // Put the result into the destination register...
1258 BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
1262 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1263 /// for constant immediate shift values, and for constant immediate
1264 /// shift values equal to 1. Even the general case is sort of special,
1265 /// because the shift amount has to be in CL, not just any old register.
1267 void ISel::visitShiftInst(ShiftInst &I) {
1268 unsigned SrcReg = getReg(I.getOperand(0));
1269 unsigned DestReg = getReg(I);
1270 bool isLeftShift = I.getOpcode() == Instruction::Shl;
1271 bool isSigned = I.getType()->isSigned();
1272 unsigned Class = getClass(I.getType());
1274 static const unsigned ConstantOperand[][4] = {
1275 { X86::SHRir8, X86::SHRir16, X86::SHRir32, X86::SHRDir32 }, // SHR
1276 { X86::SARir8, X86::SARir16, X86::SARir32, X86::SHRDir32 }, // SAR
1277 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SHL
1278 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SAL = SHL
1281 static const unsigned NonConstantOperand[][4] = {
1282 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
1283 { X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
1284 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
1285 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
1288 // Longs, as usual, are handled specially...
1289 if (Class == cLong) {
1290 // If we have a constant shift, we can generate much more efficient code
1291 // than otherwise...
1293 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getOperand(1))) {
1294 unsigned Amount = CUI->getValue();
1296 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1298 BuildMI(BB, Opc[3], 3,
1299 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1300 BuildMI(BB, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1302 BuildMI(BB, Opc[3], 3,
1303 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1304 BuildMI(BB, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1306 } else { // Shifting more than 32 bits
1309 BuildMI(BB, X86::SHLir32, 2,DestReg+1).addReg(SrcReg).addZImm(Amount);
1310 BuildMI(BB, X86::MOVir32, 1,DestReg ).addZImm(0);
1312 unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32;
1313 BuildMI(BB, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1314 BuildMI(BB, X86::MOVir32, 1, DestReg+1).addZImm(0);
1318 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1320 if (!isLeftShift && isSigned) {
1321 // If this is a SHR of a Long, then we need to do funny sign extension
1322 // stuff. TmpReg gets the value to use as the high-part if we are
1323 // shifting more than 32 bits.
1324 BuildMI(BB, X86::SARir32, 2, TmpReg).addReg(SrcReg).addZImm(31);
1326 // Other shifts use a fixed zero value if the shift is more than 32
1328 BuildMI(BB, X86::MOVir32, 1, TmpReg).addZImm(0);
1331 // Initialize CL with the shift amount...
1332 unsigned ShiftAmount = getReg(I.getOperand(1));
1333 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmount);
1335 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
1336 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
1338 // TmpReg2 = shld inHi, inLo
1339 BuildMI(BB, X86::SHLDrr32, 2, TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
1340 // TmpReg3 = shl inLo, CL
1341 BuildMI(BB, X86::SHLrr32, 1, TmpReg3).addReg(SrcReg);
1343 // Set the flags to indicate whether the shift was by more than 32 bits.
1344 BuildMI(BB, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1346 // DestHi = (>32) ? TmpReg3 : TmpReg2;
1347 BuildMI(BB, X86::CMOVNErr32, 2,
1348 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
1349 // DestLo = (>32) ? TmpReg : TmpReg3;
1350 BuildMI(BB, X86::CMOVNErr32, 2, DestReg).addReg(TmpReg3).addReg(TmpReg);
1352 // TmpReg2 = shrd inLo, inHi
1353 BuildMI(BB, X86::SHRDrr32, 2, TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
1354 // TmpReg3 = s[ah]r inHi, CL
1355 BuildMI(BB, isSigned ? X86::SARrr32 : X86::SHRrr32, 1, TmpReg3)
1358 // Set the flags to indicate whether the shift was by more than 32 bits.
1359 BuildMI(BB, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1361 // DestLo = (>32) ? TmpReg3 : TmpReg2;
1362 BuildMI(BB, X86::CMOVNErr32, 2,
1363 DestReg).addReg(TmpReg2).addReg(TmpReg3);
1365 // DestHi = (>32) ? TmpReg : TmpReg3;
1366 BuildMI(BB, X86::CMOVNErr32, 2,
1367 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
1373 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getOperand(1))) {
1374 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
1375 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
1377 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1378 BuildMI(BB, Opc[Class], 2, DestReg).addReg(SrcReg).addZImm(CUI->getValue());
1379 } else { // The shift amount is non-constant.
1380 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
1382 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
1383 BuildMI(BB, Opc[Class], 1, DestReg).addReg(SrcReg);
1388 /// doFPLoad - This method is used to load an FP value from memory using the
1389 /// current endianness. NOTE: This method returns a partially constructed load
1390 /// instruction which needs to have the memory source filled in still.
1392 MachineInstr *ISel::doFPLoad(MachineBasicBlock *MBB,
1393 MachineBasicBlock::iterator &MBBI,
1394 const Type *Ty, unsigned DestReg) {
1395 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1396 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
1398 if (TM.getTargetData().isLittleEndian()) // fast path...
1399 return BMI(MBB, MBBI, LoadOpcode, 4, DestReg);
1401 // If we are big-endian, start by creating an LEA instruction to represent the
1402 // address of the memory location to load from...
1404 unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy);
1405 MachineInstr *Result = BMI(MBB, MBBI, X86::LEAr32, 5, SrcAddrReg);
1407 // Allocate a temporary stack slot to transform the value into...
1408 int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData());
1410 // Perform the bswaps 32 bits at a time...
1411 unsigned TmpReg1 = makeAnotherReg(Type::UIntTy);
1412 unsigned TmpReg2 = makeAnotherReg(Type::UIntTy);
1413 addDirectMem(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg);
1414 BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1415 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1416 addFrameReference(BMI(MBB, MBBI, X86::MOVrm32, 5),
1417 FrameIdx, Offset).addReg(TmpReg2);
1419 if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value...
1420 TmpReg1 = makeAnotherReg(Type::UIntTy);
1421 TmpReg2 = makeAnotherReg(Type::UIntTy);
1423 addRegOffset(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4);
1424 BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1425 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1426 addFrameReference(BMI(MBB, MBBI, X86::MOVrm32,5), FrameIdx).addReg(TmpReg2);
1429 // Now we can reload the final byteswapped result into the final destination.
1430 addFrameReference(BMI(MBB, MBBI, LoadOpcode, 4, DestReg), FrameIdx);
1434 /// EmitByteSwap - Byteswap SrcReg into DestReg.
1436 void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) {
1437 // Emit the byte swap instruction...
1440 // No byteswap necessary for 8 bit value...
1441 BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(SrcReg);
1444 // Use the 32 bit bswap instruction to do a 32 bit swap...
1445 BuildMI(BB, X86::BSWAPr32, 1, DestReg).addReg(SrcReg);
1449 // For 16 bit we have to use an xchg instruction, because there is no
1450 // 16-bit bswap. XCHG is necessarily not in SSA form, so we force things
1451 // into AX to do the xchg.
1453 BuildMI(BB, X86::MOVrr16, 1, X86::AX).addReg(SrcReg);
1454 BuildMI(BB, X86::XCHGrr8, 2).addReg(X86::AL, MOTy::UseAndDef)
1455 .addReg(X86::AH, MOTy::UseAndDef);
1456 BuildMI(BB, X86::MOVrr16, 1, DestReg).addReg(X86::AX);
1458 default: assert(0 && "Cannot byteswap this class!");
1463 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
1464 /// instruction. The load and store instructions are the only place where we
1465 /// need to worry about the memory layout of the target machine.
1467 void ISel::visitLoadInst(LoadInst &I) {
1468 bool isLittleEndian = TM.getTargetData().isLittleEndian();
1469 bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
1470 unsigned SrcAddrReg = getReg(I.getOperand(0));
1471 unsigned DestReg = getReg(I);
1473 unsigned Class = getClassB(I.getType());
1476 MachineBasicBlock::iterator MBBI = BB->end();
1477 addDirectMem(doFPLoad(BB, MBBI, I.getType(), DestReg), SrcAddrReg);
1480 case cLong: case cInt: case cShort: case cByte:
1481 break; // Integers of various sizes handled below
1482 default: assert(0 && "Unknown memory class!");
1485 // We need to adjust the input pointer if we are emulating a big-endian
1486 // long-pointer target. On these systems, the pointer that we are interested
1487 // in is in the upper part of the eight byte memory image of the pointer. It
1488 // also happens to be byte-swapped, but this will be handled later.
1490 if (!isLittleEndian && hasLongPointers && isa<PointerType>(I.getType())) {
1491 unsigned R = makeAnotherReg(Type::UIntTy);
1492 BuildMI(BB, X86::ADDri32, 2, R).addReg(SrcAddrReg).addZImm(4);
1496 unsigned IReg = DestReg;
1497 if (!isLittleEndian) // If big endian we need an intermediate stage
1498 DestReg = makeAnotherReg(Class != cLong ? I.getType() : Type::UIntTy);
1500 static const unsigned Opcode[] = {
1501 X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, 0, X86::MOVmr32
1503 addDirectMem(BuildMI(BB, Opcode[Class], 4, DestReg), SrcAddrReg);
1505 // Handle long values now...
1506 if (Class == cLong) {
1507 if (isLittleEndian) {
1508 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
1510 EmitByteSwap(IReg+1, DestReg, cInt);
1511 unsigned TempReg = makeAnotherReg(Type::IntTy);
1512 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TempReg), SrcAddrReg, 4);
1513 EmitByteSwap(IReg, TempReg, cInt);
1518 if (!isLittleEndian)
1519 EmitByteSwap(IReg, DestReg, Class);
1523 /// doFPStore - This method is used to store an FP value to memory using the
1524 /// current endianness.
1526 void ISel::doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg) {
1527 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1528 unsigned StoreOpcode = Ty == Type::FloatTy ? X86::FSTr32 : X86::FSTr64;
1530 if (TM.getTargetData().isLittleEndian()) { // fast path...
1531 addDirectMem(BuildMI(BB, StoreOpcode,5), DestAddrReg).addReg(SrcReg);
1535 // Allocate a temporary stack slot to transform the value into...
1536 int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData());
1537 unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy);
1538 addFrameReference(BuildMI(BB, X86::LEAr32, 5, SrcAddrReg), FrameIdx);
1540 // Store the value into a temporary stack slot...
1541 addDirectMem(BuildMI(BB, StoreOpcode, 5), SrcAddrReg).addReg(SrcReg);
1543 // Perform the bswaps 32 bits at a time...
1544 unsigned TmpReg1 = makeAnotherReg(Type::UIntTy);
1545 unsigned TmpReg2 = makeAnotherReg(Type::UIntTy);
1546 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg);
1547 BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1548 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1549 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1550 DestAddrReg, Offset).addReg(TmpReg2);
1552 if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value...
1553 TmpReg1 = makeAnotherReg(Type::UIntTy);
1554 TmpReg2 = makeAnotherReg(Type::UIntTy);
1556 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4);
1557 BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1558 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1559 addDirectMem(BuildMI(BB, X86::MOVrm32, 5), DestAddrReg).addReg(TmpReg2);
1564 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
1567 void ISel::visitStoreInst(StoreInst &I) {
1568 bool isLittleEndian = TM.getTargetData().isLittleEndian();
1569 bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
1570 unsigned ValReg = getReg(I.getOperand(0));
1571 unsigned AddressReg = getReg(I.getOperand(1));
1573 unsigned Class = getClassB(I.getOperand(0)->getType());
1576 if (isLittleEndian) {
1577 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
1578 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4),
1579 AddressReg, 4).addReg(ValReg+1);
1581 unsigned T1 = makeAnotherReg(Type::IntTy);
1582 unsigned T2 = makeAnotherReg(Type::IntTy);
1583 EmitByteSwap(T1, ValReg , cInt);
1584 EmitByteSwap(T2, ValReg+1, cInt);
1585 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(T2);
1586 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg, 4).addReg(T1);
1590 doFPStore(I.getOperand(0)->getType(), AddressReg, ValReg);
1592 case cInt: case cShort: case cByte:
1593 break; // Integers of various sizes handled below
1594 default: assert(0 && "Unknown memory class!");
1597 if (!isLittleEndian && hasLongPointers &&
1598 isa<PointerType>(I.getOperand(0)->getType())) {
1599 unsigned R = makeAnotherReg(Type::UIntTy);
1600 BuildMI(BB, X86::ADDri32, 2, R).addReg(AddressReg).addZImm(4);
1604 if (!isLittleEndian && Class != cByte) {
1605 unsigned R = makeAnotherReg(I.getOperand(0)->getType());
1606 EmitByteSwap(R, ValReg, Class);
1610 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1611 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
1615 /// visitCastInst - Here we have various kinds of copying with or without
1616 /// sign extension going on.
1617 void ISel::visitCastInst(CastInst &CI) {
1618 Value *Op = CI.getOperand(0);
1619 // If this is a cast from a 32-bit integer to a Long type, and the only uses
1620 // of the case are GEP instructions, then the cast does not need to be
1621 // generated explicitly, it will be folded into the GEP.
1622 if (CI.getType() == Type::LongTy &&
1623 (Op->getType() == Type::IntTy || Op->getType() == Type::UIntTy)) {
1624 bool AllUsesAreGEPs = true;
1625 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
1626 if (!isa<GetElementPtrInst>(*I)) {
1627 AllUsesAreGEPs = false;
1631 // No need to codegen this cast if all users are getelementptr instrs...
1632 if (AllUsesAreGEPs) return;
1635 unsigned DestReg = getReg(CI);
1636 MachineBasicBlock::iterator MI = BB->end();
1637 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
1640 /// emitCastOperation - Common code shared between visitCastInst and
1641 /// constant expression cast support.
1642 void ISel::emitCastOperation(MachineBasicBlock *BB,
1643 MachineBasicBlock::iterator &IP,
1644 Value *Src, const Type *DestTy,
1646 unsigned SrcReg = getReg(Src, BB, IP);
1647 const Type *SrcTy = Src->getType();
1648 unsigned SrcClass = getClassB(SrcTy);
1649 unsigned DestClass = getClassB(DestTy);
1651 // Implement casts to bool by using compare on the operand followed by set if
1652 // not zero on the result.
1653 if (DestTy == Type::BoolTy) {
1656 BMI(BB, IP, X86::TESTrr8, 2).addReg(SrcReg).addReg(SrcReg);
1659 BMI(BB, IP, X86::TESTrr16, 2).addReg(SrcReg).addReg(SrcReg);
1662 BMI(BB, IP, X86::TESTrr32, 2).addReg(SrcReg).addReg(SrcReg);
1665 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1666 BMI(BB, IP, X86::ORrr32, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
1670 assert(0 && "FIXME: implement cast FP to bool");
1674 // If the zero flag is not set, then the value is true, set the byte to
1676 BMI(BB, IP, X86::SETNEr, 1, DestReg);
1680 static const unsigned RegRegMove[] = {
1681 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV, X86::MOVrr32
1684 // Implement casts between values of the same type class (as determined by
1685 // getClass) by using a register-to-register move.
1686 if (SrcClass == DestClass) {
1687 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
1688 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
1689 } else if (SrcClass == cFP) {
1690 if (SrcTy == Type::FloatTy) { // double -> float
1691 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1692 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
1693 } else { // float -> double
1694 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1695 "Unknown cFP member!");
1696 // Truncate from double to float by storing to memory as short, then
1698 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
1699 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
1700 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1701 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
1703 } else if (SrcClass == cLong) {
1704 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1705 BMI(BB, IP, X86::MOVrr32, 1, DestReg+1).addReg(SrcReg+1);
1707 assert(0 && "Cannot handle this type of cast instruction!");
1713 // Handle cast of SMALLER int to LARGER int using a move with sign extension
1714 // or zero extension, depending on whether the source type was signed.
1715 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
1716 SrcClass < DestClass) {
1717 bool isLong = DestClass == cLong;
1718 if (isLong) DestClass = cInt;
1720 static const unsigned Opc[][4] = {
1721 { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, X86::MOVrr32 }, // s
1722 { X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16, X86::MOVrr32 } // u
1725 bool isUnsigned = SrcTy->isUnsigned();
1726 BMI(BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
1727 DestReg).addReg(SrcReg);
1729 if (isLong) { // Handle upper 32 bits as appropriate...
1730 if (isUnsigned) // Zero out top bits...
1731 BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1732 else // Sign extend bottom half...
1733 BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31);
1738 // Special case long -> int ...
1739 if (SrcClass == cLong && DestClass == cInt) {
1740 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1744 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
1745 // move out of AX or AL.
1746 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
1747 && SrcClass > DestClass) {
1748 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
1749 BMI(BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
1750 BMI(BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
1754 // Handle casts from integer to floating point now...
1755 if (DestClass == cFP) {
1756 // Promote the integer to a type supported by FLD. We do this because there
1757 // are no unsigned FLD instructions, so we must promote an unsigned value to
1758 // a larger signed value, then use FLD on the larger value.
1760 const Type *PromoteType = 0;
1761 unsigned PromoteOpcode;
1762 switch (SrcTy->getPrimitiveID()) {
1763 case Type::BoolTyID:
1764 case Type::SByteTyID:
1765 // We don't have the facilities for directly loading byte sized data from
1766 // memory (even signed). Promote it to 16 bits.
1767 PromoteType = Type::ShortTy;
1768 PromoteOpcode = X86::MOVSXr16r8;
1770 case Type::UByteTyID:
1771 PromoteType = Type::ShortTy;
1772 PromoteOpcode = X86::MOVZXr16r8;
1774 case Type::UShortTyID:
1775 PromoteType = Type::IntTy;
1776 PromoteOpcode = X86::MOVZXr32r16;
1778 case Type::UIntTyID: {
1779 // Make a 64 bit temporary... and zero out the top of it...
1780 unsigned TmpReg = makeAnotherReg(Type::LongTy);
1781 BMI(BB, IP, X86::MOVrr32, 1, TmpReg).addReg(SrcReg);
1782 BMI(BB, IP, X86::MOVir32, 1, TmpReg+1).addZImm(0);
1783 SrcTy = Type::LongTy;
1788 case Type::ULongTyID:
1789 assert("FIXME: not implemented: cast ulong X to fp type!");
1790 default: // No promotion needed...
1795 unsigned TmpReg = makeAnotherReg(PromoteType);
1796 BMI(BB, IP, SrcTy->isSigned() ? X86::MOVSXr16r8 : X86::MOVZXr16r8,
1797 1, TmpReg).addReg(SrcReg);
1798 SrcTy = PromoteType;
1799 SrcClass = getClass(PromoteType);
1803 // Spill the integer to memory and reload it from there...
1805 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
1807 if (SrcClass == cLong) {
1808 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5), FrameIdx).addReg(SrcReg);
1809 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5),
1810 FrameIdx, 4).addReg(SrcReg+1);
1812 static const unsigned Op1[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1813 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
1816 static const unsigned Op2[] =
1817 { 0/*byte*/, X86::FILDr16, X86::FILDr32, 0/*FP*/, X86::FILDr64 };
1818 addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
1822 // Handle casts from floating point to integer now...
1823 if (SrcClass == cFP) {
1824 // Change the floating point control register to use "round towards zero"
1825 // mode when truncating to an integer value.
1827 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1828 addFrameReference(BMI(BB, IP, X86::FNSTCWm16, 4), CWFrameIdx);
1830 // Load the old value of the high byte of the control word...
1831 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
1832 addFrameReference(BMI(BB, IP, X86::MOVmr8, 4, HighPartOfCW), CWFrameIdx, 1);
1834 // Set the high part to be round to zero...
1835 addFrameReference(BMI(BB, IP, X86::MOVim8, 5), CWFrameIdx, 1).addZImm(12);
1837 // Reload the modified control word now...
1838 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1840 // Restore the memory image of control word to original value
1841 addFrameReference(BMI(BB, IP, X86::MOVrm8, 5),
1842 CWFrameIdx, 1).addReg(HighPartOfCW);
1844 // We don't have the facilities for directly storing byte sized data to
1845 // memory. Promote it to 16 bits. We also must promote unsigned values to
1846 // larger classes because we only have signed FP stores.
1847 unsigned StoreClass = DestClass;
1848 const Type *StoreTy = DestTy;
1849 if (StoreClass == cByte || DestTy->isUnsigned())
1850 switch (StoreClass) {
1851 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
1852 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
1853 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
1854 // The following treatment of cLong may not be perfectly right,
1855 // but it survives chains of casts of the form
1856 // double->ulong->double.
1857 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
1858 default: assert(0 && "Unknown store class!");
1861 // Spill the integer to memory and reload it from there...
1863 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
1865 static const unsigned Op1[] =
1866 { 0, X86::FISTr16, X86::FISTr32, 0, X86::FISTPr64 };
1867 addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg);
1869 if (DestClass == cLong) {
1870 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg), FrameIdx);
1871 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg+1), FrameIdx, 4);
1873 static const unsigned Op2[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
1874 addFrameReference(BMI(BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
1877 // Reload the original control word now...
1878 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1882 // Anything we haven't handled already, we can't (yet) handle at all.
1883 assert(0 && "Unhandled cast instruction!");
1887 /// visitVarArgInst - Implement the va_arg instruction...
1889 void ISel::visitVarArgInst(VarArgInst &I) {
1890 unsigned SrcReg = getReg(I.getOperand(0));
1891 unsigned DestReg = getReg(I);
1893 // Load the va_list into a register...
1894 unsigned VAList = makeAnotherReg(Type::UIntTy);
1895 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, VAList), SrcReg);
1898 switch (I.getType()->getPrimitiveID()) {
1901 assert(0 && "Error: bad type for va_arg instruction!");
1903 case Type::PointerTyID:
1904 case Type::UIntTyID:
1907 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
1909 case Type::ULongTyID:
1910 case Type::LongTyID:
1912 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
1913 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), VAList, 4);
1915 case Type::DoubleTyID:
1917 addDirectMem(BuildMI(BB, X86::FLDr64, 4, DestReg), VAList);
1921 // Increment the VAList pointer...
1922 unsigned NextVAList = makeAnotherReg(Type::UIntTy);
1923 BuildMI(BB, X86::ADDri32, 2, NextVAList).addReg(VAList).addZImm(Size);
1925 // Update the VAList in memory...
1926 addDirectMem(BuildMI(BB, X86::MOVrm32, 5), SrcReg).addReg(NextVAList);
1930 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1931 // returns zero when the input is not exactly a power of two.
1932 static unsigned ExactLog2(unsigned Val) {
1933 if (Val == 0) return 0;
1936 if (Val & 1) return 0;
1943 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
1944 unsigned outputReg = getReg(I);
1945 MachineBasicBlock::iterator MI = BB->end();
1946 emitGEPOperation(BB, MI, I.getOperand(0),
1947 I.op_begin()+1, I.op_end(), outputReg);
1950 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
1951 MachineBasicBlock::iterator &IP,
1952 Value *Src, User::op_iterator IdxBegin,
1953 User::op_iterator IdxEnd, unsigned TargetReg) {
1954 const TargetData &TD = TM.getTargetData();
1955 const Type *Ty = Src->getType();
1956 unsigned BaseReg = getReg(Src, MBB, IP);
1958 // GEPs have zero or more indices; we must perform a struct access
1959 // or array access for each one.
1960 for (GetElementPtrInst::op_iterator oi = IdxBegin,
1961 oe = IdxEnd; oi != oe; ++oi) {
1963 unsigned NextReg = BaseReg;
1964 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1965 // It's a struct access. idx is the index into the structure,
1966 // which names the field. This index must have ubyte type.
1967 const ConstantUInt *CUI = cast<ConstantUInt>(idx);
1968 assert(CUI->getType() == Type::UByteTy
1969 && "Funny-looking structure index in GEP");
1970 // Use the TargetData structure to pick out what the layout of
1971 // the structure is in memory. Since the structure index must
1972 // be constant, we can get its value and use it to find the
1973 // right byte offset from the StructLayout class's list of
1974 // structure member offsets.
1975 unsigned idxValue = CUI->getValue();
1976 unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue];
1978 NextReg = makeAnotherReg(Type::UIntTy);
1979 // Emit an ADD to add FieldOff to the basePtr.
1980 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff);
1982 // The next type is the member of the structure selected by the
1984 Ty = StTy->getElementTypes()[idxValue];
1985 } else if (const SequentialType *SqTy = cast<SequentialType>(Ty)) {
1986 // It's an array or pointer access: [ArraySize x ElementType].
1988 // idx is the index into the array. Unlike with structure
1989 // indices, we may not know its actual value at code-generation
1991 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
1993 // Most GEP instructions use a [cast (int/uint) to LongTy] as their
1994 // operand on X86. Handle this case directly now...
1995 if (CastInst *CI = dyn_cast<CastInst>(idx))
1996 if (CI->getOperand(0)->getType() == Type::IntTy ||
1997 CI->getOperand(0)->getType() == Type::UIntTy)
1998 idx = CI->getOperand(0);
2000 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
2001 // must find the size of the pointed-to type (Not coincidentally, the next
2002 // type is the type of the elements in the array).
2003 Ty = SqTy->getElementType();
2004 unsigned elementSize = TD.getTypeSize(Ty);
2006 // If idxReg is a constant, we don't need to perform the multiply!
2007 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
2008 if (!CSI->isNullValue()) {
2009 unsigned Offset = elementSize*CSI->getValue();
2010 NextReg = makeAnotherReg(Type::UIntTy);
2011 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(Offset);
2013 } else if (elementSize == 1) {
2014 // If the element size is 1, we don't have to multiply, just add
2015 unsigned idxReg = getReg(idx, MBB, IP);
2016 NextReg = makeAnotherReg(Type::UIntTy);
2017 BMI(MBB, IP, X86::ADDrr32, 2, NextReg).addReg(BaseReg).addReg(idxReg);
2019 unsigned idxReg = getReg(idx, MBB, IP);
2020 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
2021 if (unsigned Shift = ExactLog2(elementSize)) {
2022 // If the element size is exactly a power of 2, use a shift to get it.
2023 BMI(MBB, IP, X86::SHLir32, 2,
2024 OffsetReg).addReg(idxReg).addZImm(Shift-1);
2026 // Most general case, emit a multiply...
2027 unsigned elementSizeReg = makeAnotherReg(Type::LongTy);
2028 BMI(MBB, IP, X86::MOVir32, 1, elementSizeReg).addZImm(elementSize);
2030 // Emit a MUL to multiply the register holding the index by
2031 // elementSize, putting the result in OffsetReg.
2032 doMultiply(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSizeReg);
2034 // Emit an ADD to add OffsetReg to the basePtr.
2035 NextReg = makeAnotherReg(Type::UIntTy);
2036 BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg);
2039 // Now that we are here, further indices refer to subtypes of this
2040 // one, so we don't need to worry about BaseReg itself, anymore.
2043 // After we have processed all the indices, the result is left in
2044 // BaseReg. Move it to the register where we were expected to
2045 // put the answer. A 32-bit move should do it, because we are in
2047 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
2051 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2052 /// frame manager, otherwise do it the hard way.
2054 void ISel::visitAllocaInst(AllocaInst &I) {
2055 // Find the data size of the alloca inst's getAllocatedType.
2056 const Type *Ty = I.getAllocatedType();
2057 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2059 // If this is a fixed size alloca in the entry block for the function,
2060 // statically stack allocate the space.
2062 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
2063 if (I.getParent() == I.getParent()->getParent()->begin()) {
2064 TySize *= CUI->getValue(); // Get total allocated size...
2065 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
2067 // Create a new stack object using the frame manager...
2068 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
2069 addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx);
2074 // Create a register to hold the temporary result of multiplying the type size
2075 // constant by the variable amount.
2076 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2077 unsigned SrcReg1 = getReg(I.getArraySize());
2078 unsigned SizeReg = makeAnotherReg(Type::UIntTy);
2079 BuildMI(BB, X86::MOVir32, 1, SizeReg).addZImm(TySize);
2081 // TotalSizeReg = mul <numelements>, <TypeSize>
2082 MachineBasicBlock::iterator MBBI = BB->end();
2083 doMultiply(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, SizeReg);
2085 // AddedSize = add <TotalSizeReg>, 15
2086 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2087 BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15);
2089 // AlignedSize = and <AddedSize>, ~15
2090 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2091 BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15);
2093 // Subtract size from stack pointer, thereby allocating some space.
2094 BuildMI(BB, X86::SUBrr32, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
2096 // Put a pointer to the space into the result register, by copying
2097 // the stack pointer.
2098 BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP);
2100 // Inform the Frame Information that we have just allocated a variable-sized
2102 F->getFrameInfo()->CreateVariableSizedObject();
2105 /// visitMallocInst - Malloc instructions are code generated into direct calls
2106 /// to the library malloc.
2108 void ISel::visitMallocInst(MallocInst &I) {
2109 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2112 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2113 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2115 Arg = makeAnotherReg(Type::UIntTy);
2116 unsigned Op0Reg = getReg(ConstantUInt::get(Type::UIntTy, AllocSize));
2117 unsigned Op1Reg = getReg(I.getOperand(0));
2118 MachineBasicBlock::iterator MBBI = BB->end();
2119 doMultiply(BB, MBBI, Arg, Type::UIntTy, Op0Reg, Op1Reg);
2122 std::vector<ValueRecord> Args;
2123 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2124 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2125 1).addExternalSymbol("malloc", true);
2126 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
2130 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2133 void ISel::visitFreeInst(FreeInst &I) {
2134 std::vector<ValueRecord> Args;
2135 Args.push_back(ValueRecord(I.getOperand(0)));
2136 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2137 1).addExternalSymbol("free", true);
2138 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
2142 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
2143 /// into a machine code representation is a very simple peep-hole fashion. The
2144 /// generated code sucks but the implementation is nice and simple.
2146 FunctionPass *createX86SimpleInstructionSelector(TargetMachine &TM) {
2147 return new ISel(TM);