1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the x86 target
12 //===----------------------------------------------------------------------===//
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Function.h"
20 #include "llvm/Instructions.h"
21 #include "llvm/IntrinsicLowering.h"
22 #include "llvm/Pass.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/InstVisitor.h"
31 #include "llvm/Support/CFG.h"
36 /// BMI - A special BuildMI variant that takes an iterator to insert the
37 /// instruction at as well as a basic block. This is the version for when you
38 /// have a destination register in mind.
39 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
40 MachineBasicBlock::iterator &I,
41 int Opcode, unsigned NumOperands,
43 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
44 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
45 I = MBB->insert(I, MI)+1;
46 return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
49 /// BMI - A special BuildMI variant that takes an iterator to insert the
50 /// instruction at as well as a basic block.
51 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
52 MachineBasicBlock::iterator &I,
53 int Opcode, unsigned NumOperands) {
54 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
55 MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
56 I = MBB->insert(I, MI)+1;
57 return MachineInstrBuilder(MI);
62 struct ISel : public FunctionPass, InstVisitor<ISel> {
64 MachineFunction *F; // The function we are compiling into
65 MachineBasicBlock *BB; // The current MBB we are compiling
66 int VarArgsFrameIndex; // FrameIndex for start of varargs area
68 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
70 // MBBMap - Mapping between LLVM BB -> Machine BB
71 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
73 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
75 /// runOnFunction - Top level implementation of instruction selection for
76 /// the entire function.
78 bool runOnFunction(Function &Fn) {
79 // First pass over the function, lower any unknown intrinsic functions
80 // with the IntrinsicLowering class.
81 LowerUnknownIntrinsicFunctionCalls(Fn);
83 F = &MachineFunction::construct(&Fn, TM);
85 // Create all of the machine basic blocks for the function...
86 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
87 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
91 // Copy incoming arguments off of the stack...
92 LoadArgumentsToVirtualRegs(Fn);
94 // Instruction select everything except PHI nodes
97 // Select the PHI nodes
103 // We always build a machine code representation for the function
107 virtual const char *getPassName() const {
108 return "X86 Simple Instruction Selection";
111 /// visitBasicBlock - This method is called when we are visiting a new basic
112 /// block. This simply creates a new MachineBasicBlock to emit code into
113 /// and adds it to the current MachineFunction. Subsequent visit* for
114 /// instructions will be invoked for all instructions in the basic block.
116 void visitBasicBlock(BasicBlock &LLVM_BB) {
117 BB = MBBMap[&LLVM_BB];
120 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
121 /// function, lowering any calls to unknown intrinsic functions into the
122 /// equivalent LLVM code.
123 void LowerUnknownIntrinsicFunctionCalls(Function &F);
125 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
126 /// from the stack into virtual registers.
128 void LoadArgumentsToVirtualRegs(Function &F);
130 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
131 /// because we have to generate our sources into the source basic blocks,
132 /// not the current one.
134 void SelectPHINodes();
136 // Visitation methods for various instructions. These methods simply emit
137 // fixed X86 code for each instruction.
140 // Control flow operators
141 void visitReturnInst(ReturnInst &RI);
142 void visitBranchInst(BranchInst &BI);
148 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
149 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
151 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
152 const std::vector<ValueRecord> &Args);
153 void visitCallInst(CallInst &I);
154 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
156 // Arithmetic operators
157 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
158 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
159 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
160 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
161 unsigned DestReg, const Type *DestTy,
162 unsigned Op0Reg, unsigned Op1Reg);
163 void doMultiplyConst(MachineBasicBlock *MBB,
164 MachineBasicBlock::iterator &MBBI,
165 unsigned DestReg, const Type *DestTy,
166 unsigned Op0Reg, unsigned Op1Val);
167 void visitMul(BinaryOperator &B);
169 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
170 void visitRem(BinaryOperator &B) { visitDivRem(B); }
171 void visitDivRem(BinaryOperator &B);
174 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
175 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
176 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
178 // Comparison operators...
179 void visitSetCondInst(SetCondInst &I);
180 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
181 MachineBasicBlock *MBB,
182 MachineBasicBlock::iterator &MBBI);
184 // Memory Instructions
185 void visitLoadInst(LoadInst &I);
186 void visitStoreInst(StoreInst &I);
187 void visitGetElementPtrInst(GetElementPtrInst &I);
188 void visitAllocaInst(AllocaInst &I);
189 void visitMallocInst(MallocInst &I);
190 void visitFreeInst(FreeInst &I);
193 void visitShiftInst(ShiftInst &I);
194 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
195 void visitCastInst(CastInst &I);
196 void visitVANextInst(VANextInst &I);
197 void visitVAArgInst(VAArgInst &I);
199 void visitInstruction(Instruction &I) {
200 std::cerr << "Cannot instruction select: " << I;
204 /// promote32 - Make a value 32-bits wide, and put it somewhere.
206 void promote32(unsigned targetReg, const ValueRecord &VR);
208 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
209 /// constant expression GEP support.
211 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator&IP,
212 Value *Src, User::op_iterator IdxBegin,
213 User::op_iterator IdxEnd, unsigned TargetReg);
215 /// emitCastOperation - Common code shared between visitCastInst and
216 /// constant expression cast support.
217 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
218 Value *Src, const Type *DestTy, unsigned TargetReg);
220 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
221 /// and constant expression support.
222 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
223 MachineBasicBlock::iterator &IP,
224 Value *Op0, Value *Op1,
225 unsigned OperatorClass, unsigned TargetReg);
227 void emitDivRemOperation(MachineBasicBlock *BB,
228 MachineBasicBlock::iterator &IP,
229 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
230 const Type *Ty, unsigned TargetReg);
232 /// emitSetCCOperation - Common code shared between visitSetCondInst and
233 /// constant expression support.
234 void emitSetCCOperation(MachineBasicBlock *BB,
235 MachineBasicBlock::iterator &IP,
236 Value *Op0, Value *Op1, unsigned Opcode,
239 /// emitShiftOperation - Common code shared between visitShiftInst and
240 /// constant expression support.
241 void emitShiftOperation(MachineBasicBlock *MBB,
242 MachineBasicBlock::iterator &IP,
243 Value *Op, Value *ShiftAmount, bool isLeftShift,
244 const Type *ResultTy, unsigned DestReg);
247 /// copyConstantToRegister - Output the instructions required to put the
248 /// specified constant into the specified register.
250 void copyConstantToRegister(MachineBasicBlock *MBB,
251 MachineBasicBlock::iterator &MBBI,
252 Constant *C, unsigned Reg);
254 /// makeAnotherReg - This method returns the next register number we haven't
257 /// Long values are handled somewhat specially. They are always allocated
258 /// as pairs of 32 bit integer values. The register number returned is the
259 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
260 /// of the long value.
262 unsigned makeAnotherReg(const Type *Ty) {
263 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
264 "Current target doesn't have X86 reg info??");
265 const X86RegisterInfo *MRI =
266 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
267 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
268 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
269 // Create the lower part
270 F->getSSARegMap()->createVirtualRegister(RC);
271 // Create the upper part.
272 return F->getSSARegMap()->createVirtualRegister(RC)-1;
275 // Add the mapping of regnumber => reg class to MachineFunction
276 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
277 return F->getSSARegMap()->createVirtualRegister(RC);
280 /// getReg - This method turns an LLVM value into a register number. This
281 /// is guaranteed to produce the same register number for a particular value
282 /// every time it is queried.
284 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
285 unsigned getReg(Value *V) {
286 // Just append to the end of the current bb.
287 MachineBasicBlock::iterator It = BB->end();
288 return getReg(V, BB, It);
290 unsigned getReg(Value *V, MachineBasicBlock *MBB,
291 MachineBasicBlock::iterator &IPt) {
292 unsigned &Reg = RegMap[V];
294 Reg = makeAnotherReg(V->getType());
298 // If this operand is a constant, emit the code to copy the constant into
299 // the register here...
301 if (Constant *C = dyn_cast<Constant>(V)) {
302 copyConstantToRegister(MBB, IPt, C, Reg);
303 RegMap.erase(V); // Assign a new name to this constant if ref'd again
304 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
305 // Move the address of the global into the register
306 BMI(MBB, IPt, X86::MOVir32, 1, Reg).addGlobalAddress(GV);
307 RegMap.erase(V); // Assign a new name to this address if ref'd again
315 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
319 cByte, cShort, cInt, cFP, cLong
322 /// getClass - Turn a primitive type into a "class" number which is based on the
323 /// size of the type, and whether or not it is floating point.
325 static inline TypeClass getClass(const Type *Ty) {
326 switch (Ty->getPrimitiveID()) {
327 case Type::SByteTyID:
328 case Type::UByteTyID: return cByte; // Byte operands are class #0
329 case Type::ShortTyID:
330 case Type::UShortTyID: return cShort; // Short operands are class #1
333 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
335 case Type::FloatTyID:
336 case Type::DoubleTyID: return cFP; // Floating Point is #3
339 case Type::ULongTyID: return cLong; // Longs are class #4
341 assert(0 && "Invalid type to getClass!");
342 return cByte; // not reached
346 // getClassB - Just like getClass, but treat boolean values as bytes.
347 static inline TypeClass getClassB(const Type *Ty) {
348 if (Ty == Type::BoolTy) return cByte;
353 /// copyConstantToRegister - Output the instructions required to put the
354 /// specified constant into the specified register.
356 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
357 MachineBasicBlock::iterator &IP,
358 Constant *C, unsigned R) {
359 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
361 switch (CE->getOpcode()) {
362 case Instruction::GetElementPtr:
363 emitGEPOperation(MBB, IP, CE->getOperand(0),
364 CE->op_begin()+1, CE->op_end(), R);
366 case Instruction::Cast:
367 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
370 case Instruction::Xor: ++Class; // FALL THROUGH
371 case Instruction::Or: ++Class; // FALL THROUGH
372 case Instruction::And: ++Class; // FALL THROUGH
373 case Instruction::Sub: ++Class; // FALL THROUGH
374 case Instruction::Add:
375 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
379 case Instruction::Mul: {
380 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
381 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
382 doMultiply(MBB, IP, R, CE->getType(), Op0Reg, Op1Reg);
385 case Instruction::Div:
386 case Instruction::Rem: {
387 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
388 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
389 emitDivRemOperation(MBB, IP, Op0Reg, Op1Reg,
390 CE->getOpcode() == Instruction::Div,
395 case Instruction::SetNE:
396 case Instruction::SetEQ:
397 case Instruction::SetLT:
398 case Instruction::SetGT:
399 case Instruction::SetLE:
400 case Instruction::SetGE:
401 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
405 case Instruction::Shl:
406 case Instruction::Shr:
407 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
408 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
412 std::cerr << "Offending expr: " << C << "\n";
413 assert(0 && "Constant expression not yet handled!\n");
417 if (C->getType()->isIntegral()) {
418 unsigned Class = getClassB(C->getType());
420 if (Class == cLong) {
421 // Copy the value into the register pair.
422 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
423 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(Val & 0xFFFFFFFF);
424 BMI(MBB, IP, X86::MOVir32, 1, R+1).addZImm(Val >> 32);
428 assert(Class <= cInt && "Type not handled yet!");
430 static const unsigned IntegralOpcodeTab[] = {
431 X86::MOVir8, X86::MOVir16, X86::MOVir32
434 if (C->getType() == Type::BoolTy) {
435 BMI(MBB, IP, X86::MOVir8, 1, R).addZImm(C == ConstantBool::True);
437 ConstantInt *CI = cast<ConstantInt>(C);
438 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CI->getRawValue());
440 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
441 if (CFP->isExactlyValue(+0.0))
442 BMI(MBB, IP, X86::FLD0, 0, R);
443 else if (CFP->isExactlyValue(+1.0))
444 BMI(MBB, IP, X86::FLD1, 0, R);
446 // Otherwise we need to spill the constant to memory...
447 MachineConstantPool *CP = F->getConstantPool();
448 unsigned CPI = CP->getConstantPoolIndex(CFP);
449 const Type *Ty = CFP->getType();
451 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
452 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
453 addConstantPoolReference(BMI(MBB, IP, LoadOpcode, 4, R), CPI);
456 } else if (isa<ConstantPointerNull>(C)) {
457 // Copy zero (null pointer) to the register.
458 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0);
459 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
460 unsigned SrcReg = getReg(CPR->getValue(), MBB, IP);
461 BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg);
463 std::cerr << "Offending constant: " << C << "\n";
464 assert(0 && "Type not handled yet!");
468 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
469 /// the stack into virtual registers.
471 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
472 // Emit instructions to load the arguments... On entry to a function on the
473 // X86, the stack frame looks like this:
475 // [ESP] -- return address
476 // [ESP + 4] -- first argument (leftmost lexically)
477 // [ESP + 8] -- second argument, if first argument is four bytes in size
480 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
481 MachineFrameInfo *MFI = F->getFrameInfo();
483 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
484 unsigned Reg = getReg(*I);
486 int FI; // Frame object index
487 switch (getClassB(I->getType())) {
489 FI = MFI->CreateFixedObject(1, ArgOffset);
490 addFrameReference(BuildMI(BB, X86::MOVmr8, 4, Reg), FI);
493 FI = MFI->CreateFixedObject(2, ArgOffset);
494 addFrameReference(BuildMI(BB, X86::MOVmr16, 4, Reg), FI);
497 FI = MFI->CreateFixedObject(4, ArgOffset);
498 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
501 FI = MFI->CreateFixedObject(8, ArgOffset);
502 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
503 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg+1), FI, 4);
504 ArgOffset += 4; // longs require 4 additional bytes
508 if (I->getType() == Type::FloatTy) {
509 Opcode = X86::FLDr32;
510 FI = MFI->CreateFixedObject(4, ArgOffset);
512 Opcode = X86::FLDr64;
513 FI = MFI->CreateFixedObject(8, ArgOffset);
514 ArgOffset += 4; // doubles require 4 additional bytes
516 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
519 assert(0 && "Unhandled argument type!");
521 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
524 // If the function takes variable number of arguments, add a frame offset for
525 // the start of the first vararg value... this is used to expand
527 if (Fn.getFunctionType()->isVarArg())
528 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
532 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
533 /// because we have to generate our sources into the source basic blocks, not
536 void ISel::SelectPHINodes() {
537 const TargetInstrInfo &TII = TM.getInstrInfo();
538 const Function &LF = *F->getFunction(); // The LLVM function...
539 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
540 const BasicBlock *BB = I;
541 MachineBasicBlock *MBB = MBBMap[I];
543 // Loop over all of the PHI nodes in the LLVM basic block...
544 unsigned NumPHIs = 0;
545 for (BasicBlock::const_iterator I = BB->begin();
546 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
548 // Create a new machine instr PHI node, and insert it.
549 unsigned PHIReg = getReg(*PN);
550 MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
551 MBB->insert(MBB->begin()+NumPHIs++, PhiMI);
553 MachineInstr *LongPhiMI = 0;
554 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
555 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
556 MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
559 // PHIValues - Map of blocks to incoming virtual registers. We use this
560 // so that we only initialize one incoming value for a particular block,
561 // even if the block has multiple entries in the PHI node.
563 std::map<MachineBasicBlock*, unsigned> PHIValues;
565 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
566 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
568 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
569 PHIValues.lower_bound(PredMBB);
571 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
572 // We already inserted an initialization of the register for this
573 // predecessor. Recycle it.
574 ValReg = EntryIt->second;
577 // Get the incoming value into a virtual register.
579 Value *Val = PN->getIncomingValue(i);
581 // If this is a constant or GlobalValue, we may have to insert code
582 // into the basic block to compute it into a virtual register.
583 if (isa<Constant>(Val) || isa<GlobalValue>(Val)) {
584 // Because we don't want to clobber any values which might be in
585 // physical registers with the computation of this constant (which
586 // might be arbitrarily complex if it is a constant expression),
587 // just insert the computation at the top of the basic block.
588 MachineBasicBlock::iterator PI = PredMBB->begin();
590 // Skip over any PHI nodes though!
591 while (PI != PredMBB->end() && (*PI)->getOpcode() == X86::PHI)
594 ValReg = getReg(Val, PredMBB, PI);
596 ValReg = getReg(Val);
599 // Remember that we inserted a value for this PHI for this predecessor
600 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
603 PhiMI->addRegOperand(ValReg);
604 PhiMI->addMachineBasicBlockOperand(PredMBB);
606 LongPhiMI->addRegOperand(ValReg+1);
607 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
614 // canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
615 // the conditional branch instruction which is the only user of the cc
616 // instruction. This is the case if the conditional branch is the only user of
617 // the setcc, and if the setcc is in the same basic block as the conditional
618 // branch. We also don't handle long arguments below, so we reject them here as
621 static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
622 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
623 if (SCI->hasOneUse() && isa<BranchInst>(SCI->use_back()) &&
624 SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
625 const Type *Ty = SCI->getOperand(0)->getType();
626 if (Ty != Type::LongTy && Ty != Type::ULongTy)
632 // Return a fixed numbering for setcc instructions which does not depend on the
633 // order of the opcodes.
635 static unsigned getSetCCNumber(unsigned Opcode) {
637 default: assert(0 && "Unknown setcc instruction!");
638 case Instruction::SetEQ: return 0;
639 case Instruction::SetNE: return 1;
640 case Instruction::SetLT: return 2;
641 case Instruction::SetGE: return 3;
642 case Instruction::SetGT: return 4;
643 case Instruction::SetLE: return 5;
647 // LLVM -> X86 signed X86 unsigned
648 // ----- ---------- ------------
649 // seteq -> sete sete
650 // setne -> setne setne
651 // setlt -> setl setb
652 // setge -> setge setae
653 // setgt -> setg seta
654 // setle -> setle setbe
656 // sets // Used by comparison with 0 optimization
658 static const unsigned SetCCOpcodeTab[2][8] = {
659 { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
661 { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
662 X86::SETSr, X86::SETNSr },
665 // EmitComparison - This function emits a comparison of the two operands,
666 // returning the extended setcc code to use.
667 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
668 MachineBasicBlock *MBB,
669 MachineBasicBlock::iterator &IP) {
670 // The arguments are already supposed to be of the same type.
671 const Type *CompTy = Op0->getType();
672 unsigned Class = getClassB(CompTy);
673 unsigned Op0r = getReg(Op0, MBB, IP);
675 // Special case handling of: cmp R, i
676 if (Class == cByte || Class == cShort || Class == cInt)
677 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
678 uint64_t Op1v = cast<ConstantInt>(CI)->getRawValue();
680 // Mask off any upper bits of the constant, if there are any...
681 Op1v &= (1ULL << (8 << Class)) - 1;
683 // If this is a comparison against zero, emit more efficient code. We
684 // can't handle unsigned comparisons against zero unless they are == or
685 // !=. These should have been strength reduced already anyway.
686 if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
687 static const unsigned TESTTab[] = {
688 X86::TESTrr8, X86::TESTrr16, X86::TESTrr32
690 BMI(MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
692 if (OpNum == 2) return 6; // Map jl -> js
693 if (OpNum == 3) return 7; // Map jg -> jns
697 static const unsigned CMPTab[] = {
698 X86::CMPri8, X86::CMPri16, X86::CMPri32
701 BMI(MBB, IP, CMPTab[Class], 2).addReg(Op0r).addZImm(Op1v);
705 // Special case handling of comparison against +/- 0.0
706 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op1))
707 if (CFP->isExactlyValue(+0.0) || CFP->isExactlyValue(-0.0)) {
708 BMI(MBB, IP, X86::FTST, 1).addReg(Op0r);
709 BMI(MBB, IP, X86::FNSTSWr8, 0);
710 BMI(MBB, IP, X86::SAHF, 1);
714 unsigned Op1r = getReg(Op1, MBB, IP);
716 default: assert(0 && "Unknown type class!");
717 // Emit: cmp <var1>, <var2> (do the comparison). We can
718 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
721 BMI(MBB, IP, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r);
724 BMI(MBB, IP, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r);
727 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
730 BMI(MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
731 BMI(MBB, IP, X86::FNSTSWr8, 0);
732 BMI(MBB, IP, X86::SAHF, 1);
736 if (OpNum < 2) { // seteq, setne
737 unsigned LoTmp = makeAnotherReg(Type::IntTy);
738 unsigned HiTmp = makeAnotherReg(Type::IntTy);
739 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
740 BMI(MBB, IP, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r);
741 BMI(MBB, IP, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
742 BMI(MBB, IP, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
743 break; // Allow the sete or setne to be generated from flags set by OR
745 // Emit a sequence of code which compares the high and low parts once
746 // each, then uses a conditional move to handle the overflow case. For
747 // example, a setlt for long would generate code like this:
749 // AL = lo(op1) < lo(op2) // Signedness depends on operands
750 // BL = hi(op1) < hi(op2) // Always unsigned comparison
751 // dest = hi(op1) == hi(op2) ? AL : BL;
754 // FIXME: This would be much better if we had hierarchical register
755 // classes! Until then, hardcode registers so that we can deal with their
756 // aliases (because we don't have conditional byte moves).
758 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
759 BMI(MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
760 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
761 BMI(MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
762 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
763 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
764 BMI(MBB, IP, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
765 // NOTE: visitSetCondInst knows that the value is dumped into the BL
766 // register at this point for long values...
774 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
775 /// register, then move it to wherever the result should be.
777 void ISel::visitSetCondInst(SetCondInst &I) {
778 if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
780 unsigned DestReg = getReg(I);
781 MachineBasicBlock::iterator MII = BB->end();
782 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
786 /// emitSetCCOperation - Common code shared between visitSetCondInst and
787 /// constant expression support.
788 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
789 MachineBasicBlock::iterator &IP,
790 Value *Op0, Value *Op1, unsigned Opcode,
791 unsigned TargetReg) {
792 unsigned OpNum = getSetCCNumber(Opcode);
793 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
795 const Type *CompTy = Op0->getType();
796 unsigned CompClass = getClassB(CompTy);
797 bool isSigned = CompTy->isSigned() && CompClass != cFP;
799 if (CompClass != cLong || OpNum < 2) {
800 // Handle normal comparisons with a setcc instruction...
801 BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
803 // Handle long comparisons by copying the value which is already in BL into
804 // the register we want...
805 BMI(MBB, IP, X86::MOVrr8, 1, TargetReg).addReg(X86::BL);
812 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
813 /// operand, in the specified target register.
814 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
815 bool isUnsigned = VR.Ty->isUnsigned();
817 // Make sure we have the register number for this value...
818 unsigned Reg = VR.Val ? getReg(VR.Val) : VR.Reg;
820 switch (getClassB(VR.Ty)) {
822 // Extend value into target register (8->32)
824 BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(Reg);
826 BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(Reg);
829 // Extend value into target register (16->32)
831 BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(Reg);
833 BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(Reg);
836 // Move value into target register (32->32)
837 BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(Reg);
840 assert(0 && "Unpromotable operand class in promote32");
844 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
845 /// we have the following possibilities:
847 /// ret void: No return value, simply emit a 'ret' instruction
848 /// ret sbyte, ubyte : Extend value into EAX and return
849 /// ret short, ushort: Extend value into EAX and return
850 /// ret int, uint : Move value into EAX and return
851 /// ret pointer : Move value into EAX and return
852 /// ret long, ulong : Move value into EAX/EDX and return
853 /// ret float/double : Top of FP stack
855 void ISel::visitReturnInst(ReturnInst &I) {
856 if (I.getNumOperands() == 0) {
858 BuildMI(BB, X86::FP_REG_KILL, 0);
860 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
864 Value *RetVal = I.getOperand(0);
865 unsigned RetReg = getReg(RetVal);
866 switch (getClassB(RetVal->getType())) {
867 case cByte: // integral return values: extend or move into EAX and return
870 promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
871 // Declare that EAX is live on exit
872 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
874 case cFP: // Floats & Doubles: Return in ST(0)
875 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
876 // Declare that top-of-stack is live on exit
877 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
880 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
881 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
882 // Declare that EAX & EDX are live on exit
883 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
889 // Emit a 'ret' instruction
891 BuildMI(BB, X86::FP_REG_KILL, 0);
893 BuildMI(BB, X86::RET, 0);
896 // getBlockAfter - Return the basic block which occurs lexically after the
898 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
899 Function::iterator I = BB; ++I; // Get iterator to next block
900 return I != BB->getParent()->end() ? &*I : 0;
903 /// RequiresFPRegKill - The floating point stackifier pass cannot insert
904 /// compensation code on critical edges. As such, it requires that we kill all
905 /// FP registers on the exit from any blocks that either ARE critical edges, or
906 /// branch to a block that has incoming critical edges.
908 /// Note that this kill instruction will eventually be eliminated when
909 /// restrictions in the stackifier are relaxed.
911 static bool RequiresFPRegKill(const BasicBlock *BB) {
913 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB); SI!=E; ++SI) {
914 const BasicBlock *Succ = *SI;
915 pred_const_iterator PI = pred_begin(Succ), PE = pred_end(Succ);
916 ++PI; // Block have at least one predecessory
917 if (PI != PE) { // If it has exactly one, this isn't crit edge
918 // If this block has more than one predecessor, check all of the
919 // predecessors to see if they have multiple successors. If so, then the
920 // block we are analyzing needs an FPRegKill.
921 for (PI = pred_begin(Succ); PI != PE; ++PI) {
922 const BasicBlock *Pred = *PI;
923 succ_const_iterator SI2 = succ_begin(Pred);
924 ++SI2; // There must be at least one successor of this block.
925 if (SI2 != succ_end(Pred))
926 return true; // Yes, we must insert the kill on this edge.
930 // If we got this far, there is no need to insert the kill instruction.
937 /// visitBranchInst - Handle conditional and unconditional branches here. Note
938 /// that since code layout is frozen at this point, that if we are trying to
939 /// jump to a block that is the immediate successor of the current block, we can
940 /// just make a fall-through (but we don't currently).
942 void ISel::visitBranchInst(BranchInst &BI) {
943 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
945 if (!BI.isConditional()) { // Unconditional branch?
946 if (RequiresFPRegKill(BI.getParent()))
947 BuildMI(BB, X86::FP_REG_KILL, 0);
948 if (BI.getSuccessor(0) != NextBB)
949 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
953 // See if we can fold the setcc into the branch itself...
954 SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
956 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
957 // computed some other way...
958 unsigned condReg = getReg(BI.getCondition());
959 BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
960 if (RequiresFPRegKill(BI.getParent()))
961 BuildMI(BB, X86::FP_REG_KILL, 0);
962 if (BI.getSuccessor(1) == NextBB) {
963 if (BI.getSuccessor(0) != NextBB)
964 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
966 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
968 if (BI.getSuccessor(0) != NextBB)
969 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
974 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
975 MachineBasicBlock::iterator MII = BB->end();
976 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
978 const Type *CompTy = SCI->getOperand(0)->getType();
979 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
982 // LLVM -> X86 signed X86 unsigned
983 // ----- ---------- ------------
991 // js // Used by comparison with 0 optimization
994 static const unsigned OpcodeTab[2][8] = {
995 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
996 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
1000 if (RequiresFPRegKill(BI.getParent()))
1001 BuildMI(BB, X86::FP_REG_KILL, 0);
1002 if (BI.getSuccessor(0) != NextBB) {
1003 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
1004 if (BI.getSuccessor(1) != NextBB)
1005 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
1007 // Change to the inverse condition...
1008 if (BI.getSuccessor(1) != NextBB) {
1010 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
1016 /// doCall - This emits an abstract call instruction, setting up the arguments
1017 /// and the return value as appropriate. For the actual function call itself,
1018 /// it inserts the specified CallMI instruction into the stream.
1020 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1021 const std::vector<ValueRecord> &Args) {
1023 // Count how many bytes are to be pushed on the stack...
1024 unsigned NumBytes = 0;
1026 if (!Args.empty()) {
1027 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1028 switch (getClassB(Args[i].Ty)) {
1029 case cByte: case cShort: case cInt:
1030 NumBytes += 4; break;
1032 NumBytes += 8; break;
1034 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
1036 default: assert(0 && "Unknown class!");
1039 // Adjust the stack pointer for the new arguments...
1040 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes);
1042 // Arguments go on the stack in reverse order, as specified by the ABI.
1043 unsigned ArgOffset = 0;
1044 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1045 unsigned ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1046 switch (getClassB(Args[i].Ty)) {
1049 // Promote arg to 32 bits wide into a temporary register...
1050 unsigned R = makeAnotherReg(Type::UIntTy);
1051 promote32(R, Args[i]);
1052 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1053 X86::ESP, ArgOffset).addReg(R);
1057 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1058 X86::ESP, ArgOffset).addReg(ArgReg);
1061 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1062 X86::ESP, ArgOffset).addReg(ArgReg);
1063 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1064 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
1065 ArgOffset += 4; // 8 byte entry, not 4.
1069 if (Args[i].Ty == Type::FloatTy) {
1070 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
1071 X86::ESP, ArgOffset).addReg(ArgReg);
1073 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
1074 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
1075 X86::ESP, ArgOffset).addReg(ArgReg);
1076 ArgOffset += 4; // 8 byte entry, not 4.
1080 default: assert(0 && "Unknown class!");
1085 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(0);
1088 BB->push_back(CallMI);
1090 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes);
1092 // If there is a return value, scavenge the result from the location the call
1095 if (Ret.Ty != Type::VoidTy) {
1096 unsigned DestClass = getClassB(Ret.Ty);
1097 switch (DestClass) {
1101 // Integral results are in %eax, or the appropriate portion
1103 static const unsigned regRegMove[] = {
1104 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
1106 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
1107 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
1110 case cFP: // Floating-point return values live in %ST(0)
1111 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
1113 case cLong: // Long values are left in EDX:EAX
1114 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg).addReg(X86::EAX);
1115 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg+1).addReg(X86::EDX);
1117 default: assert(0 && "Unknown class!");
1123 /// visitCallInst - Push args on stack and do a procedure call instruction.
1124 void ISel::visitCallInst(CallInst &CI) {
1125 MachineInstr *TheCall;
1126 if (Function *F = CI.getCalledFunction()) {
1127 // Is it an intrinsic function call?
1128 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1129 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1133 // Emit a CALL instruction with PC-relative displacement.
1134 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
1135 } else { // Emit an indirect call...
1136 unsigned Reg = getReg(CI.getCalledValue());
1137 TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg);
1140 std::vector<ValueRecord> Args;
1141 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1142 Args.push_back(ValueRecord(CI.getOperand(i)));
1144 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1145 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1149 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1150 /// function, lowering any calls to unknown intrinsic functions into the
1151 /// equivalent LLVM code.
1152 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1153 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1154 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1155 if (CallInst *CI = dyn_cast<CallInst>(I++))
1156 if (Function *F = CI->getCalledFunction())
1157 switch (F->getIntrinsicID()) {
1158 case Intrinsic::not_intrinsic:
1159 case Intrinsic::va_start:
1160 case Intrinsic::va_copy:
1161 case Intrinsic::va_end:
1162 // We directly implement these intrinsics
1165 // All other intrinsic calls we must lower.
1166 Instruction *Before = CI->getPrev();
1167 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1168 if (Before) { // Move iterator to instruction after call
1177 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1178 unsigned TmpReg1, TmpReg2;
1180 case Intrinsic::va_start:
1181 // Get the address of the first vararg value...
1182 TmpReg1 = getReg(CI);
1183 addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
1186 case Intrinsic::va_copy:
1187 TmpReg1 = getReg(CI);
1188 TmpReg2 = getReg(CI.getOperand(1));
1189 BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2);
1191 case Intrinsic::va_end: return; // Noop on X86
1193 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1198 /// visitSimpleBinary - Implement simple binary operators for integral types...
1199 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1201 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1202 unsigned DestReg = getReg(B);
1203 MachineBasicBlock::iterator MI = BB->end();
1204 emitSimpleBinaryOperation(BB, MI, B.getOperand(0), B.getOperand(1),
1205 OperatorClass, DestReg);
1208 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1209 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1212 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1213 /// and constant expression support.
1215 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1216 MachineBasicBlock::iterator &IP,
1217 Value *Op0, Value *Op1,
1218 unsigned OperatorClass, unsigned DestReg) {
1219 unsigned Class = getClassB(Op0->getType());
1221 // sub 0, X -> neg X
1222 if (OperatorClass == 1 && Class != cLong)
1223 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0)) {
1224 if (CI->isNullValue()) {
1225 unsigned op1Reg = getReg(Op1, MBB, IP);
1227 default: assert(0 && "Unknown class for this function!");
1229 BMI(MBB, IP, X86::NEGr8, 1, DestReg).addReg(op1Reg);
1232 BMI(MBB, IP, X86::NEGr16, 1, DestReg).addReg(op1Reg);
1235 BMI(MBB, IP, X86::NEGr32, 1, DestReg).addReg(op1Reg);
1239 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
1240 if (CFP->isExactlyValue(-0.0)) {
1242 unsigned op1Reg = getReg(Op1, MBB, IP);
1243 BMI(MBB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg);
1247 if (!isa<ConstantInt>(Op1) || Class == cLong) {
1248 static const unsigned OpcodeTab[][4] = {
1249 // Arithmetic operators
1250 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
1251 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
1253 // Bitwise operators
1254 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
1255 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
1256 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
1259 bool isLong = false;
1260 if (Class == cLong) {
1262 Class = cInt; // Bottom 32 bits are handled just like ints
1265 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1266 assert(Opcode && "Floating point arguments to logical inst?");
1267 unsigned Op0r = getReg(Op0, MBB, IP);
1268 unsigned Op1r = getReg(Op1, MBB, IP);
1269 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1271 if (isLong) { // Handle the upper 32 bits of long values...
1272 static const unsigned TopTab[] = {
1273 X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
1275 BMI(MBB, IP, TopTab[OperatorClass], 2,
1276 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
1281 // Special case: op Reg, <const>
1282 ConstantInt *Op1C = cast<ConstantInt>(Op1);
1283 unsigned Op0r = getReg(Op0, MBB, IP);
1285 // xor X, -1 -> not X
1286 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1287 static unsigned const NOTTab[] = { X86::NOTr8, X86::NOTr16, X86::NOTr32 };
1288 BMI(MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
1292 // add X, -1 -> dec X
1293 if (OperatorClass == 0 && Op1C->isAllOnesValue()) {
1294 static unsigned const DECTab[] = { X86::DECr8, X86::DECr16, X86::DECr32 };
1295 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1299 // add X, 1 -> inc X
1300 if (OperatorClass == 0 && Op1C->equalsInt(1)) {
1301 static unsigned const DECTab[] = { X86::INCr8, X86::INCr16, X86::INCr32 };
1302 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1306 static const unsigned OpcodeTab[][3] = {
1307 // Arithmetic operators
1308 { X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
1309 { X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
1311 // Bitwise operators
1312 { X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
1313 { X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
1314 { X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
1317 assert(Class < 3 && "General code handles 64-bit integer types!");
1318 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1319 uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
1321 // Mask off any upper bits of the constant, if there are any...
1322 Op1v &= (1ULL << (8 << Class)) - 1;
1323 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addZImm(Op1v);
1326 /// doMultiply - Emit appropriate instructions to multiply together the
1327 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1328 /// result should be given as DestTy.
1330 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
1331 unsigned DestReg, const Type *DestTy,
1332 unsigned op0Reg, unsigned op1Reg) {
1333 unsigned Class = getClass(DestTy);
1335 case cFP: // Floating point multiply
1336 BMI(BB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1340 BMI(BB, MBBI, Class == cInt ? X86::IMULrr32 : X86::IMULrr16, 2, DestReg)
1341 .addReg(op0Reg).addReg(op1Reg);
1344 // Must use the MUL instruction, which forces use of AL...
1345 BMI(MBB, MBBI, X86::MOVrr8, 1, X86::AL).addReg(op0Reg);
1346 BMI(MBB, MBBI, X86::MULr8, 1).addReg(op1Reg);
1347 BMI(MBB, MBBI, X86::MOVrr8, 1, DestReg).addReg(X86::AL);
1350 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
1354 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1355 // returns zero when the input is not exactly a power of two.
1356 static unsigned ExactLog2(unsigned Val) {
1357 if (Val == 0) return 0;
1360 if (Val & 1) return 0;
1367 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
1368 MachineBasicBlock::iterator &IP,
1369 unsigned DestReg, const Type *DestTy,
1370 unsigned op0Reg, unsigned ConstRHS) {
1371 unsigned Class = getClass(DestTy);
1373 // If the element size is exactly a power of 2, use a shift to get it.
1374 if (unsigned Shift = ExactLog2(ConstRHS)) {
1376 default: assert(0 && "Unknown class for this function!");
1378 BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1381 BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1384 BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1389 if (Class == cShort) {
1390 BMI(MBB, IP, X86::IMULri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1392 } else if (Class == cInt) {
1393 BMI(MBB, IP, X86::IMULri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1397 // Most general case, emit a normal multiply...
1398 static const unsigned MOVirTab[] = {
1399 X86::MOVir8, X86::MOVir16, X86::MOVir32
1402 unsigned TmpReg = makeAnotherReg(DestTy);
1403 BMI(MBB, IP, MOVirTab[Class], 1, TmpReg).addZImm(ConstRHS);
1405 // Emit a MUL to multiply the register holding the index by
1406 // elementSize, putting the result in OffsetReg.
1407 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
1410 /// visitMul - Multiplies are not simple binary operators because they must deal
1411 /// with the EAX register explicitly.
1413 void ISel::visitMul(BinaryOperator &I) {
1414 unsigned Op0Reg = getReg(I.getOperand(0));
1415 unsigned DestReg = getReg(I);
1417 // Simple scalar multiply?
1418 if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
1419 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1))) {
1420 unsigned Val = (unsigned)CI->getRawValue(); // Cannot be 64-bit constant
1421 MachineBasicBlock::iterator MBBI = BB->end();
1422 doMultiplyConst(BB, MBBI, DestReg, I.getType(), Op0Reg, Val);
1424 unsigned Op1Reg = getReg(I.getOperand(1));
1425 MachineBasicBlock::iterator MBBI = BB->end();
1426 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
1429 unsigned Op1Reg = getReg(I.getOperand(1));
1431 // Long value. We have to do things the hard way...
1432 // Multiply the two low parts... capturing carry into EDX
1433 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
1434 BuildMI(BB, X86::MULr32, 1).addReg(Op1Reg); // AL*BL
1436 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1437 BuildMI(BB, X86::MOVrr32, 1, DestReg).addReg(X86::EAX); // AL*BL
1438 BuildMI(BB, X86::MOVrr32, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32
1440 MachineBasicBlock::iterator MBBI = BB->end();
1441 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
1442 BMI(BB, MBBI, X86::IMULrr32, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
1444 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1445 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
1446 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1449 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1450 BMI(BB, MBBI, X86::IMULrr32, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
1452 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1453 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1458 /// visitDivRem - Handle division and remainder instructions... these
1459 /// instruction both require the same instructions to be generated, they just
1460 /// select the result from a different register. Note that both of these
1461 /// instructions work differently for signed and unsigned operands.
1463 void ISel::visitDivRem(BinaryOperator &I) {
1464 unsigned Op0Reg = getReg(I.getOperand(0));
1465 unsigned Op1Reg = getReg(I.getOperand(1));
1466 unsigned ResultReg = getReg(I);
1468 MachineBasicBlock::iterator IP = BB->end();
1469 emitDivRemOperation(BB, IP, Op0Reg, Op1Reg, I.getOpcode() == Instruction::Div,
1470 I.getType(), ResultReg);
1473 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1474 MachineBasicBlock::iterator &IP,
1475 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
1476 const Type *Ty, unsigned ResultReg) {
1477 unsigned Class = getClass(Ty);
1479 case cFP: // Floating point divide
1481 BMI(BB, IP, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1482 } else { // Floating point remainder...
1483 MachineInstr *TheCall =
1484 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1485 std::vector<ValueRecord> Args;
1486 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1487 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1488 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1492 static const char *FnName[] =
1493 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1495 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
1496 MachineInstr *TheCall =
1497 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
1499 std::vector<ValueRecord> Args;
1500 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1501 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1502 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1505 case cByte: case cShort: case cInt:
1506 break; // Small integrals, handled below...
1507 default: assert(0 && "Unknown class!");
1510 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1511 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1512 static const unsigned SarOpcode[]={ X86::SARir8, X86::SARir16, X86::SARir32 };
1513 static const unsigned ClrOpcode[]={ X86::MOVir8, X86::MOVir16, X86::MOVir32 };
1514 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
1516 static const unsigned DivOpcode[][4] = {
1517 { X86::DIVr8 , X86::DIVr16 , X86::DIVr32 , 0 }, // Unsigned division
1518 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
1521 bool isSigned = Ty->isSigned();
1522 unsigned Reg = Regs[Class];
1523 unsigned ExtReg = ExtRegs[Class];
1525 // Put the first operand into one of the A registers...
1526 BMI(BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
1529 // Emit a sign extension instruction...
1530 unsigned ShiftResult = makeAnotherReg(Ty);
1531 BMI(BB, IP, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
1532 BMI(BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
1534 // If unsigned, emit a zeroing instruction... (reg = 0)
1535 BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addZImm(0);
1538 // Emit the appropriate divide or remainder instruction...
1539 BMI(BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
1541 // Figure out which register we want to pick the result out of...
1542 unsigned DestReg = isDiv ? Reg : ExtReg;
1544 // Put the result into the destination register...
1545 BMI(BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
1549 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1550 /// for constant immediate shift values, and for constant immediate
1551 /// shift values equal to 1. Even the general case is sort of special,
1552 /// because the shift amount has to be in CL, not just any old register.
1554 void ISel::visitShiftInst(ShiftInst &I) {
1555 MachineBasicBlock::iterator IP = BB->end ();
1556 emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1),
1557 I.getOpcode () == Instruction::Shl, I.getType (),
1561 /// emitShiftOperation - Common code shared between visitShiftInst and
1562 /// constant expression support.
1563 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
1564 MachineBasicBlock::iterator &IP,
1565 Value *Op, Value *ShiftAmount, bool isLeftShift,
1566 const Type *ResultTy, unsigned DestReg) {
1567 unsigned SrcReg = getReg (Op, MBB, IP);
1568 bool isSigned = ResultTy->isSigned ();
1569 unsigned Class = getClass (ResultTy);
1571 static const unsigned ConstantOperand[][4] = {
1572 { X86::SHRir8, X86::SHRir16, X86::SHRir32, X86::SHRDir32 }, // SHR
1573 { X86::SARir8, X86::SARir16, X86::SARir32, X86::SHRDir32 }, // SAR
1574 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SHL
1575 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SAL = SHL
1578 static const unsigned NonConstantOperand[][4] = {
1579 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
1580 { X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
1581 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
1582 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
1585 // Longs, as usual, are handled specially...
1586 if (Class == cLong) {
1587 // If we have a constant shift, we can generate much more efficient code
1588 // than otherwise...
1590 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
1591 unsigned Amount = CUI->getValue();
1593 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1595 BMI(MBB, IP, Opc[3], 3,
1596 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1597 BMI(MBB, IP, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1599 BMI(MBB, IP, Opc[3], 3,
1600 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1601 BMI(MBB, IP, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1603 } else { // Shifting more than 32 bits
1606 BMI(MBB, IP, X86::SHLir32, 2,
1607 DestReg + 1).addReg(SrcReg).addZImm(Amount);
1608 BMI(MBB, IP, X86::MOVir32, 1,
1609 DestReg).addZImm(0);
1611 unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32;
1612 BMI(MBB, IP, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1613 BMI(MBB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1617 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1619 if (!isLeftShift && isSigned) {
1620 // If this is a SHR of a Long, then we need to do funny sign extension
1621 // stuff. TmpReg gets the value to use as the high-part if we are
1622 // shifting more than 32 bits.
1623 BMI(MBB, IP, X86::SARir32, 2, TmpReg).addReg(SrcReg).addZImm(31);
1625 // Other shifts use a fixed zero value if the shift is more than 32
1627 BMI(MBB, IP, X86::MOVir32, 1, TmpReg).addZImm(0);
1630 // Initialize CL with the shift amount...
1631 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
1632 BMI(MBB, IP, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmountReg);
1634 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
1635 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
1637 // TmpReg2 = shld inHi, inLo
1638 BMI(MBB, IP, X86::SHLDrr32, 2, TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
1639 // TmpReg3 = shl inLo, CL
1640 BMI(MBB, IP, X86::SHLrr32, 1, TmpReg3).addReg(SrcReg);
1642 // Set the flags to indicate whether the shift was by more than 32 bits.
1643 BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1645 // DestHi = (>32) ? TmpReg3 : TmpReg2;
1646 BMI(MBB, IP, X86::CMOVNErr32, 2,
1647 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
1648 // DestLo = (>32) ? TmpReg : TmpReg3;
1649 BMI(MBB, IP, X86::CMOVNErr32, 2,
1650 DestReg).addReg(TmpReg3).addReg(TmpReg);
1652 // TmpReg2 = shrd inLo, inHi
1653 BMI(MBB, IP, X86::SHRDrr32, 2, TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
1654 // TmpReg3 = s[ah]r inHi, CL
1655 BMI(MBB, IP, isSigned ? X86::SARrr32 : X86::SHRrr32, 1, TmpReg3)
1658 // Set the flags to indicate whether the shift was by more than 32 bits.
1659 BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1661 // DestLo = (>32) ? TmpReg3 : TmpReg2;
1662 BMI(MBB, IP, X86::CMOVNErr32, 2,
1663 DestReg).addReg(TmpReg2).addReg(TmpReg3);
1665 // DestHi = (>32) ? TmpReg : TmpReg3;
1666 BMI(MBB, IP, X86::CMOVNErr32, 2,
1667 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
1673 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
1674 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
1675 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
1677 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1678 BMI(MBB, IP, Opc[Class], 2,
1679 DestReg).addReg(SrcReg).addZImm(CUI->getValue());
1680 } else { // The shift amount is non-constant.
1681 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
1682 BMI(MBB, IP, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmountReg);
1684 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
1685 BMI(MBB, IP, Opc[Class], 1, DestReg).addReg(SrcReg);
1690 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
1691 /// instruction. The load and store instructions are the only place where we
1692 /// need to worry about the memory layout of the target machine.
1694 void ISel::visitLoadInst(LoadInst &I) {
1695 unsigned SrcAddrReg = getReg(I.getOperand(0));
1696 unsigned DestReg = getReg(I);
1698 unsigned Class = getClassB(I.getType());
1700 if (Class == cLong) {
1701 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), SrcAddrReg);
1702 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
1706 static const unsigned Opcodes[] = {
1707 X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr32
1709 unsigned Opcode = Opcodes[Class];
1710 if (I.getType() == Type::DoubleTy) Opcode = X86::FLDr64;
1711 addDirectMem(BuildMI(BB, Opcode, 4, DestReg), SrcAddrReg);
1714 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
1717 void ISel::visitStoreInst(StoreInst &I) {
1718 unsigned ValReg = getReg(I.getOperand(0));
1719 unsigned AddressReg = getReg(I.getOperand(1));
1721 const Type *ValTy = I.getOperand(0)->getType();
1722 unsigned Class = getClassB(ValTy);
1724 if (Class == cLong) {
1725 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
1726 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg,4).addReg(ValReg+1);
1730 static const unsigned Opcodes[] = {
1731 X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTr32
1733 unsigned Opcode = Opcodes[Class];
1734 if (ValTy == Type::DoubleTy) Opcode = X86::FSTr64;
1735 addDirectMem(BuildMI(BB, Opcode, 1+4), AddressReg).addReg(ValReg);
1739 /// visitCastInst - Here we have various kinds of copying with or without
1740 /// sign extension going on.
1741 void ISel::visitCastInst(CastInst &CI) {
1742 Value *Op = CI.getOperand(0);
1743 // If this is a cast from a 32-bit integer to a Long type, and the only uses
1744 // of the case are GEP instructions, then the cast does not need to be
1745 // generated explicitly, it will be folded into the GEP.
1746 if (CI.getType() == Type::LongTy &&
1747 (Op->getType() == Type::IntTy || Op->getType() == Type::UIntTy)) {
1748 bool AllUsesAreGEPs = true;
1749 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
1750 if (!isa<GetElementPtrInst>(*I)) {
1751 AllUsesAreGEPs = false;
1755 // No need to codegen this cast if all users are getelementptr instrs...
1756 if (AllUsesAreGEPs) return;
1759 unsigned DestReg = getReg(CI);
1760 MachineBasicBlock::iterator MI = BB->end();
1761 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
1764 /// emitCastOperation - Common code shared between visitCastInst and
1765 /// constant expression cast support.
1766 void ISel::emitCastOperation(MachineBasicBlock *BB,
1767 MachineBasicBlock::iterator &IP,
1768 Value *Src, const Type *DestTy,
1770 unsigned SrcReg = getReg(Src, BB, IP);
1771 const Type *SrcTy = Src->getType();
1772 unsigned SrcClass = getClassB(SrcTy);
1773 unsigned DestClass = getClassB(DestTy);
1775 // Implement casts to bool by using compare on the operand followed by set if
1776 // not zero on the result.
1777 if (DestTy == Type::BoolTy) {
1780 BMI(BB, IP, X86::TESTrr8, 2).addReg(SrcReg).addReg(SrcReg);
1783 BMI(BB, IP, X86::TESTrr16, 2).addReg(SrcReg).addReg(SrcReg);
1786 BMI(BB, IP, X86::TESTrr32, 2).addReg(SrcReg).addReg(SrcReg);
1789 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1790 BMI(BB, IP, X86::ORrr32, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
1794 assert(0 && "FIXME: implement cast FP to bool");
1798 // If the zero flag is not set, then the value is true, set the byte to
1800 BMI(BB, IP, X86::SETNEr, 1, DestReg);
1804 static const unsigned RegRegMove[] = {
1805 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV, X86::MOVrr32
1808 // Implement casts between values of the same type class (as determined by
1809 // getClass) by using a register-to-register move.
1810 if (SrcClass == DestClass) {
1811 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
1812 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
1813 } else if (SrcClass == cFP) {
1814 if (SrcTy == Type::FloatTy) { // double -> float
1815 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1816 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
1817 } else { // float -> double
1818 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1819 "Unknown cFP member!");
1820 // Truncate from double to float by storing to memory as short, then
1822 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
1823 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
1824 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1825 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
1827 } else if (SrcClass == cLong) {
1828 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1829 BMI(BB, IP, X86::MOVrr32, 1, DestReg+1).addReg(SrcReg+1);
1831 assert(0 && "Cannot handle this type of cast instruction!");
1837 // Handle cast of SMALLER int to LARGER int using a move with sign extension
1838 // or zero extension, depending on whether the source type was signed.
1839 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
1840 SrcClass < DestClass) {
1841 bool isLong = DestClass == cLong;
1842 if (isLong) DestClass = cInt;
1844 static const unsigned Opc[][4] = {
1845 { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, X86::MOVrr32 }, // s
1846 { X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16, X86::MOVrr32 } // u
1849 bool isUnsigned = SrcTy->isUnsigned();
1850 BMI(BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
1851 DestReg).addReg(SrcReg);
1853 if (isLong) { // Handle upper 32 bits as appropriate...
1854 if (isUnsigned) // Zero out top bits...
1855 BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1856 else // Sign extend bottom half...
1857 BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31);
1862 // Special case long -> int ...
1863 if (SrcClass == cLong && DestClass == cInt) {
1864 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1868 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
1869 // move out of AX or AL.
1870 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
1871 && SrcClass > DestClass) {
1872 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
1873 BMI(BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
1874 BMI(BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
1878 // Handle casts from integer to floating point now...
1879 if (DestClass == cFP) {
1880 // Promote the integer to a type supported by FLD. We do this because there
1881 // are no unsigned FLD instructions, so we must promote an unsigned value to
1882 // a larger signed value, then use FLD on the larger value.
1884 const Type *PromoteType = 0;
1885 unsigned PromoteOpcode;
1886 switch (SrcTy->getPrimitiveID()) {
1887 case Type::BoolTyID:
1888 case Type::SByteTyID:
1889 // We don't have the facilities for directly loading byte sized data from
1890 // memory (even signed). Promote it to 16 bits.
1891 PromoteType = Type::ShortTy;
1892 PromoteOpcode = X86::MOVSXr16r8;
1894 case Type::UByteTyID:
1895 PromoteType = Type::ShortTy;
1896 PromoteOpcode = X86::MOVZXr16r8;
1898 case Type::UShortTyID:
1899 PromoteType = Type::IntTy;
1900 PromoteOpcode = X86::MOVZXr32r16;
1902 case Type::UIntTyID: {
1903 // Make a 64 bit temporary... and zero out the top of it...
1904 unsigned TmpReg = makeAnotherReg(Type::LongTy);
1905 BMI(BB, IP, X86::MOVrr32, 1, TmpReg).addReg(SrcReg);
1906 BMI(BB, IP, X86::MOVir32, 1, TmpReg+1).addZImm(0);
1907 SrcTy = Type::LongTy;
1912 case Type::ULongTyID:
1913 assert("FIXME: not implemented: cast ulong X to fp type!");
1914 default: // No promotion needed...
1919 unsigned TmpReg = makeAnotherReg(PromoteType);
1920 BMI(BB, IP, SrcTy->isSigned() ? X86::MOVSXr16r8 : X86::MOVZXr16r8,
1921 1, TmpReg).addReg(SrcReg);
1922 SrcTy = PromoteType;
1923 SrcClass = getClass(PromoteType);
1927 // Spill the integer to memory and reload it from there...
1929 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
1931 if (SrcClass == cLong) {
1932 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5), FrameIdx).addReg(SrcReg);
1933 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5),
1934 FrameIdx, 4).addReg(SrcReg+1);
1936 static const unsigned Op1[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1937 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
1940 static const unsigned Op2[] =
1941 { 0/*byte*/, X86::FILDr16, X86::FILDr32, 0/*FP*/, X86::FILDr64 };
1942 addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
1946 // Handle casts from floating point to integer now...
1947 if (SrcClass == cFP) {
1948 // Change the floating point control register to use "round towards zero"
1949 // mode when truncating to an integer value.
1951 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1952 addFrameReference(BMI(BB, IP, X86::FNSTCWm16, 4), CWFrameIdx);
1954 // Load the old value of the high byte of the control word...
1955 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
1956 addFrameReference(BMI(BB, IP, X86::MOVmr8, 4, HighPartOfCW), CWFrameIdx, 1);
1958 // Set the high part to be round to zero...
1959 addFrameReference(BMI(BB, IP, X86::MOVim8, 5), CWFrameIdx, 1).addZImm(12);
1961 // Reload the modified control word now...
1962 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1964 // Restore the memory image of control word to original value
1965 addFrameReference(BMI(BB, IP, X86::MOVrm8, 5),
1966 CWFrameIdx, 1).addReg(HighPartOfCW);
1968 // We don't have the facilities for directly storing byte sized data to
1969 // memory. Promote it to 16 bits. We also must promote unsigned values to
1970 // larger classes because we only have signed FP stores.
1971 unsigned StoreClass = DestClass;
1972 const Type *StoreTy = DestTy;
1973 if (StoreClass == cByte || DestTy->isUnsigned())
1974 switch (StoreClass) {
1975 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
1976 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
1977 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
1978 // The following treatment of cLong may not be perfectly right,
1979 // but it survives chains of casts of the form
1980 // double->ulong->double.
1981 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
1982 default: assert(0 && "Unknown store class!");
1985 // Spill the integer to memory and reload it from there...
1987 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
1989 static const unsigned Op1[] =
1990 { 0, X86::FISTr16, X86::FISTr32, 0, X86::FISTPr64 };
1991 addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg);
1993 if (DestClass == cLong) {
1994 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg), FrameIdx);
1995 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg+1), FrameIdx, 4);
1997 static const unsigned Op2[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
1998 addFrameReference(BMI(BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
2001 // Reload the original control word now...
2002 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
2006 // Anything we haven't handled already, we can't (yet) handle at all.
2007 assert(0 && "Unhandled cast instruction!");
2011 /// visitVANextInst - Implement the va_next instruction...
2013 void ISel::visitVANextInst(VANextInst &I) {
2014 unsigned VAList = getReg(I.getOperand(0));
2015 unsigned DestReg = getReg(I);
2018 switch (I.getArgType()->getPrimitiveID()) {
2021 assert(0 && "Error: bad type for va_next instruction!");
2023 case Type::PointerTyID:
2024 case Type::UIntTyID:
2028 case Type::ULongTyID:
2029 case Type::LongTyID:
2030 case Type::DoubleTyID:
2035 // Increment the VAList pointer...
2036 BuildMI(BB, X86::ADDri32, 2, DestReg).addReg(VAList).addZImm(Size);
2039 void ISel::visitVAArgInst(VAArgInst &I) {
2040 unsigned VAList = getReg(I.getOperand(0));
2041 unsigned DestReg = getReg(I);
2043 switch (I.getType()->getPrimitiveID()) {
2046 assert(0 && "Error: bad type for va_next instruction!");
2048 case Type::PointerTyID:
2049 case Type::UIntTyID:
2051 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
2053 case Type::ULongTyID:
2054 case Type::LongTyID:
2055 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
2056 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), VAList, 4);
2058 case Type::DoubleTyID:
2059 addDirectMem(BuildMI(BB, X86::FLDr64, 4, DestReg), VAList);
2065 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
2066 unsigned outputReg = getReg(I);
2067 MachineBasicBlock::iterator MI = BB->end();
2068 emitGEPOperation(BB, MI, I.getOperand(0),
2069 I.op_begin()+1, I.op_end(), outputReg);
2072 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
2073 MachineBasicBlock::iterator &IP,
2074 Value *Src, User::op_iterator IdxBegin,
2075 User::op_iterator IdxEnd, unsigned TargetReg) {
2076 const TargetData &TD = TM.getTargetData();
2077 const Type *Ty = Src->getType();
2078 unsigned BaseReg = getReg(Src, MBB, IP);
2080 // GEPs have zero or more indices; we must perform a struct access
2081 // or array access for each one.
2082 for (GetElementPtrInst::op_iterator oi = IdxBegin,
2083 oe = IdxEnd; oi != oe; ++oi) {
2085 unsigned NextReg = BaseReg;
2086 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2087 // It's a struct access. idx is the index into the structure,
2088 // which names the field. This index must have ubyte type.
2089 const ConstantUInt *CUI = cast<ConstantUInt>(idx);
2090 assert(CUI->getType() == Type::UByteTy
2091 && "Funny-looking structure index in GEP");
2092 // Use the TargetData structure to pick out what the layout of
2093 // the structure is in memory. Since the structure index must
2094 // be constant, we can get its value and use it to find the
2095 // right byte offset from the StructLayout class's list of
2096 // structure member offsets.
2097 unsigned idxValue = CUI->getValue();
2098 unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue];
2100 NextReg = makeAnotherReg(Type::UIntTy);
2101 // Emit an ADD to add FieldOff to the basePtr.
2102 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff);
2104 // The next type is the member of the structure selected by the
2106 Ty = StTy->getElementType(idxValue);
2107 } else if (const SequentialType *SqTy = cast<SequentialType>(Ty)) {
2108 // It's an array or pointer access: [ArraySize x ElementType].
2110 // idx is the index into the array. Unlike with structure
2111 // indices, we may not know its actual value at code-generation
2113 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
2115 // Most GEP instructions use a [cast (int/uint) to LongTy] as their
2116 // operand on X86. Handle this case directly now...
2117 if (CastInst *CI = dyn_cast<CastInst>(idx))
2118 if (CI->getOperand(0)->getType() == Type::IntTy ||
2119 CI->getOperand(0)->getType() == Type::UIntTy)
2120 idx = CI->getOperand(0);
2122 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
2123 // must find the size of the pointed-to type (Not coincidentally, the next
2124 // type is the type of the elements in the array).
2125 Ty = SqTy->getElementType();
2126 unsigned elementSize = TD.getTypeSize(Ty);
2128 // If idxReg is a constant, we don't need to perform the multiply!
2129 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
2130 if (!CSI->isNullValue()) {
2131 unsigned Offset = elementSize*CSI->getValue();
2132 NextReg = makeAnotherReg(Type::UIntTy);
2133 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(Offset);
2135 } else if (elementSize == 1) {
2136 // If the element size is 1, we don't have to multiply, just add
2137 unsigned idxReg = getReg(idx, MBB, IP);
2138 NextReg = makeAnotherReg(Type::UIntTy);
2139 BMI(MBB, IP, X86::ADDrr32, 2, NextReg).addReg(BaseReg).addReg(idxReg);
2141 unsigned idxReg = getReg(idx, MBB, IP);
2142 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
2144 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
2146 // Emit an ADD to add OffsetReg to the basePtr.
2147 NextReg = makeAnotherReg(Type::UIntTy);
2148 BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg);
2151 // Now that we are here, further indices refer to subtypes of this
2152 // one, so we don't need to worry about BaseReg itself, anymore.
2155 // After we have processed all the indices, the result is left in
2156 // BaseReg. Move it to the register where we were expected to
2157 // put the answer. A 32-bit move should do it, because we are in
2159 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
2163 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2164 /// frame manager, otherwise do it the hard way.
2166 void ISel::visitAllocaInst(AllocaInst &I) {
2167 // Find the data size of the alloca inst's getAllocatedType.
2168 const Type *Ty = I.getAllocatedType();
2169 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2171 // If this is a fixed size alloca in the entry block for the function,
2172 // statically stack allocate the space.
2174 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
2175 if (I.getParent() == I.getParent()->getParent()->begin()) {
2176 TySize *= CUI->getValue(); // Get total allocated size...
2177 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
2179 // Create a new stack object using the frame manager...
2180 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
2181 addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx);
2186 // Create a register to hold the temporary result of multiplying the type size
2187 // constant by the variable amount.
2188 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2189 unsigned SrcReg1 = getReg(I.getArraySize());
2191 // TotalSizeReg = mul <numelements>, <TypeSize>
2192 MachineBasicBlock::iterator MBBI = BB->end();
2193 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
2195 // AddedSize = add <TotalSizeReg>, 15
2196 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2197 BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15);
2199 // AlignedSize = and <AddedSize>, ~15
2200 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2201 BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15);
2203 // Subtract size from stack pointer, thereby allocating some space.
2204 BuildMI(BB, X86::SUBrr32, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
2206 // Put a pointer to the space into the result register, by copying
2207 // the stack pointer.
2208 BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP);
2210 // Inform the Frame Information that we have just allocated a variable-sized
2212 F->getFrameInfo()->CreateVariableSizedObject();
2215 /// visitMallocInst - Malloc instructions are code generated into direct calls
2216 /// to the library malloc.
2218 void ISel::visitMallocInst(MallocInst &I) {
2219 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2222 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2223 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2225 Arg = makeAnotherReg(Type::UIntTy);
2226 unsigned Op0Reg = getReg(I.getOperand(0));
2227 MachineBasicBlock::iterator MBBI = BB->end();
2228 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
2231 std::vector<ValueRecord> Args;
2232 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2233 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2234 1).addExternalSymbol("malloc", true);
2235 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
2239 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2242 void ISel::visitFreeInst(FreeInst &I) {
2243 std::vector<ValueRecord> Args;
2244 Args.push_back(ValueRecord(I.getOperand(0)));
2245 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2246 1).addExternalSymbol("free", true);
2247 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
2250 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
2251 /// into a machine code representation is a very simple peep-hole fashion. The
2252 /// generated code sucks but the implementation is nice and simple.
2254 FunctionPass *llvm::createX86SimpleInstructionSelector(TargetMachine &TM) {
2255 return new ISel(TM);