1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // This file defines a simple peephole instruction selector for the x86 target
5 //===----------------------------------------------------------------------===//
8 #include "X86InstrInfo.h"
9 #include "X86InstrBuilder.h"
10 #include "llvm/Function.h"
11 #include "llvm/Instructions.h"
12 #include "llvm/DerivedTypes.h"
13 #include "llvm/Constants.h"
14 #include "llvm/Pass.h"
15 #include "llvm/Intrinsics.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/SSARegMap.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "llvm/Support/InstVisitor.h"
25 /// BMI - A special BuildMI variant that takes an iterator to insert the
26 /// instruction at as well as a basic block. This is the version for when you
27 /// have a destination register in mind.
28 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
29 MachineBasicBlock::iterator &I,
33 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
34 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
35 I = MBB->insert(I, MI)+1;
36 return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
39 /// BMI - A special BuildMI variant that takes an iterator to insert the
40 /// instruction at as well as a basic block.
41 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
42 MachineBasicBlock::iterator &I,
44 unsigned NumOperands) {
45 assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
46 MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
47 I = MBB->insert(I, MI)+1;
48 return MachineInstrBuilder(MI);
53 struct ISel : public FunctionPass, InstVisitor<ISel> {
55 MachineFunction *F; // The function we are compiling into
56 MachineBasicBlock *BB; // The current MBB we are compiling
57 int VarArgsFrameIndex; // FrameIndex for start of varargs area
59 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
61 // MBBMap - Mapping between LLVM BB -> Machine BB
62 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
64 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
66 /// runOnFunction - Top level implementation of instruction selection for
67 /// the entire function.
69 bool runOnFunction(Function &Fn) {
70 F = &MachineFunction::construct(&Fn, TM);
72 // Create all of the machine basic blocks for the function...
73 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
74 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
78 // Copy incoming arguments off of the stack...
79 LoadArgumentsToVirtualRegs(Fn);
81 // Instruction select everything except PHI nodes
84 // Select the PHI nodes
90 return false; // We never modify the LLVM itself.
93 virtual const char *getPassName() const {
94 return "X86 Simple Instruction Selection";
97 /// visitBasicBlock - This method is called when we are visiting a new basic
98 /// block. This simply creates a new MachineBasicBlock to emit code into
99 /// and adds it to the current MachineFunction. Subsequent visit* for
100 /// instructions will be invoked for all instructions in the basic block.
102 void visitBasicBlock(BasicBlock &LLVM_BB) {
103 BB = MBBMap[&LLVM_BB];
106 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
107 /// from the stack into virtual registers.
109 void LoadArgumentsToVirtualRegs(Function &F);
111 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
112 /// because we have to generate our sources into the source basic blocks,
113 /// not the current one.
115 void SelectPHINodes();
117 // Visitation methods for various instructions. These methods simply emit
118 // fixed X86 code for each instruction.
121 // Control flow operators
122 void visitReturnInst(ReturnInst &RI);
123 void visitBranchInst(BranchInst &BI);
128 ValueRecord(unsigned R, const Type *T) : Reg(R), Ty(T) {}
130 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
131 const std::vector<ValueRecord> &Args);
132 void visitCallInst(CallInst &I);
133 void visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &I);
135 // Arithmetic operators
136 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
137 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
138 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
139 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
140 unsigned DestReg, const Type *DestTy,
141 unsigned Op0Reg, unsigned Op1Reg);
142 void visitMul(BinaryOperator &B);
144 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
145 void visitRem(BinaryOperator &B) { visitDivRem(B); }
146 void visitDivRem(BinaryOperator &B);
149 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
150 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
151 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
153 // Comparison operators...
154 void visitSetCondInst(SetCondInst &I);
155 bool EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1);
157 // Memory Instructions
158 MachineInstr *doFPLoad(MachineBasicBlock *MBB,
159 MachineBasicBlock::iterator &MBBI,
160 const Type *Ty, unsigned DestReg);
161 void visitLoadInst(LoadInst &I);
162 void doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg);
163 void visitStoreInst(StoreInst &I);
164 void visitGetElementPtrInst(GetElementPtrInst &I);
165 void visitAllocaInst(AllocaInst &I);
166 void visitMallocInst(MallocInst &I);
167 void visitFreeInst(FreeInst &I);
170 void visitShiftInst(ShiftInst &I);
171 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
172 void visitCastInst(CastInst &I);
173 void visitVarArgInst(VarArgInst &I);
175 void visitInstruction(Instruction &I) {
176 std::cerr << "Cannot instruction select: " << I;
180 /// promote32 - Make a value 32-bits wide, and put it somewhere.
182 void promote32(unsigned targetReg, const ValueRecord &VR);
184 /// EmitByteSwap - Byteswap SrcReg into DestReg.
186 void EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class);
188 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
189 /// constant expression GEP support.
191 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator&IP,
192 Value *Src, User::op_iterator IdxBegin,
193 User::op_iterator IdxEnd, unsigned TargetReg);
195 /// emitCastOperation - Common code shared between visitCastInst and
196 /// constant expression cast support.
197 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator&IP,
198 Value *Src, const Type *DestTy, unsigned TargetReg);
200 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
201 /// and constant expression support.
202 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
203 MachineBasicBlock::iterator &IP,
204 Value *Op0, Value *Op1,
205 unsigned OperatorClass, unsigned TargetReg);
207 /// copyConstantToRegister - Output the instructions required to put the
208 /// specified constant into the specified register.
210 void copyConstantToRegister(MachineBasicBlock *MBB,
211 MachineBasicBlock::iterator &MBBI,
212 Constant *C, unsigned Reg);
214 /// makeAnotherReg - This method returns the next register number we haven't
217 /// Long values are handled somewhat specially. They are always allocated
218 /// as pairs of 32 bit integer values. The register number returned is the
219 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
220 /// of the long value.
222 unsigned makeAnotherReg(const Type *Ty) {
223 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
224 const TargetRegisterClass *RC =
225 TM.getRegisterInfo()->getRegClassForType(Type::IntTy);
226 // Create the lower part
227 F->getSSARegMap()->createVirtualRegister(RC);
228 // Create the upper part.
229 return F->getSSARegMap()->createVirtualRegister(RC)-1;
232 // Add the mapping of regnumber => reg class to MachineFunction
233 const TargetRegisterClass *RC =
234 TM.getRegisterInfo()->getRegClassForType(Ty);
235 return F->getSSARegMap()->createVirtualRegister(RC);
238 /// getReg - This method turns an LLVM value into a register number. This
239 /// is guaranteed to produce the same register number for a particular value
240 /// every time it is queried.
242 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
243 unsigned getReg(Value *V) {
244 // Just append to the end of the current bb.
245 MachineBasicBlock::iterator It = BB->end();
246 return getReg(V, BB, It);
248 unsigned getReg(Value *V, MachineBasicBlock *MBB,
249 MachineBasicBlock::iterator &IPt) {
250 unsigned &Reg = RegMap[V];
252 Reg = makeAnotherReg(V->getType());
256 // If this operand is a constant, emit the code to copy the constant into
257 // the register here...
259 if (Constant *C = dyn_cast<Constant>(V)) {
260 copyConstantToRegister(MBB, IPt, C, Reg);
261 RegMap.erase(V); // Assign a new name to this constant if ref'd again
262 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
263 // Move the address of the global into the register
264 BMI(MBB, IPt, X86::MOVir32, 1, Reg).addGlobalAddress(GV);
265 RegMap.erase(V); // Assign a new name to this address if ref'd again
273 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
277 cByte, cShort, cInt, cFP, cLong
280 /// getClass - Turn a primitive type into a "class" number which is based on the
281 /// size of the type, and whether or not it is floating point.
283 static inline TypeClass getClass(const Type *Ty) {
284 switch (Ty->getPrimitiveID()) {
285 case Type::SByteTyID:
286 case Type::UByteTyID: return cByte; // Byte operands are class #0
287 case Type::ShortTyID:
288 case Type::UShortTyID: return cShort; // Short operands are class #1
291 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
293 case Type::FloatTyID:
294 case Type::DoubleTyID: return cFP; // Floating Point is #3
297 case Type::ULongTyID: return cLong; // Longs are class #4
299 assert(0 && "Invalid type to getClass!");
300 return cByte; // not reached
304 // getClassB - Just like getClass, but treat boolean values as bytes.
305 static inline TypeClass getClassB(const Type *Ty) {
306 if (Ty == Type::BoolTy) return cByte;
311 /// copyConstantToRegister - Output the instructions required to put the
312 /// specified constant into the specified register.
314 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
315 MachineBasicBlock::iterator &IP,
316 Constant *C, unsigned R) {
317 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
319 switch (CE->getOpcode()) {
320 case Instruction::GetElementPtr:
321 emitGEPOperation(MBB, IP, CE->getOperand(0),
322 CE->op_begin()+1, CE->op_end(), R);
324 case Instruction::Cast:
325 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
328 case Instruction::Xor: ++Class; // FALL THROUGH
329 case Instruction::Or: ++Class; // FALL THROUGH
330 case Instruction::And: ++Class; // FALL THROUGH
331 case Instruction::Sub: ++Class; // FALL THROUGH
332 case Instruction::Add:
333 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
338 std::cerr << "Offending expr: " << C << "\n";
339 assert(0 && "Constant expressions not yet handled!\n");
343 if (C->getType()->isIntegral()) {
344 unsigned Class = getClassB(C->getType());
346 if (Class == cLong) {
347 // Copy the value into the register pair.
349 if (C->getType()->isSigned())
350 Val = cast<ConstantSInt>(C)->getValue();
352 Val = cast<ConstantUInt>(C)->getValue();
354 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(Val & 0xFFFFFFFF);
355 BMI(MBB, IP, X86::MOVir32, 1, R+1).addZImm(Val >> 32);
359 assert(Class <= cInt && "Type not handled yet!");
361 static const unsigned IntegralOpcodeTab[] = {
362 X86::MOVir8, X86::MOVir16, X86::MOVir32
365 if (C->getType() == Type::BoolTy) {
366 BMI(MBB, IP, X86::MOVir8, 1, R).addZImm(C == ConstantBool::True);
367 } else if (C->getType()->isSigned()) {
368 ConstantSInt *CSI = cast<ConstantSInt>(C);
369 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CSI->getValue());
371 ConstantUInt *CUI = cast<ConstantUInt>(C);
372 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
374 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
375 double Value = CFP->getValue();
377 BMI(MBB, IP, X86::FLD0, 0, R);
378 else if (Value == +1.0)
379 BMI(MBB, IP, X86::FLD1, 0, R);
381 // Otherwise we need to spill the constant to memory...
382 MachineConstantPool *CP = F->getConstantPool();
383 unsigned CPI = CP->getConstantPoolIndex(CFP);
384 addConstantPoolReference(doFPLoad(MBB, IP, CFP->getType(), R), CPI);
387 } else if (isa<ConstantPointerNull>(C)) {
388 // Copy zero (null pointer) to the register.
389 BMI(MBB, IP, X86::MOVir32, 1, R).addZImm(0);
390 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
391 unsigned SrcReg = getReg(CPR->getValue(), MBB, IP);
392 BMI(MBB, IP, X86::MOVrr32, 1, R).addReg(SrcReg);
394 std::cerr << "Offending constant: " << C << "\n";
395 assert(0 && "Type not handled yet!");
399 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
400 /// the stack into virtual registers.
402 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
403 // Emit instructions to load the arguments... On entry to a function on the
404 // X86, the stack frame looks like this:
406 // [ESP] -- return address
407 // [ESP + 4] -- first argument (leftmost lexically)
408 // [ESP + 8] -- second argument, if first argument is four bytes in size
411 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
412 MachineFrameInfo *MFI = F->getFrameInfo();
414 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
415 unsigned Reg = getReg(*I);
417 int FI; // Frame object index
418 switch (getClassB(I->getType())) {
420 FI = MFI->CreateFixedObject(1, ArgOffset);
421 addFrameReference(BuildMI(BB, X86::MOVmr8, 4, Reg), FI);
424 FI = MFI->CreateFixedObject(2, ArgOffset);
425 addFrameReference(BuildMI(BB, X86::MOVmr16, 4, Reg), FI);
428 FI = MFI->CreateFixedObject(4, ArgOffset);
429 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
432 FI = MFI->CreateFixedObject(8, ArgOffset);
433 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg), FI);
434 addFrameReference(BuildMI(BB, X86::MOVmr32, 4, Reg+1), FI, 4);
435 ArgOffset += 4; // longs require 4 additional bytes
439 if (I->getType() == Type::FloatTy) {
440 Opcode = X86::FLDr32;
441 FI = MFI->CreateFixedObject(4, ArgOffset);
443 Opcode = X86::FLDr64;
444 FI = MFI->CreateFixedObject(8, ArgOffset);
445 ArgOffset += 4; // doubles require 4 additional bytes
447 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
450 assert(0 && "Unhandled argument type!");
452 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
455 // If the function takes variable number of arguments, add a frame offset for
456 // the start of the first vararg value... this is used to expand
458 if (Fn.getFunctionType()->isVarArg())
459 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
463 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
464 /// because we have to generate our sources into the source basic blocks, not
467 void ISel::SelectPHINodes() {
468 const TargetInstrInfo &TII = TM.getInstrInfo();
469 const Function &LF = *F->getFunction(); // The LLVM function...
470 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
471 const BasicBlock *BB = I;
472 MachineBasicBlock *MBB = MBBMap[I];
474 // Loop over all of the PHI nodes in the LLVM basic block...
475 unsigned NumPHIs = 0;
476 for (BasicBlock::const_iterator I = BB->begin();
477 PHINode *PN = (PHINode*)dyn_cast<PHINode>(I); ++I) {
479 // Create a new machine instr PHI node, and insert it.
480 unsigned PHIReg = getReg(*PN);
481 MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
482 MBB->insert(MBB->begin()+NumPHIs++, PhiMI);
484 MachineInstr *LongPhiMI = 0;
485 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
486 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
487 MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
490 // PHIValues - Map of blocks to incoming virtual registers. We use this
491 // so that we only initialize one incoming value for a particular block,
492 // even if the block has multiple entries in the PHI node.
494 std::map<MachineBasicBlock*, unsigned> PHIValues;
496 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
497 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
499 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
500 PHIValues.lower_bound(PredMBB);
502 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
503 // We already inserted an initialization of the register for this
504 // predecessor. Recycle it.
505 ValReg = EntryIt->second;
508 // Get the incoming value into a virtual register. If it is not
509 // already available in a virtual register, insert the computation
512 MachineBasicBlock::iterator PI = PredMBB->end();
513 while (PI != PredMBB->begin() &&
514 TII.isTerminatorInstr((*(PI-1))->getOpcode()))
516 ValReg = getReg(PN->getIncomingValue(i), PredMBB, PI);
518 // Remember that we inserted a value for this PHI for this predecessor
519 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
522 PhiMI->addRegOperand(ValReg);
523 PhiMI->addMachineBasicBlockOperand(PredMBB);
525 LongPhiMI->addRegOperand(ValReg+1);
526 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
533 // canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
534 // the conditional branch instruction which is the only user of the cc
535 // instruction. This is the case if the conditional branch is the only user of
536 // the setcc, and if the setcc is in the same basic block as the conditional
537 // branch. We also don't handle long arguments below, so we reject them here as
540 static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
541 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
542 if (SCI->use_size() == 1 && isa<BranchInst>(SCI->use_back()) &&
543 SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
544 const Type *Ty = SCI->getOperand(0)->getType();
545 if (Ty != Type::LongTy && Ty != Type::ULongTy)
551 // Return a fixed numbering for setcc instructions which does not depend on the
552 // order of the opcodes.
554 static unsigned getSetCCNumber(unsigned Opcode) {
556 default: assert(0 && "Unknown setcc instruction!");
557 case Instruction::SetEQ: return 0;
558 case Instruction::SetNE: return 1;
559 case Instruction::SetLT: return 2;
560 case Instruction::SetGE: return 3;
561 case Instruction::SetGT: return 4;
562 case Instruction::SetLE: return 5;
566 // LLVM -> X86 signed X86 unsigned
567 // ----- ---------- ------------
568 // seteq -> sete sete
569 // setne -> setne setne
570 // setlt -> setl setb
571 // setge -> setge setae
572 // setgt -> setg seta
573 // setle -> setle setbe
574 static const unsigned SetCCOpcodeTab[2][6] = {
575 {X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr},
576 {X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr},
579 bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1) {
581 // The arguments are already supposed to be of the same type.
582 const Type *CompTy = Op0->getType();
583 bool isSigned = CompTy->isSigned();
584 unsigned reg1 = getReg(Op0);
585 unsigned reg2 = getReg(Op1);
587 unsigned Class = getClassB(CompTy);
589 default: assert(0 && "Unknown type class!");
590 // Emit: cmp <var1>, <var2> (do the comparison). We can
591 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
594 BuildMI(BB, X86::CMPrr8, 2).addReg(reg1).addReg(reg2);
597 BuildMI(BB, X86::CMPrr16, 2).addReg(reg1).addReg(reg2);
600 BuildMI(BB, X86::CMPrr32, 2).addReg(reg1).addReg(reg2);
603 BuildMI(BB, X86::FpUCOM, 2).addReg(reg1).addReg(reg2);
604 BuildMI(BB, X86::FNSTSWr8, 0);
605 BuildMI(BB, X86::SAHF, 1);
606 isSigned = false; // Compare with unsigned operators
610 if (OpNum < 2) { // seteq, setne
611 unsigned LoTmp = makeAnotherReg(Type::IntTy);
612 unsigned HiTmp = makeAnotherReg(Type::IntTy);
613 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
614 BuildMI(BB, X86::XORrr32, 2, LoTmp).addReg(reg1).addReg(reg2);
615 BuildMI(BB, X86::XORrr32, 2, HiTmp).addReg(reg1+1).addReg(reg2+1);
616 BuildMI(BB, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
617 break; // Allow the sete or setne to be generated from flags set by OR
619 // Emit a sequence of code which compares the high and low parts once
620 // each, then uses a conditional move to handle the overflow case. For
621 // example, a setlt for long would generate code like this:
623 // AL = lo(op1) < lo(op2) // Signedness depends on operands
624 // BL = hi(op1) < hi(op2) // Always unsigned comparison
625 // dest = hi(op1) == hi(op2) ? AL : BL;
628 // FIXME: This would be much better if we had hierarchical register
629 // classes! Until then, hardcode registers so that we can deal with their
630 // aliases (because we don't have conditional byte moves).
632 BuildMI(BB, X86::CMPrr32, 2).addReg(reg1).addReg(reg2);
633 BuildMI(BB, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
634 BuildMI(BB, X86::CMPrr32, 2).addReg(reg1+1).addReg(reg2+1);
635 BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
636 BuildMI(BB, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
637 // NOTE: visitSetCondInst knows that the value is dumped into the BL
638 // register at this point for long values...
646 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
647 /// register, then move it to wherever the result should be.
649 void ISel::visitSetCondInst(SetCondInst &I) {
650 if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
652 unsigned OpNum = getSetCCNumber(I.getOpcode());
653 unsigned DestReg = getReg(I);
654 bool isSigned = EmitComparisonGetSignedness(OpNum, I.getOperand(0),
657 if (getClassB(I.getOperand(0)->getType()) != cLong || OpNum < 2) {
658 // Handle normal comparisons with a setcc instruction...
659 BuildMI(BB, SetCCOpcodeTab[isSigned][OpNum], 0, DestReg);
661 // Handle long comparisons by copying the value which is already in BL into
662 // the register we want...
663 BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(X86::BL);
667 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
668 /// operand, in the specified target register.
669 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
670 bool isUnsigned = VR.Ty->isUnsigned();
671 switch (getClassB(VR.Ty)) {
673 // Extend value into target register (8->32)
675 BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(VR.Reg);
677 BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(VR.Reg);
680 // Extend value into target register (16->32)
682 BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(VR.Reg);
684 BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(VR.Reg);
687 // Move value into target register (32->32)
688 BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(VR.Reg);
691 assert(0 && "Unpromotable operand class in promote32");
695 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
696 /// we have the following possibilities:
698 /// ret void: No return value, simply emit a 'ret' instruction
699 /// ret sbyte, ubyte : Extend value into EAX and return
700 /// ret short, ushort: Extend value into EAX and return
701 /// ret int, uint : Move value into EAX and return
702 /// ret pointer : Move value into EAX and return
703 /// ret long, ulong : Move value into EAX/EDX and return
704 /// ret float/double : Top of FP stack
706 void ISel::visitReturnInst(ReturnInst &I) {
707 if (I.getNumOperands() == 0) {
708 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
712 Value *RetVal = I.getOperand(0);
713 unsigned RetReg = getReg(RetVal);
714 switch (getClassB(RetVal->getType())) {
715 case cByte: // integral return values: extend or move into EAX and return
718 promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
719 // Declare that EAX is live on exit
720 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
722 case cFP: // Floats & Doubles: Return in ST(0)
723 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
724 // Declare that top-of-stack is live on exit
725 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
728 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
729 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
730 // Declare that EAX & EDX are live on exit
731 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX).addReg(X86::ESP);
736 // Emit a 'ret' instruction
737 BuildMI(BB, X86::RET, 0);
740 // getBlockAfter - Return the basic block which occurs lexically after the
742 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
743 Function::iterator I = BB; ++I; // Get iterator to next block
744 return I != BB->getParent()->end() ? &*I : 0;
747 /// visitBranchInst - Handle conditional and unconditional branches here. Note
748 /// that since code layout is frozen at this point, that if we are trying to
749 /// jump to a block that is the immediate successor of the current block, we can
750 /// just make a fall-through (but we don't currently).
752 void ISel::visitBranchInst(BranchInst &BI) {
753 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
755 if (!BI.isConditional()) { // Unconditional branch?
756 if (BI.getSuccessor(0) != NextBB)
757 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
761 // See if we can fold the setcc into the branch itself...
762 SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
764 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
765 // computed some other way...
766 unsigned condReg = getReg(BI.getCondition());
767 BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
768 if (BI.getSuccessor(1) == NextBB) {
769 if (BI.getSuccessor(0) != NextBB)
770 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
772 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
774 if (BI.getSuccessor(0) != NextBB)
775 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
780 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
781 bool isSigned = EmitComparisonGetSignedness(OpNum, SCI->getOperand(0),
784 // LLVM -> X86 signed X86 unsigned
785 // ----- ---------- ------------
792 static const unsigned OpcodeTab[2][6] = {
793 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE },
794 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE },
797 if (BI.getSuccessor(0) != NextBB) {
798 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
799 if (BI.getSuccessor(1) != NextBB)
800 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
802 // Change to the inverse condition...
803 if (BI.getSuccessor(1) != NextBB) {
805 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
811 /// doCall - This emits an abstract call instruction, setting up the arguments
812 /// and the return value as appropriate. For the actual function call itself,
813 /// it inserts the specified CallMI instruction into the stream.
815 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
816 const std::vector<ValueRecord> &Args) {
818 // Count how many bytes are to be pushed on the stack...
819 unsigned NumBytes = 0;
822 for (unsigned i = 0, e = Args.size(); i != e; ++i)
823 switch (getClassB(Args[i].Ty)) {
824 case cByte: case cShort: case cInt:
825 NumBytes += 4; break;
827 NumBytes += 8; break;
829 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
831 default: assert(0 && "Unknown class!");
834 // Adjust the stack pointer for the new arguments...
835 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes);
837 // Arguments go on the stack in reverse order, as specified by the ABI.
838 unsigned ArgOffset = 0;
839 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
840 unsigned ArgReg = Args[i].Reg;
841 switch (getClassB(Args[i].Ty)) {
844 // Promote arg to 32 bits wide into a temporary register...
845 unsigned R = makeAnotherReg(Type::UIntTy);
846 promote32(R, Args[i]);
847 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
848 X86::ESP, ArgOffset).addReg(R);
852 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
853 X86::ESP, ArgOffset).addReg(ArgReg);
856 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
857 X86::ESP, ArgOffset).addReg(ArgReg);
858 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
859 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
860 ArgOffset += 4; // 8 byte entry, not 4.
864 if (Args[i].Ty == Type::FloatTy) {
865 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
866 X86::ESP, ArgOffset).addReg(ArgReg);
868 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
869 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
870 X86::ESP, ArgOffset).addReg(ArgReg);
871 ArgOffset += 4; // 8 byte entry, not 4.
875 default: assert(0 && "Unknown class!");
880 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(0);
883 BB->push_back(CallMI);
885 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes);
887 // If there is a return value, scavenge the result from the location the call
890 if (Ret.Ty != Type::VoidTy) {
891 unsigned DestClass = getClassB(Ret.Ty);
896 // Integral results are in %eax, or the appropriate portion
898 static const unsigned regRegMove[] = {
899 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
901 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
902 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
905 case cFP: // Floating-point return values live in %ST(0)
906 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
908 case cLong: // Long values are left in EDX:EAX
909 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg).addReg(X86::EAX);
910 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg+1).addReg(X86::EDX);
912 default: assert(0 && "Unknown class!");
918 /// visitCallInst - Push args on stack and do a procedure call instruction.
919 void ISel::visitCallInst(CallInst &CI) {
920 MachineInstr *TheCall;
921 if (Function *F = CI.getCalledFunction()) {
922 // Is it an intrinsic function call?
923 if (LLVMIntrinsic::ID ID = (LLVMIntrinsic::ID)F->getIntrinsicID()) {
924 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
928 // Emit a CALL instruction with PC-relative displacement.
929 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
930 } else { // Emit an indirect call...
931 unsigned Reg = getReg(CI.getCalledValue());
932 TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg);
935 std::vector<ValueRecord> Args;
936 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
937 Args.push_back(ValueRecord(getReg(CI.getOperand(i)),
938 CI.getOperand(i)->getType()));
940 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
941 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
944 void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) {
945 unsigned TmpReg1, TmpReg2;
947 case LLVMIntrinsic::va_start:
948 // Get the address of the first vararg value...
949 TmpReg1 = makeAnotherReg(Type::UIntTy);
950 addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
951 TmpReg2 = getReg(CI.getOperand(1));
952 addDirectMem(BuildMI(BB, X86::MOVrm32, 5), TmpReg2).addReg(TmpReg1);
955 case LLVMIntrinsic::va_end: return; // Noop on X86
956 case LLVMIntrinsic::va_copy:
957 TmpReg1 = getReg(CI.getOperand(2)); // Get existing va_list
958 TmpReg2 = getReg(CI.getOperand(1)); // Get va_list* to store into
959 addDirectMem(BuildMI(BB, X86::MOVrm32, 5), TmpReg2).addReg(TmpReg1);
962 default: assert(0 && "Unknown intrinsic for X86!");
967 /// visitSimpleBinary - Implement simple binary operators for integral types...
968 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
970 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
971 unsigned DestReg = getReg(B);
972 MachineBasicBlock::iterator MI = BB->end();
973 emitSimpleBinaryOperation(BB, MI, B.getOperand(0), B.getOperand(1),
974 OperatorClass, DestReg);
977 /// visitSimpleBinary - Implement simple binary operators for integral types...
978 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
981 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
982 /// and constant expression support.
983 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *BB,
984 MachineBasicBlock::iterator &IP,
985 Value *Op0, Value *Op1,
986 unsigned OperatorClass,unsigned TargetReg){
987 unsigned Class = getClassB(Op0->getType());
989 static const unsigned OpcodeTab[][4] = {
990 // Arithmetic operators
991 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
992 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
995 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
996 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
997 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
1000 bool isLong = false;
1001 if (Class == cLong) {
1003 Class = cInt; // Bottom 32 bits are handled just like ints
1006 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1007 assert(Opcode && "Floating point arguments to logical inst?");
1008 unsigned Op0r = getReg(Op0, BB, IP);
1009 unsigned Op1r = getReg(Op1, BB, IP);
1010 BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addReg(Op1r);
1012 if (isLong) { // Handle the upper 32 bits of long values...
1013 static const unsigned TopTab[] = {
1014 X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
1016 BMI(BB, IP, TopTab[OperatorClass], 2,
1017 TargetReg+1).addReg(Op0r+1).addReg(Op1r+1);
1021 /// doMultiply - Emit appropriate instructions to multiply together the
1022 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1023 /// result should be given as DestTy.
1025 /// FIXME: doMultiply should use one of the two address IMUL instructions!
1027 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
1028 unsigned DestReg, const Type *DestTy,
1029 unsigned op0Reg, unsigned op1Reg) {
1030 unsigned Class = getClass(DestTy);
1032 case cFP: // Floating point multiply
1033 BMI(BB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1036 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
1039 case cInt: // Small integerals, handled below...
1043 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1044 static const unsigned MulOpcode[]={ X86::MULr8 , X86::MULr16 , X86::MULr32 };
1045 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1046 unsigned Reg = Regs[Class];
1048 // Emit a MOV to put the first operand into the appropriately-sized
1050 BMI(MBB, MBBI, MovOpcode[Class], 1, Reg).addReg(op0Reg);
1052 // Emit the appropriate multiply instruction.
1053 BMI(MBB, MBBI, MulOpcode[Class], 1).addReg(op1Reg);
1055 // Emit another MOV to put the result into the destination register.
1056 BMI(MBB, MBBI, MovOpcode[Class], 1, DestReg).addReg(Reg);
1059 /// visitMul - Multiplies are not simple binary operators because they must deal
1060 /// with the EAX register explicitly.
1062 void ISel::visitMul(BinaryOperator &I) {
1063 unsigned Op0Reg = getReg(I.getOperand(0));
1064 unsigned Op1Reg = getReg(I.getOperand(1));
1065 unsigned DestReg = getReg(I);
1067 // Simple scalar multiply?
1068 if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
1069 MachineBasicBlock::iterator MBBI = BB->end();
1070 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
1072 // Long value. We have to do things the hard way...
1073 // Multiply the two low parts... capturing carry into EDX
1074 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
1075 BuildMI(BB, X86::MULr32, 1).addReg(Op1Reg); // AL*BL
1077 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1078 BuildMI(BB, X86::MOVrr32, 1, DestReg).addReg(X86::EAX); // AL*BL
1079 BuildMI(BB, X86::MOVrr32, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32
1081 MachineBasicBlock::iterator MBBI = BB->end();
1082 unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
1083 doMultiply(BB, MBBI, AHBLReg, Type::UIntTy, Op0Reg+1, Op1Reg); // AH*BL
1085 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1086 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
1087 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1090 unsigned ALBHReg = makeAnotherReg(Type::UIntTy);
1091 doMultiply(BB, MBBI, ALBHReg, Type::UIntTy, Op0Reg, Op1Reg+1); // AL*BH
1093 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1094 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1099 /// visitDivRem - Handle division and remainder instructions... these
1100 /// instruction both require the same instructions to be generated, they just
1101 /// select the result from a different register. Note that both of these
1102 /// instructions work differently for signed and unsigned operands.
1104 void ISel::visitDivRem(BinaryOperator &I) {
1105 unsigned Class = getClass(I.getType());
1106 unsigned Op0Reg = getReg(I.getOperand(0));
1107 unsigned Op1Reg = getReg(I.getOperand(1));
1108 unsigned ResultReg = getReg(I);
1111 case cFP: // Floating point divide
1112 if (I.getOpcode() == Instruction::Div)
1113 BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1114 else { // Floating point remainder...
1115 MachineInstr *TheCall =
1116 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1117 std::vector<ValueRecord> Args;
1118 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1119 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1120 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1124 static const char *FnName[] =
1125 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1127 unsigned NameIdx = I.getType()->isUnsigned()*2;
1128 NameIdx += I.getOpcode() == Instruction::Div;
1129 MachineInstr *TheCall =
1130 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
1132 std::vector<ValueRecord> Args;
1133 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1134 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1135 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1138 case cByte: case cShort: case cInt:
1139 break; // Small integerals, handled below...
1140 default: assert(0 && "Unknown class!");
1143 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1144 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1145 static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
1146 static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
1147 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
1149 static const unsigned DivOpcode[][4] = {
1150 { X86::DIVr8 , X86::DIVr16 , X86::DIVr32 , 0 }, // Unsigned division
1151 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
1154 bool isSigned = I.getType()->isSigned();
1155 unsigned Reg = Regs[Class];
1156 unsigned ExtReg = ExtRegs[Class];
1158 // Put the first operand into one of the A registers...
1159 BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
1162 // Emit a sign extension instruction...
1163 BuildMI(BB, ExtOpcode[Class], 0);
1165 // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
1166 BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
1169 // Emit the appropriate divide or remainder instruction...
1170 BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
1172 // Figure out which register we want to pick the result out of...
1173 unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
1175 // Put the result into the destination register...
1176 BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
1180 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1181 /// for constant immediate shift values, and for constant immediate
1182 /// shift values equal to 1. Even the general case is sort of special,
1183 /// because the shift amount has to be in CL, not just any old register.
1185 void ISel::visitShiftInst(ShiftInst &I) {
1186 unsigned SrcReg = getReg(I.getOperand(0));
1187 unsigned DestReg = getReg(I);
1188 bool isLeftShift = I.getOpcode() == Instruction::Shl;
1189 bool isSigned = I.getType()->isSigned();
1190 unsigned Class = getClass(I.getType());
1192 static const unsigned ConstantOperand[][4] = {
1193 { X86::SHRir8, X86::SHRir16, X86::SHRir32, X86::SHRDir32 }, // SHR
1194 { X86::SARir8, X86::SARir16, X86::SARir32, X86::SHRDir32 }, // SAR
1195 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SHL
1196 { X86::SHLir8, X86::SHLir16, X86::SHLir32, X86::SHLDir32 }, // SAL = SHL
1199 static const unsigned NonConstantOperand[][4] = {
1200 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
1201 { X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
1202 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
1203 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
1206 // Longs, as usual, are handled specially...
1207 if (Class == cLong) {
1208 // If we have a constant shift, we can generate much more efficient code
1209 // than otherwise...
1211 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getOperand(1))) {
1212 unsigned Amount = CUI->getValue();
1214 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1216 BuildMI(BB, Opc[3], 3,
1217 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1218 BuildMI(BB, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1220 BuildMI(BB, Opc[3], 3,
1221 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1222 BuildMI(BB, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1224 } else { // Shifting more than 32 bits
1227 BuildMI(BB, X86::SHLir32, 2,DestReg+1).addReg(SrcReg).addZImm(Amount);
1228 BuildMI(BB, X86::MOVir32, 1,DestReg ).addZImm(0);
1230 unsigned Opcode = isSigned ? X86::SARir32 : X86::SHRir32;
1231 BuildMI(BB, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1232 BuildMI(BB, X86::MOVir32, 1, DestReg+1).addZImm(0);
1236 visitInstruction(I); // FIXME: Implement long shift by non-constant
1241 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getOperand(1))) {
1242 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
1243 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
1245 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1246 BuildMI(BB, Opc[Class], 2, DestReg).addReg(SrcReg).addZImm(CUI->getValue());
1247 } else { // The shift amount is non-constant.
1248 BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
1250 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
1251 BuildMI(BB, Opc[Class], 1, DestReg).addReg(SrcReg);
1256 /// doFPLoad - This method is used to load an FP value from memory using the
1257 /// current endianness. NOTE: This method returns a partially constructed load
1258 /// instruction which needs to have the memory source filled in still.
1260 MachineInstr *ISel::doFPLoad(MachineBasicBlock *MBB,
1261 MachineBasicBlock::iterator &MBBI,
1262 const Type *Ty, unsigned DestReg) {
1263 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1264 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
1266 if (TM.getTargetData().isLittleEndian()) // fast path...
1267 return BMI(MBB, MBBI, LoadOpcode, 4, DestReg);
1269 // If we are big-endian, start by creating an LEA instruction to represent the
1270 // address of the memory location to load from...
1272 unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy);
1273 MachineInstr *Result = BMI(MBB, MBBI, X86::LEAr32, 5, SrcAddrReg);
1275 // Allocate a temporary stack slot to transform the value into...
1276 int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData());
1278 // Perform the bswaps 32 bits at a time...
1279 unsigned TmpReg1 = makeAnotherReg(Type::UIntTy);
1280 unsigned TmpReg2 = makeAnotherReg(Type::UIntTy);
1281 addDirectMem(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg);
1282 BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1283 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1284 addFrameReference(BMI(MBB, MBBI, X86::MOVrm32, 5),
1285 FrameIdx, Offset).addReg(TmpReg2);
1287 if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value...
1288 TmpReg1 = makeAnotherReg(Type::UIntTy);
1289 TmpReg2 = makeAnotherReg(Type::UIntTy);
1291 addRegOffset(BMI(MBB, MBBI, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4);
1292 BMI(MBB, MBBI, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1293 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1294 addFrameReference(BMI(MBB, MBBI, X86::MOVrm32,5), FrameIdx).addReg(TmpReg2);
1297 // Now we can reload the final byteswapped result into the final destination.
1298 addFrameReference(BMI(MBB, MBBI, LoadOpcode, 4, DestReg), FrameIdx);
1302 /// EmitByteSwap - Byteswap SrcReg into DestReg.
1304 void ISel::EmitByteSwap(unsigned DestReg, unsigned SrcReg, unsigned Class) {
1305 // Emit the byte swap instruction...
1308 // No byteswap necessary for 8 bit value...
1309 BuildMI(BB, X86::MOVrr8, 1, DestReg).addReg(SrcReg);
1312 // Use the 32 bit bswap instruction to do a 32 bit swap...
1313 BuildMI(BB, X86::BSWAPr32, 1, DestReg).addReg(SrcReg);
1317 // For 16 bit we have to use an xchg instruction, because there is no
1318 // 16-bit bswap. XCHG is necessarily not in SSA form, so we force things
1319 // into AX to do the xchg.
1321 BuildMI(BB, X86::MOVrr16, 1, X86::AX).addReg(SrcReg);
1322 BuildMI(BB, X86::XCHGrr8, 2).addReg(X86::AL, MOTy::UseAndDef)
1323 .addReg(X86::AH, MOTy::UseAndDef);
1324 BuildMI(BB, X86::MOVrr16, 1, DestReg).addReg(X86::AX);
1326 default: assert(0 && "Cannot byteswap this class!");
1331 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
1332 /// instruction. The load and store instructions are the only place where we
1333 /// need to worry about the memory layout of the target machine.
1335 void ISel::visitLoadInst(LoadInst &I) {
1336 bool isLittleEndian = TM.getTargetData().isLittleEndian();
1337 bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
1338 unsigned SrcAddrReg = getReg(I.getOperand(0));
1339 unsigned DestReg = getReg(I);
1341 unsigned Class = getClass(I.getType());
1344 MachineBasicBlock::iterator MBBI = BB->end();
1345 addDirectMem(doFPLoad(BB, MBBI, I.getType(), DestReg), SrcAddrReg);
1348 case cLong: case cInt: case cShort: case cByte:
1349 break; // Integers of various sizes handled below
1350 default: assert(0 && "Unknown memory class!");
1353 // We need to adjust the input pointer if we are emulating a big-endian
1354 // long-pointer target. On these systems, the pointer that we are interested
1355 // in is in the upper part of the eight byte memory image of the pointer. It
1356 // also happens to be byte-swapped, but this will be handled later.
1358 if (!isLittleEndian && hasLongPointers && isa<PointerType>(I.getType())) {
1359 unsigned R = makeAnotherReg(Type::UIntTy);
1360 BuildMI(BB, X86::ADDri32, 2, R).addReg(SrcAddrReg).addZImm(4);
1364 unsigned IReg = DestReg;
1365 if (!isLittleEndian) // If big endian we need an intermediate stage
1366 DestReg = makeAnotherReg(Class != cLong ? I.getType() : Type::UIntTy);
1368 static const unsigned Opcode[] = {
1369 X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, 0, X86::MOVmr32
1371 addDirectMem(BuildMI(BB, Opcode[Class], 4, DestReg), SrcAddrReg);
1373 // Handle long values now...
1374 if (Class == cLong) {
1375 if (isLittleEndian) {
1376 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), SrcAddrReg, 4);
1378 EmitByteSwap(IReg+1, DestReg, cInt);
1379 unsigned TempReg = makeAnotherReg(Type::IntTy);
1380 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TempReg), SrcAddrReg, 4);
1381 EmitByteSwap(IReg, TempReg, cInt);
1386 if (!isLittleEndian)
1387 EmitByteSwap(IReg, DestReg, Class);
1391 /// doFPStore - This method is used to store an FP value to memory using the
1392 /// current endianness.
1394 void ISel::doFPStore(const Type *Ty, unsigned DestAddrReg, unsigned SrcReg) {
1395 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1396 unsigned StoreOpcode = Ty == Type::FloatTy ? X86::FSTr32 : X86::FSTr64;
1398 if (TM.getTargetData().isLittleEndian()) { // fast path...
1399 addDirectMem(BuildMI(BB, StoreOpcode,5), DestAddrReg).addReg(SrcReg);
1403 // Allocate a temporary stack slot to transform the value into...
1404 int FrameIdx = F->getFrameInfo()->CreateStackObject(Ty, TM.getTargetData());
1405 unsigned SrcAddrReg = makeAnotherReg(Type::UIntTy);
1406 addFrameReference(BuildMI(BB, X86::LEAr32, 5, SrcAddrReg), FrameIdx);
1408 // Store the value into a temporary stack slot...
1409 addDirectMem(BuildMI(BB, StoreOpcode, 5), SrcAddrReg).addReg(SrcReg);
1411 // Perform the bswaps 32 bits at a time...
1412 unsigned TmpReg1 = makeAnotherReg(Type::UIntTy);
1413 unsigned TmpReg2 = makeAnotherReg(Type::UIntTy);
1414 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg);
1415 BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1416 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1417 addRegOffset(BuildMI(BB, X86::MOVrm32, 5),
1418 DestAddrReg, Offset).addReg(TmpReg2);
1420 if (Ty == Type::DoubleTy) { // Swap the other 32 bits of a double value...
1421 TmpReg1 = makeAnotherReg(Type::UIntTy);
1422 TmpReg2 = makeAnotherReg(Type::UIntTy);
1424 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, TmpReg1), SrcAddrReg, 4);
1425 BuildMI(BB, X86::BSWAPr32, 1, TmpReg2).addReg(TmpReg1);
1426 unsigned Offset = (Ty == Type::DoubleTy) << 2;
1427 addDirectMem(BuildMI(BB, X86::MOVrm32, 5), DestAddrReg).addReg(TmpReg2);
1432 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
1435 void ISel::visitStoreInst(StoreInst &I) {
1436 bool isLittleEndian = TM.getTargetData().isLittleEndian();
1437 bool hasLongPointers = TM.getTargetData().getPointerSize() == 8;
1438 unsigned ValReg = getReg(I.getOperand(0));
1439 unsigned AddressReg = getReg(I.getOperand(1));
1441 unsigned Class = getClass(I.getOperand(0)->getType());
1444 if (isLittleEndian) {
1445 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(ValReg);
1446 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4),
1447 AddressReg, 4).addReg(ValReg+1);
1449 unsigned T1 = makeAnotherReg(Type::IntTy);
1450 unsigned T2 = makeAnotherReg(Type::IntTy);
1451 EmitByteSwap(T1, ValReg , cInt);
1452 EmitByteSwap(T2, ValReg+1, cInt);
1453 addDirectMem(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg).addReg(T2);
1454 addRegOffset(BuildMI(BB, X86::MOVrm32, 1+4), AddressReg, 4).addReg(T1);
1458 doFPStore(I.getOperand(0)->getType(), AddressReg, ValReg);
1460 case cInt: case cShort: case cByte:
1461 break; // Integers of various sizes handled below
1462 default: assert(0 && "Unknown memory class!");
1465 if (!isLittleEndian && hasLongPointers &&
1466 isa<PointerType>(I.getOperand(0)->getType())) {
1467 unsigned R = makeAnotherReg(Type::UIntTy);
1468 BuildMI(BB, X86::ADDri32, 2, R).addReg(AddressReg).addZImm(4);
1472 if (!isLittleEndian && Class != cByte) {
1473 unsigned R = makeAnotherReg(I.getOperand(0)->getType());
1474 EmitByteSwap(R, ValReg, Class);
1478 static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1479 addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
1483 /// visitCastInst - Here we have various kinds of copying with or without
1484 /// sign extension going on.
1485 void ISel::visitCastInst(CastInst &CI) {
1486 unsigned DestReg = getReg(CI);
1487 MachineBasicBlock::iterator MI = BB->end();
1488 emitCastOperation(BB, MI, CI.getOperand(0), CI.getType(), DestReg);
1491 /// emitCastOperation - Common code shared between visitCastInst and
1492 /// constant expression cast support.
1493 void ISel::emitCastOperation(MachineBasicBlock *BB,
1494 MachineBasicBlock::iterator &IP,
1495 Value *Src, const Type *DestTy,
1497 unsigned SrcReg = getReg(Src, BB, IP);
1498 const Type *SrcTy = Src->getType();
1499 unsigned SrcClass = getClassB(SrcTy);
1500 unsigned DestClass = getClassB(DestTy);
1502 // Implement casts to bool by using compare on the operand followed by set if
1503 // not zero on the result.
1504 if (DestTy == Type::BoolTy) {
1505 if (SrcClass == cFP || SrcClass == cLong)
1506 abort(); // FIXME: implement cast (long & FP) to bool
1508 BMI(BB, IP, X86::CMPri8, 2).addReg(SrcReg).addZImm(0);
1509 BMI(BB, IP, X86::SETNEr, 1, DestReg);
1513 static const unsigned RegRegMove[] = {
1514 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV, X86::MOVrr32
1517 // Implement casts between values of the same type class (as determined by
1518 // getClass) by using a register-to-register move.
1519 if (SrcClass == DestClass) {
1520 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
1521 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
1522 } else if (SrcClass == cFP) {
1523 if (SrcTy == Type::FloatTy) { // double -> float
1524 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
1525 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
1526 } else { // float -> double
1527 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
1528 "Unknown cFP member!");
1529 // Truncate from double to float by storing to memory as short, then
1531 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
1532 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
1533 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
1534 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
1536 } else if (SrcClass == cLong) {
1537 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1538 BMI(BB, IP, X86::MOVrr32, 1, DestReg+1).addReg(SrcReg+1);
1540 assert(0 && "Cannot handle this type of cast instruction!");
1546 // Handle cast of SMALLER int to LARGER int using a move with sign extension
1547 // or zero extension, depending on whether the source type was signed.
1548 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
1549 SrcClass < DestClass) {
1550 bool isLong = DestClass == cLong;
1551 if (isLong) DestClass = cInt;
1553 static const unsigned Opc[][4] = {
1554 { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, X86::MOVrr32 }, // s
1555 { X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16, X86::MOVrr32 } // u
1558 bool isUnsigned = SrcTy->isUnsigned();
1559 BMI(BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
1560 DestReg).addReg(SrcReg);
1562 if (isLong) { // Handle upper 32 bits as appropriate...
1563 if (isUnsigned) // Zero out top bits...
1564 BMI(BB, IP, X86::MOVir32, 1, DestReg+1).addZImm(0);
1565 else // Sign extend bottom half...
1566 BMI(BB, IP, X86::SARir32, 2, DestReg+1).addReg(DestReg).addZImm(31);
1571 // Special case long -> int ...
1572 if (SrcClass == cLong && DestClass == cInt) {
1573 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
1577 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
1578 // move out of AX or AL.
1579 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
1580 && SrcClass > DestClass) {
1581 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
1582 BMI(BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
1583 BMI(BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
1587 // Handle casts from integer to floating point now...
1588 if (DestClass == cFP) {
1589 // Promote the integer to a type supported by FLD. We do this because there
1590 // are no unsigned FLD instructions, so we must promote an unsigned value to
1591 // a larger signed value, then use FLD on the larger value.
1593 const Type *PromoteType = 0;
1594 unsigned PromoteOpcode;
1595 switch (SrcTy->getPrimitiveID()) {
1596 case Type::BoolTyID:
1597 case Type::SByteTyID:
1598 // We don't have the facilities for directly loading byte sized data from
1599 // memory (even signed). Promote it to 16 bits.
1600 PromoteType = Type::ShortTy;
1601 PromoteOpcode = X86::MOVSXr16r8;
1603 case Type::UByteTyID:
1604 PromoteType = Type::ShortTy;
1605 PromoteOpcode = X86::MOVZXr16r8;
1607 case Type::UShortTyID:
1608 PromoteType = Type::IntTy;
1609 PromoteOpcode = X86::MOVZXr32r16;
1611 case Type::UIntTyID: {
1612 // Make a 64 bit temporary... and zero out the top of it...
1613 unsigned TmpReg = makeAnotherReg(Type::LongTy);
1614 BMI(BB, IP, X86::MOVrr32, 1, TmpReg).addReg(SrcReg);
1615 BMI(BB, IP, X86::MOVir32, 1, TmpReg+1).addZImm(0);
1616 SrcTy = Type::LongTy;
1621 case Type::ULongTyID:
1622 assert("FIXME: not implemented: cast ulong X to fp type!");
1623 default: // No promotion needed...
1628 unsigned TmpReg = makeAnotherReg(PromoteType);
1629 BMI(BB, IP, SrcTy->isSigned() ? X86::MOVSXr16r8 : X86::MOVZXr16r8,
1630 1, TmpReg).addReg(SrcReg);
1631 SrcTy = PromoteType;
1632 SrcClass = getClass(PromoteType);
1636 // Spill the integer to memory and reload it from there...
1638 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
1640 if (SrcClass == cLong) {
1641 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5), FrameIdx).addReg(SrcReg);
1642 addFrameReference(BMI(BB, IP, X86::MOVrm32, 5),
1643 FrameIdx, 4).addReg(SrcReg+1);
1645 static const unsigned Op1[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
1646 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
1649 static const unsigned Op2[] =
1650 { 0/*byte*/, X86::FILDr16, X86::FILDr32, 0/*FP*/, X86::FILDr64 };
1651 addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
1655 // Handle casts from floating point to integer now...
1656 if (SrcClass == cFP) {
1657 // Change the floating point control register to use "round towards zero"
1658 // mode when truncating to an integer value.
1660 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1661 addFrameReference(BMI(BB, IP, X86::FNSTCWm16, 4), CWFrameIdx);
1663 // Load the old value of the high byte of the control word...
1664 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
1665 addFrameReference(BMI(BB, IP, X86::MOVmr8, 4, HighPartOfCW), CWFrameIdx, 1);
1667 // Set the high part to be round to zero...
1668 addFrameReference(BMI(BB, IP, X86::MOVim8, 5), CWFrameIdx, 1).addZImm(12);
1670 // Reload the modified control word now...
1671 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1673 // Restore the memory image of control word to original value
1674 addFrameReference(BMI(BB, IP, X86::MOVrm8, 5),
1675 CWFrameIdx, 1).addReg(HighPartOfCW);
1677 // We don't have the facilities for directly storing byte sized data to
1678 // memory. Promote it to 16 bits. We also must promote unsigned values to
1679 // larger classes because we only have signed FP stores.
1680 unsigned StoreClass = DestClass;
1681 const Type *StoreTy = DestTy;
1682 if (StoreClass == cByte || DestTy->isUnsigned())
1683 switch (StoreClass) {
1684 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
1685 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
1686 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
1688 assert(0 &&"FIXME not implemented: cast FP to unsigned long long");
1690 default: assert(0 && "Unknown store class!");
1693 // Spill the integer to memory and reload it from there...
1695 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
1697 static const unsigned Op1[] =
1698 { 0, X86::FISTr16, X86::FISTr32, 0, X86::FISTPr64 };
1699 addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg);
1701 if (DestClass == cLong) {
1702 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg), FrameIdx);
1703 addFrameReference(BMI(BB, IP, X86::MOVmr32, 4, DestReg+1), FrameIdx, 4);
1705 static const unsigned Op2[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
1706 addFrameReference(BMI(BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
1709 // Reload the original control word now...
1710 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
1714 // Anything we haven't handled already, we can't (yet) handle at all.
1715 assert(0 && "Unhandled cast instruction!");
1719 /// visitVarArgInst - Implement the va_arg instruction...
1721 void ISel::visitVarArgInst(VarArgInst &I) {
1722 unsigned SrcReg = getReg(I.getOperand(0));
1723 unsigned DestReg = getReg(I);
1725 // Load the va_list into a register...
1726 unsigned VAList = makeAnotherReg(Type::UIntTy);
1727 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, VAList), SrcReg);
1730 switch (I.getType()->getPrimitiveID()) {
1733 assert(0 && "Error: bad type for va_arg instruction!");
1735 case Type::PointerTyID:
1736 case Type::UIntTyID:
1739 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
1741 case Type::ULongTyID:
1742 case Type::LongTyID:
1744 addDirectMem(BuildMI(BB, X86::MOVmr32, 4, DestReg), VAList);
1745 addRegOffset(BuildMI(BB, X86::MOVmr32, 4, DestReg+1), VAList, 4);
1747 case Type::DoubleTyID:
1749 addDirectMem(BuildMI(BB, X86::FLDr64, 4, DestReg), VAList);
1753 // Increment the VAList pointer...
1754 unsigned NextVAList = makeAnotherReg(Type::UIntTy);
1755 BuildMI(BB, X86::ADDri32, 2, NextVAList).addReg(VAList).addZImm(Size);
1757 // Update the VAList in memory...
1758 addDirectMem(BuildMI(BB, X86::MOVrm32, 5), SrcReg).addReg(NextVAList);
1762 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1763 // returns zero when the input is not exactly a power of two.
1764 static unsigned ExactLog2(unsigned Val) {
1765 if (Val == 0) return 0;
1768 if (Val & 1) return 0;
1775 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
1776 unsigned outputReg = getReg(I);
1777 MachineBasicBlock::iterator MI = BB->end();
1778 emitGEPOperation(BB, MI, I.getOperand(0),
1779 I.op_begin()+1, I.op_end(), outputReg);
1782 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
1783 MachineBasicBlock::iterator &IP,
1784 Value *Src, User::op_iterator IdxBegin,
1785 User::op_iterator IdxEnd, unsigned TargetReg) {
1786 const TargetData &TD = TM.getTargetData();
1787 const Type *Ty = Src->getType();
1788 unsigned BaseReg = getReg(Src, MBB, IP);
1790 // GEPs have zero or more indices; we must perform a struct access
1791 // or array access for each one.
1792 for (GetElementPtrInst::op_iterator oi = IdxBegin,
1793 oe = IdxEnd; oi != oe; ++oi) {
1795 unsigned NextReg = BaseReg;
1796 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1797 // It's a struct access. idx is the index into the structure,
1798 // which names the field. This index must have ubyte type.
1799 const ConstantUInt *CUI = cast<ConstantUInt>(idx);
1800 assert(CUI->getType() == Type::UByteTy
1801 && "Funny-looking structure index in GEP");
1802 // Use the TargetData structure to pick out what the layout of
1803 // the structure is in memory. Since the structure index must
1804 // be constant, we can get its value and use it to find the
1805 // right byte offset from the StructLayout class's list of
1806 // structure member offsets.
1807 unsigned idxValue = CUI->getValue();
1808 unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue];
1810 NextReg = makeAnotherReg(Type::UIntTy);
1811 // Emit an ADD to add FieldOff to the basePtr.
1812 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(FieldOff);
1814 // The next type is the member of the structure selected by the
1816 Ty = StTy->getElementTypes()[idxValue];
1817 } else if (const SequentialType *SqTy = cast<SequentialType>(Ty)) {
1818 // It's an array or pointer access: [ArraySize x ElementType].
1820 // idx is the index into the array. Unlike with structure
1821 // indices, we may not know its actual value at code-generation
1823 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
1825 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
1826 // must find the size of the pointed-to type (Not coincidentally, the next
1827 // type is the type of the elements in the array).
1828 Ty = SqTy->getElementType();
1829 unsigned elementSize = TD.getTypeSize(Ty);
1831 // If idxReg is a constant, we don't need to perform the multiply!
1832 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
1833 if (!CSI->isNullValue()) {
1834 unsigned Offset = elementSize*CSI->getValue();
1835 NextReg = makeAnotherReg(Type::UIntTy);
1836 BMI(MBB, IP, X86::ADDri32, 2,NextReg).addReg(BaseReg).addZImm(Offset);
1838 } else if (elementSize == 1) {
1839 // If the element size is 1, we don't have to multiply, just add
1840 unsigned idxReg = getReg(idx, MBB, IP);
1841 NextReg = makeAnotherReg(Type::UIntTy);
1842 BMI(MBB, IP, X86::ADDrr32, 2, NextReg).addReg(BaseReg).addReg(idxReg);
1844 unsigned idxReg = getReg(idx, MBB, IP);
1845 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
1846 if (unsigned Shift = ExactLog2(elementSize)) {
1847 // If the element size is exactly a power of 2, use a shift to get it.
1848 BMI(MBB, IP, X86::SHLir32, 2,
1849 OffsetReg).addReg(idxReg).addZImm(Shift-1);
1851 // Most general case, emit a multiply...
1852 unsigned elementSizeReg = makeAnotherReg(Type::LongTy);
1853 BMI(MBB, IP, X86::MOVir32, 1, elementSizeReg).addZImm(elementSize);
1855 // Emit a MUL to multiply the register holding the index by
1856 // elementSize, putting the result in OffsetReg.
1857 doMultiply(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSizeReg);
1859 // Emit an ADD to add OffsetReg to the basePtr.
1860 NextReg = makeAnotherReg(Type::UIntTy);
1861 BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg);
1864 // Now that we are here, further indices refer to subtypes of this
1865 // one, so we don't need to worry about BaseReg itself, anymore.
1868 // After we have processed all the indices, the result is left in
1869 // BaseReg. Move it to the register where we were expected to
1870 // put the answer. A 32-bit move should do it, because we are in
1872 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
1876 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
1877 /// frame manager, otherwise do it the hard way.
1879 void ISel::visitAllocaInst(AllocaInst &I) {
1880 // Find the data size of the alloca inst's getAllocatedType.
1881 const Type *Ty = I.getAllocatedType();
1882 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
1884 // If this is a fixed size alloca in the entry block for the function,
1885 // statically stack allocate the space.
1887 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
1888 if (I.getParent() == I.getParent()->getParent()->begin()) {
1889 TySize *= CUI->getValue(); // Get total allocated size...
1890 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
1892 // Create a new stack object using the frame manager...
1893 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
1894 addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx);
1899 // Create a register to hold the temporary result of multiplying the type size
1900 // constant by the variable amount.
1901 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
1902 unsigned SrcReg1 = getReg(I.getArraySize());
1903 unsigned SizeReg = makeAnotherReg(Type::UIntTy);
1904 BuildMI(BB, X86::MOVir32, 1, SizeReg).addZImm(TySize);
1906 // TotalSizeReg = mul <numelements>, <TypeSize>
1907 MachineBasicBlock::iterator MBBI = BB->end();
1908 doMultiply(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, SizeReg);
1910 // AddedSize = add <TotalSizeReg>, 15
1911 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
1912 BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15);
1914 // AlignedSize = and <AddedSize>, ~15
1915 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
1916 BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15);
1918 // Subtract size from stack pointer, thereby allocating some space.
1919 BuildMI(BB, X86::SUBrr32, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
1921 // Put a pointer to the space into the result register, by copying
1922 // the stack pointer.
1923 BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP);
1925 // Inform the Frame Information that we have just allocated a variable-sized
1927 F->getFrameInfo()->CreateVariableSizedObject();
1930 /// visitMallocInst - Malloc instructions are code generated into direct calls
1931 /// to the library malloc.
1933 void ISel::visitMallocInst(MallocInst &I) {
1934 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
1937 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
1938 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
1940 Arg = makeAnotherReg(Type::UIntTy);
1941 unsigned Op0Reg = getReg(ConstantUInt::get(Type::UIntTy, AllocSize));
1942 unsigned Op1Reg = getReg(I.getOperand(0));
1943 MachineBasicBlock::iterator MBBI = BB->end();
1944 doMultiply(BB, MBBI, Arg, Type::UIntTy, Op0Reg, Op1Reg);
1949 std::vector<ValueRecord> Args;
1950 Args.push_back(ValueRecord(Arg, Type::UIntTy));
1951 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
1952 1).addExternalSymbol("malloc", true);
1953 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
1957 /// visitFreeInst - Free instructions are code gen'd to call the free libc
1960 void ISel::visitFreeInst(FreeInst &I) {
1961 std::vector<ValueRecord> Args;
1962 Args.push_back(ValueRecord(getReg(I.getOperand(0)),
1963 I.getOperand(0)->getType()));
1964 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
1965 1).addExternalSymbol("free", true);
1966 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
1970 /// createSimpleX86InstructionSelector - This pass converts an LLVM function
1971 /// into a machine code representation is a very simple peep-hole fashion. The
1972 /// generated code sucks but the implementation is nice and simple.
1974 Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {
1975 return new ISel(TM);