1 //===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the x86 target
12 //===----------------------------------------------------------------------===//
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Function.h"
20 #include "llvm/Instructions.h"
21 #include "llvm/IntrinsicLowering.h"
22 #include "llvm/Pass.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/GetElementPtrTypeIterator.h"
31 #include "llvm/Support/InstVisitor.h"
32 #include "llvm/Support/CFG.h"
33 #include "Support/Statistic.h"
38 NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
41 /// BMI - A special BuildMI variant that takes an iterator to insert the
42 /// instruction at as well as a basic block. This is the version for when you
43 /// have a destination register in mind.
44 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
45 MachineBasicBlock::iterator I,
46 int Opcode, unsigned NumOperands,
48 MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
50 return MachineInstrBuilder(MI).addReg(DestReg, MachineOperand::Def);
53 /// BMI - A special BuildMI variant that takes an iterator to insert the
54 /// instruction at as well as a basic block.
55 inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
56 MachineBasicBlock::iterator I,
57 int Opcode, unsigned NumOperands) {
58 MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
60 return MachineInstrBuilder(MI);
65 struct ISel : public FunctionPass, InstVisitor<ISel> {
67 MachineFunction *F; // The function we are compiling into
68 MachineBasicBlock *BB; // The current MBB we are compiling
69 int VarArgsFrameIndex; // FrameIndex for start of varargs area
70 int ReturnAddressIndex; // FrameIndex for the return address
72 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
74 // MBBMap - Mapping between LLVM BB -> Machine BB
75 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
77 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
79 /// runOnFunction - Top level implementation of instruction selection for
80 /// the entire function.
82 bool runOnFunction(Function &Fn) {
83 // First pass over the function, lower any unknown intrinsic functions
84 // with the IntrinsicLowering class.
85 LowerUnknownIntrinsicFunctionCalls(Fn);
87 F = &MachineFunction::construct(&Fn, TM);
89 // Create all of the machine basic blocks for the function...
90 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
91 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
95 // Set up a frame object for the return address. This is used by the
96 // llvm.returnaddress & llvm.frameaddress intrinisics.
97 ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
99 // Copy incoming arguments off of the stack...
100 LoadArgumentsToVirtualRegs(Fn);
102 // Instruction select everything except PHI nodes
105 // Select the PHI nodes
108 // Insert the FP_REG_KILL instructions into blocks that need them.
114 // We always build a machine code representation for the function
118 virtual const char *getPassName() const {
119 return "X86 Simple Instruction Selection";
122 /// visitBasicBlock - This method is called when we are visiting a new basic
123 /// block. This simply creates a new MachineBasicBlock to emit code into
124 /// and adds it to the current MachineFunction. Subsequent visit* for
125 /// instructions will be invoked for all instructions in the basic block.
127 void visitBasicBlock(BasicBlock &LLVM_BB) {
128 BB = MBBMap[&LLVM_BB];
131 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
132 /// function, lowering any calls to unknown intrinsic functions into the
133 /// equivalent LLVM code.
134 void LowerUnknownIntrinsicFunctionCalls(Function &F);
136 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
137 /// from the stack into virtual registers.
139 void LoadArgumentsToVirtualRegs(Function &F);
141 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
142 /// because we have to generate our sources into the source basic blocks,
143 /// not the current one.
145 void SelectPHINodes();
147 /// InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks
148 /// that need them. This only occurs due to the floating point stackifier
149 /// not being aggressive enough to handle arbitrary global stackification.
151 void InsertFPRegKills();
153 // Visitation methods for various instructions. These methods simply emit
154 // fixed X86 code for each instruction.
157 // Control flow operators
158 void visitReturnInst(ReturnInst &RI);
159 void visitBranchInst(BranchInst &BI);
165 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
166 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
168 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
169 const std::vector<ValueRecord> &Args);
170 void visitCallInst(CallInst &I);
171 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
173 // Arithmetic operators
174 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
175 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
176 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
177 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
178 unsigned DestReg, const Type *DestTy,
179 unsigned Op0Reg, unsigned Op1Reg);
180 void doMultiplyConst(MachineBasicBlock *MBB,
181 MachineBasicBlock::iterator MBBI,
182 unsigned DestReg, const Type *DestTy,
183 unsigned Op0Reg, unsigned Op1Val);
184 void visitMul(BinaryOperator &B);
186 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
187 void visitRem(BinaryOperator &B) { visitDivRem(B); }
188 void visitDivRem(BinaryOperator &B);
191 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
192 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
193 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
195 // Comparison operators...
196 void visitSetCondInst(SetCondInst &I);
197 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
198 MachineBasicBlock *MBB,
199 MachineBasicBlock::iterator MBBI);
201 // Memory Instructions
202 void visitLoadInst(LoadInst &I);
203 void visitStoreInst(StoreInst &I);
204 void visitGetElementPtrInst(GetElementPtrInst &I);
205 void visitAllocaInst(AllocaInst &I);
206 void visitMallocInst(MallocInst &I);
207 void visitFreeInst(FreeInst &I);
210 void visitShiftInst(ShiftInst &I);
211 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
212 void visitCastInst(CastInst &I);
213 void visitVANextInst(VANextInst &I);
214 void visitVAArgInst(VAArgInst &I);
216 void visitInstruction(Instruction &I) {
217 std::cerr << "Cannot instruction select: " << I;
221 /// promote32 - Make a value 32-bits wide, and put it somewhere.
223 void promote32(unsigned targetReg, const ValueRecord &VR);
225 // getGEPIndex - This is used to fold GEP instructions into X86 addressing
227 void getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
228 std::vector<Value*> &GEPOps,
229 std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
230 unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
232 /// isGEPFoldable - Return true if the specified GEP can be completely
233 /// folded into the addressing mode of a load/store or lea instruction.
234 bool isGEPFoldable(MachineBasicBlock *MBB,
235 Value *Src, User::op_iterator IdxBegin,
236 User::op_iterator IdxEnd, unsigned &BaseReg,
237 unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
239 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
240 /// constant expression GEP support.
242 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
243 Value *Src, User::op_iterator IdxBegin,
244 User::op_iterator IdxEnd, unsigned TargetReg);
246 /// emitCastOperation - Common code shared between visitCastInst and
247 /// constant expression cast support.
248 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
249 Value *Src, const Type *DestTy, unsigned TargetReg);
251 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
252 /// and constant expression support.
253 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
254 MachineBasicBlock::iterator IP,
255 Value *Op0, Value *Op1,
256 unsigned OperatorClass, unsigned TargetReg);
258 void emitDivRemOperation(MachineBasicBlock *BB,
259 MachineBasicBlock::iterator IP,
260 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
261 const Type *Ty, unsigned TargetReg);
263 /// emitSetCCOperation - Common code shared between visitSetCondInst and
264 /// constant expression support.
265 void emitSetCCOperation(MachineBasicBlock *BB,
266 MachineBasicBlock::iterator IP,
267 Value *Op0, Value *Op1, unsigned Opcode,
270 /// emitShiftOperation - Common code shared between visitShiftInst and
271 /// constant expression support.
272 void emitShiftOperation(MachineBasicBlock *MBB,
273 MachineBasicBlock::iterator IP,
274 Value *Op, Value *ShiftAmount, bool isLeftShift,
275 const Type *ResultTy, unsigned DestReg);
278 /// copyConstantToRegister - Output the instructions required to put the
279 /// specified constant into the specified register.
281 void copyConstantToRegister(MachineBasicBlock *MBB,
282 MachineBasicBlock::iterator MBBI,
283 Constant *C, unsigned Reg);
285 /// makeAnotherReg - This method returns the next register number we haven't
288 /// Long values are handled somewhat specially. They are always allocated
289 /// as pairs of 32 bit integer values. The register number returned is the
290 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
291 /// of the long value.
293 unsigned makeAnotherReg(const Type *Ty) {
294 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
295 "Current target doesn't have X86 reg info??");
296 const X86RegisterInfo *MRI =
297 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
298 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
299 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
300 // Create the lower part
301 F->getSSARegMap()->createVirtualRegister(RC);
302 // Create the upper part.
303 return F->getSSARegMap()->createVirtualRegister(RC)-1;
306 // Add the mapping of regnumber => reg class to MachineFunction
307 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
308 return F->getSSARegMap()->createVirtualRegister(RC);
311 /// getReg - This method turns an LLVM value into a register number. This
312 /// is guaranteed to produce the same register number for a particular value
313 /// every time it is queried.
315 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
316 unsigned getReg(Value *V) {
317 // Just append to the end of the current bb.
318 MachineBasicBlock::iterator It = BB->end();
319 return getReg(V, BB, It);
321 unsigned getReg(Value *V, MachineBasicBlock *MBB,
322 MachineBasicBlock::iterator IPt) {
323 unsigned &Reg = RegMap[V];
325 Reg = makeAnotherReg(V->getType());
329 // If this operand is a constant, emit the code to copy the constant into
330 // the register here...
332 if (Constant *C = dyn_cast<Constant>(V)) {
333 copyConstantToRegister(MBB, IPt, C, Reg);
334 RegMap.erase(V); // Assign a new name to this constant if ref'd again
335 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
336 // Move the address of the global into the register
337 BMI(MBB, IPt, X86::MOVri32, 1, Reg).addGlobalAddress(GV);
338 RegMap.erase(V); // Assign a new name to this address if ref'd again
346 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
350 cByte, cShort, cInt, cFP, cLong
353 /// getClass - Turn a primitive type into a "class" number which is based on the
354 /// size of the type, and whether or not it is floating point.
356 static inline TypeClass getClass(const Type *Ty) {
357 switch (Ty->getPrimitiveID()) {
358 case Type::SByteTyID:
359 case Type::UByteTyID: return cByte; // Byte operands are class #0
360 case Type::ShortTyID:
361 case Type::UShortTyID: return cShort; // Short operands are class #1
364 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
366 case Type::FloatTyID:
367 case Type::DoubleTyID: return cFP; // Floating Point is #3
370 case Type::ULongTyID: return cLong; // Longs are class #4
372 assert(0 && "Invalid type to getClass!");
373 return cByte; // not reached
377 // getClassB - Just like getClass, but treat boolean values as bytes.
378 static inline TypeClass getClassB(const Type *Ty) {
379 if (Ty == Type::BoolTy) return cByte;
384 /// copyConstantToRegister - Output the instructions required to put the
385 /// specified constant into the specified register.
387 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
388 MachineBasicBlock::iterator IP,
389 Constant *C, unsigned R) {
390 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
392 switch (CE->getOpcode()) {
393 case Instruction::GetElementPtr:
394 emitGEPOperation(MBB, IP, CE->getOperand(0),
395 CE->op_begin()+1, CE->op_end(), R);
397 case Instruction::Cast:
398 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
401 case Instruction::Xor: ++Class; // FALL THROUGH
402 case Instruction::Or: ++Class; // FALL THROUGH
403 case Instruction::And: ++Class; // FALL THROUGH
404 case Instruction::Sub: ++Class; // FALL THROUGH
405 case Instruction::Add:
406 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
410 case Instruction::Mul: {
411 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
412 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
413 doMultiply(MBB, IP, R, CE->getType(), Op0Reg, Op1Reg);
416 case Instruction::Div:
417 case Instruction::Rem: {
418 unsigned Op0Reg = getReg(CE->getOperand(0), MBB, IP);
419 unsigned Op1Reg = getReg(CE->getOperand(1), MBB, IP);
420 emitDivRemOperation(MBB, IP, Op0Reg, Op1Reg,
421 CE->getOpcode() == Instruction::Div,
426 case Instruction::SetNE:
427 case Instruction::SetEQ:
428 case Instruction::SetLT:
429 case Instruction::SetGT:
430 case Instruction::SetLE:
431 case Instruction::SetGE:
432 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
436 case Instruction::Shl:
437 case Instruction::Shr:
438 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
439 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
443 std::cerr << "Offending expr: " << C << "\n";
444 assert(0 && "Constant expression not yet handled!\n");
448 if (C->getType()->isIntegral()) {
449 unsigned Class = getClassB(C->getType());
451 if (Class == cLong) {
452 // Copy the value into the register pair.
453 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
454 BMI(MBB, IP, X86::MOVri32, 1, R).addZImm(Val & 0xFFFFFFFF);
455 BMI(MBB, IP, X86::MOVri32, 1, R+1).addZImm(Val >> 32);
459 assert(Class <= cInt && "Type not handled yet!");
461 static const unsigned IntegralOpcodeTab[] = {
462 X86::MOVri8, X86::MOVri16, X86::MOVri32
465 if (C->getType() == Type::BoolTy) {
466 BMI(MBB, IP, X86::MOVri8, 1, R).addZImm(C == ConstantBool::True);
468 ConstantInt *CI = cast<ConstantInt>(C);
469 BMI(MBB, IP, IntegralOpcodeTab[Class], 1, R).addZImm(CI->getRawValue());
471 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
472 if (CFP->isExactlyValue(+0.0))
473 BMI(MBB, IP, X86::FLD0, 0, R);
474 else if (CFP->isExactlyValue(+1.0))
475 BMI(MBB, IP, X86::FLD1, 0, R);
477 // Otherwise we need to spill the constant to memory...
478 MachineConstantPool *CP = F->getConstantPool();
479 unsigned CPI = CP->getConstantPoolIndex(CFP);
480 const Type *Ty = CFP->getType();
482 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
483 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64;
484 addConstantPoolReference(BMI(MBB, IP, LoadOpcode, 4, R), CPI);
487 } else if (isa<ConstantPointerNull>(C)) {
488 // Copy zero (null pointer) to the register.
489 BMI(MBB, IP, X86::MOVri32, 1, R).addZImm(0);
490 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
491 BMI(MBB, IP, X86::MOVri32, 1, R).addGlobalAddress(CPR->getValue());
493 std::cerr << "Offending constant: " << C << "\n";
494 assert(0 && "Type not handled yet!");
498 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
499 /// the stack into virtual registers.
501 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
502 // Emit instructions to load the arguments... On entry to a function on the
503 // X86, the stack frame looks like this:
505 // [ESP] -- return address
506 // [ESP + 4] -- first argument (leftmost lexically)
507 // [ESP + 8] -- second argument, if first argument is four bytes in size
510 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
511 MachineFrameInfo *MFI = F->getFrameInfo();
513 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
514 unsigned Reg = getReg(*I);
516 int FI; // Frame object index
517 switch (getClassB(I->getType())) {
519 FI = MFI->CreateFixedObject(1, ArgOffset);
520 addFrameReference(BuildMI(BB, X86::MOVrm8, 4, Reg), FI);
523 FI = MFI->CreateFixedObject(2, ArgOffset);
524 addFrameReference(BuildMI(BB, X86::MOVrm16, 4, Reg), FI);
527 FI = MFI->CreateFixedObject(4, ArgOffset);
528 addFrameReference(BuildMI(BB, X86::MOVrm32, 4, Reg), FI);
531 FI = MFI->CreateFixedObject(8, ArgOffset);
532 addFrameReference(BuildMI(BB, X86::MOVrm32, 4, Reg), FI);
533 addFrameReference(BuildMI(BB, X86::MOVrm32, 4, Reg+1), FI, 4);
534 ArgOffset += 4; // longs require 4 additional bytes
538 if (I->getType() == Type::FloatTy) {
539 Opcode = X86::FLDr32;
540 FI = MFI->CreateFixedObject(4, ArgOffset);
542 Opcode = X86::FLDr64;
543 FI = MFI->CreateFixedObject(8, ArgOffset);
544 ArgOffset += 4; // doubles require 4 additional bytes
546 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
549 assert(0 && "Unhandled argument type!");
551 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
554 // If the function takes variable number of arguments, add a frame offset for
555 // the start of the first vararg value... this is used to expand
557 if (Fn.getFunctionType()->isVarArg())
558 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
562 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
563 /// because we have to generate our sources into the source basic blocks, not
566 void ISel::SelectPHINodes() {
567 const TargetInstrInfo &TII = TM.getInstrInfo();
568 const Function &LF = *F->getFunction(); // The LLVM function...
569 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
570 const BasicBlock *BB = I;
571 MachineBasicBlock *MBB = MBBMap[I];
573 // Loop over all of the PHI nodes in the LLVM basic block...
574 MachineBasicBlock::iterator instr = MBB->begin();
575 for (BasicBlock::const_iterator I = BB->begin();
576 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
578 // Create a new machine instr PHI node, and insert it.
579 unsigned PHIReg = getReg(*PN);
580 MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
581 MBB->insert(instr, PhiMI);
583 MachineInstr *LongPhiMI = 0;
584 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
585 LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
586 MBB->insert(instr, LongPhiMI);
589 // PHIValues - Map of blocks to incoming virtual registers. We use this
590 // so that we only initialize one incoming value for a particular block,
591 // even if the block has multiple entries in the PHI node.
593 std::map<MachineBasicBlock*, unsigned> PHIValues;
595 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
596 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
598 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
599 PHIValues.lower_bound(PredMBB);
601 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
602 // We already inserted an initialization of the register for this
603 // predecessor. Recycle it.
604 ValReg = EntryIt->second;
607 // Get the incoming value into a virtual register.
609 Value *Val = PN->getIncomingValue(i);
611 // If this is a constant or GlobalValue, we may have to insert code
612 // into the basic block to compute it into a virtual register.
613 if (isa<Constant>(Val) || isa<GlobalValue>(Val)) {
614 // Because we don't want to clobber any values which might be in
615 // physical registers with the computation of this constant (which
616 // might be arbitrarily complex if it is a constant expression),
617 // just insert the computation at the top of the basic block.
618 MachineBasicBlock::iterator PI = PredMBB->begin();
620 // Skip over any PHI nodes though!
621 while (PI != PredMBB->end() && PI->getOpcode() == X86::PHI)
624 ValReg = getReg(Val, PredMBB, PI);
626 ValReg = getReg(Val);
629 // Remember that we inserted a value for this PHI for this predecessor
630 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
633 PhiMI->addRegOperand(ValReg);
634 PhiMI->addMachineBasicBlockOperand(PredMBB);
636 LongPhiMI->addRegOperand(ValReg+1);
637 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
644 /// RequiresFPRegKill - The floating point stackifier pass cannot insert
645 /// compensation code on critical edges. As such, it requires that we kill all
646 /// FP registers on the exit from any blocks that either ARE critical edges, or
647 /// branch to a block that has incoming critical edges.
649 /// Note that this kill instruction will eventually be eliminated when
650 /// restrictions in the stackifier are relaxed.
652 static bool RequiresFPRegKill(const BasicBlock *BB) {
654 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB); SI!=E; ++SI) {
655 const BasicBlock *Succ = *SI;
656 pred_const_iterator PI = pred_begin(Succ), PE = pred_end(Succ);
657 ++PI; // Block have at least one predecessory
658 if (PI != PE) { // If it has exactly one, this isn't crit edge
659 // If this block has more than one predecessor, check all of the
660 // predecessors to see if they have multiple successors. If so, then the
661 // block we are analyzing needs an FPRegKill.
662 for (PI = pred_begin(Succ); PI != PE; ++PI) {
663 const BasicBlock *Pred = *PI;
664 succ_const_iterator SI2 = succ_begin(Pred);
665 ++SI2; // There must be at least one successor of this block.
666 if (SI2 != succ_end(Pred))
667 return true; // Yes, we must insert the kill on this edge.
671 // If we got this far, there is no need to insert the kill instruction.
678 // InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks that
679 // need them. This only occurs due to the floating point stackifier not being
680 // aggressive enough to handle arbitrary global stackification.
682 // Currently we insert an FP_REG_KILL instruction into each block that uses or
683 // defines a floating point virtual register.
685 // When the global register allocators (like linear scan) finally update live
686 // variable analysis, we can keep floating point values in registers across
687 // portions of the CFG that do not involve critical edges. This will be a big
688 // win, but we are waiting on the global allocators before we can do this.
690 // With a bit of work, the floating point stackifier pass can be enhanced to
691 // break critical edges as needed (to make a place to put compensation code),
692 // but this will require some infrastructure improvements as well.
694 void ISel::InsertFPRegKills() {
695 SSARegMap &RegMap = *F->getSSARegMap();
697 for (MachineFunction::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
698 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I!=E; ++I)
699 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
700 if (I->getOperand(i).isRegister()) {
701 unsigned Reg = I->getOperand(i).getReg();
702 if (MRegisterInfo::isVirtualRegister(Reg))
703 if (RegMap.getRegClass(Reg)->getSize() == 10)
707 // If we haven't found an FP register use or def in this basic block, check
708 // to see if any of our successors has an FP PHI node, which will cause a
709 // copy to be inserted into this block.
710 for (succ_const_iterator SI = succ_begin(BB->getBasicBlock()),
711 E = succ_end(BB->getBasicBlock()); SI != E; ++SI) {
712 MachineBasicBlock *SBB = MBBMap[*SI];
713 for (MachineBasicBlock::iterator I = SBB->begin();
714 I != SBB->end() && I->getOpcode() == X86::PHI; ++I) {
715 if (RegMap.getRegClass(I->getOperand(0).getReg())->getSize() == 10)
721 // Okay, this block uses an FP register. If the block has successors (ie,
722 // it's not an unwind/return), insert the FP_REG_KILL instruction.
723 if (BB->getBasicBlock()->getTerminator()->getNumSuccessors() &&
724 RequiresFPRegKill(BB->getBasicBlock())) {
725 BMI(BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
732 // canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it into
733 // the conditional branch instruction which is the only user of the cc
734 // instruction. This is the case if the conditional branch is the only user of
735 // the setcc, and if the setcc is in the same basic block as the conditional
736 // branch. We also don't handle long arguments below, so we reject them here as
739 static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
740 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
741 if (SCI->hasOneUse() && isa<BranchInst>(SCI->use_back()) &&
742 SCI->getParent() == cast<BranchInst>(SCI->use_back())->getParent()) {
743 const Type *Ty = SCI->getOperand(0)->getType();
744 if (Ty != Type::LongTy && Ty != Type::ULongTy)
750 // Return a fixed numbering for setcc instructions which does not depend on the
751 // order of the opcodes.
753 static unsigned getSetCCNumber(unsigned Opcode) {
755 default: assert(0 && "Unknown setcc instruction!");
756 case Instruction::SetEQ: return 0;
757 case Instruction::SetNE: return 1;
758 case Instruction::SetLT: return 2;
759 case Instruction::SetGE: return 3;
760 case Instruction::SetGT: return 4;
761 case Instruction::SetLE: return 5;
765 // LLVM -> X86 signed X86 unsigned
766 // ----- ---------- ------------
767 // seteq -> sete sete
768 // setne -> setne setne
769 // setlt -> setl setb
770 // setge -> setge setae
771 // setgt -> setg seta
772 // setle -> setle setbe
774 // sets // Used by comparison with 0 optimization
776 static const unsigned SetCCOpcodeTab[2][8] = {
777 { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
779 { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
780 X86::SETSr, X86::SETNSr },
783 // EmitComparison - This function emits a comparison of the two operands,
784 // returning the extended setcc code to use.
785 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
786 MachineBasicBlock *MBB,
787 MachineBasicBlock::iterator IP) {
788 // The arguments are already supposed to be of the same type.
789 const Type *CompTy = Op0->getType();
790 unsigned Class = getClassB(CompTy);
791 unsigned Op0r = getReg(Op0, MBB, IP);
793 // Special case handling of: cmp R, i
794 if (Class == cByte || Class == cShort || Class == cInt)
795 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
796 uint64_t Op1v = cast<ConstantInt>(CI)->getRawValue();
798 // Mask off any upper bits of the constant, if there are any...
799 Op1v &= (1ULL << (8 << Class)) - 1;
801 // If this is a comparison against zero, emit more efficient code. We
802 // can't handle unsigned comparisons against zero unless they are == or
803 // !=. These should have been strength reduced already anyway.
804 if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
805 static const unsigned TESTTab[] = {
806 X86::TESTrr8, X86::TESTrr16, X86::TESTrr32
808 BMI(MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
810 if (OpNum == 2) return 6; // Map jl -> js
811 if (OpNum == 3) return 7; // Map jg -> jns
815 static const unsigned CMPTab[] = {
816 X86::CMPri8, X86::CMPri16, X86::CMPri32
819 BMI(MBB, IP, CMPTab[Class], 2).addReg(Op0r).addZImm(Op1v);
823 // Special case handling of comparison against +/- 0.0
824 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op1))
825 if (CFP->isExactlyValue(+0.0) || CFP->isExactlyValue(-0.0)) {
826 BMI(MBB, IP, X86::FTST, 1).addReg(Op0r);
827 BMI(MBB, IP, X86::FNSTSWr8, 0);
828 BMI(MBB, IP, X86::SAHF, 1);
832 unsigned Op1r = getReg(Op1, MBB, IP);
834 default: assert(0 && "Unknown type class!");
835 // Emit: cmp <var1>, <var2> (do the comparison). We can
836 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
839 BMI(MBB, IP, X86::CMPrr8, 2).addReg(Op0r).addReg(Op1r);
842 BMI(MBB, IP, X86::CMPrr16, 2).addReg(Op0r).addReg(Op1r);
845 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
848 BMI(MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
849 BMI(MBB, IP, X86::FNSTSWr8, 0);
850 BMI(MBB, IP, X86::SAHF, 1);
854 if (OpNum < 2) { // seteq, setne
855 unsigned LoTmp = makeAnotherReg(Type::IntTy);
856 unsigned HiTmp = makeAnotherReg(Type::IntTy);
857 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
858 BMI(MBB, IP, X86::XORrr32, 2, LoTmp).addReg(Op0r).addReg(Op1r);
859 BMI(MBB, IP, X86::XORrr32, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
860 BMI(MBB, IP, X86::ORrr32, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
861 break; // Allow the sete or setne to be generated from flags set by OR
863 // Emit a sequence of code which compares the high and low parts once
864 // each, then uses a conditional move to handle the overflow case. For
865 // example, a setlt for long would generate code like this:
867 // AL = lo(op1) < lo(op2) // Signedness depends on operands
868 // BL = hi(op1) < hi(op2) // Always unsigned comparison
869 // dest = hi(op1) == hi(op2) ? AL : BL;
872 // FIXME: This would be much better if we had hierarchical register
873 // classes! Until then, hardcode registers so that we can deal with their
874 // aliases (because we don't have conditional byte moves).
876 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
877 BMI(MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
878 BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
879 BMI(MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
880 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
881 BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
882 BMI(MBB, IP, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
883 // NOTE: visitSetCondInst knows that the value is dumped into the BL
884 // register at this point for long values...
892 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
893 /// register, then move it to wherever the result should be.
895 void ISel::visitSetCondInst(SetCondInst &I) {
896 if (canFoldSetCCIntoBranch(&I)) return; // Fold this into a branch...
898 unsigned DestReg = getReg(I);
899 MachineBasicBlock::iterator MII = BB->end();
900 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
904 /// emitSetCCOperation - Common code shared between visitSetCondInst and
905 /// constant expression support.
906 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
907 MachineBasicBlock::iterator IP,
908 Value *Op0, Value *Op1, unsigned Opcode,
909 unsigned TargetReg) {
910 unsigned OpNum = getSetCCNumber(Opcode);
911 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
913 const Type *CompTy = Op0->getType();
914 unsigned CompClass = getClassB(CompTy);
915 bool isSigned = CompTy->isSigned() && CompClass != cFP;
917 if (CompClass != cLong || OpNum < 2) {
918 // Handle normal comparisons with a setcc instruction...
919 BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
921 // Handle long comparisons by copying the value which is already in BL into
922 // the register we want...
923 BMI(MBB, IP, X86::MOVrr8, 1, TargetReg).addReg(X86::BL);
930 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
931 /// operand, in the specified target register.
932 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
933 bool isUnsigned = VR.Ty->isUnsigned();
935 // Make sure we have the register number for this value...
936 unsigned Reg = VR.Val ? getReg(VR.Val) : VR.Reg;
938 switch (getClassB(VR.Ty)) {
940 // Extend value into target register (8->32)
942 BuildMI(BB, X86::MOVZXr32r8, 1, targetReg).addReg(Reg);
944 BuildMI(BB, X86::MOVSXr32r8, 1, targetReg).addReg(Reg);
947 // Extend value into target register (16->32)
949 BuildMI(BB, X86::MOVZXr32r16, 1, targetReg).addReg(Reg);
951 BuildMI(BB, X86::MOVSXr32r16, 1, targetReg).addReg(Reg);
954 // Move value into target register (32->32)
955 BuildMI(BB, X86::MOVrr32, 1, targetReg).addReg(Reg);
958 assert(0 && "Unpromotable operand class in promote32");
962 /// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
963 /// we have the following possibilities:
965 /// ret void: No return value, simply emit a 'ret' instruction
966 /// ret sbyte, ubyte : Extend value into EAX and return
967 /// ret short, ushort: Extend value into EAX and return
968 /// ret int, uint : Move value into EAX and return
969 /// ret pointer : Move value into EAX and return
970 /// ret long, ulong : Move value into EAX/EDX and return
971 /// ret float/double : Top of FP stack
973 void ISel::visitReturnInst(ReturnInst &I) {
974 if (I.getNumOperands() == 0) {
975 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
979 Value *RetVal = I.getOperand(0);
980 unsigned RetReg = getReg(RetVal);
981 switch (getClassB(RetVal->getType())) {
982 case cByte: // integral return values: extend or move into EAX and return
985 promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
986 // Declare that EAX is live on exit
987 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
989 case cFP: // Floats & Doubles: Return in ST(0)
990 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
991 // Declare that top-of-stack is live on exit
992 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
995 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(RetReg);
996 BuildMI(BB, X86::MOVrr32, 1, X86::EDX).addReg(RetReg+1);
997 // Declare that EAX & EDX are live on exit
998 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
1002 visitInstruction(I);
1004 // Emit a 'ret' instruction
1005 BuildMI(BB, X86::RET, 0);
1008 // getBlockAfter - Return the basic block which occurs lexically after the
1010 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1011 Function::iterator I = BB; ++I; // Get iterator to next block
1012 return I != BB->getParent()->end() ? &*I : 0;
1015 /// visitBranchInst - Handle conditional and unconditional branches here. Note
1016 /// that since code layout is frozen at this point, that if we are trying to
1017 /// jump to a block that is the immediate successor of the current block, we can
1018 /// just make a fall-through (but we don't currently).
1020 void ISel::visitBranchInst(BranchInst &BI) {
1021 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1023 if (!BI.isConditional()) { // Unconditional branch?
1024 if (BI.getSuccessor(0) != NextBB)
1025 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
1029 // See if we can fold the setcc into the branch itself...
1030 SetCondInst *SCI = canFoldSetCCIntoBranch(BI.getCondition());
1032 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1033 // computed some other way...
1034 unsigned condReg = getReg(BI.getCondition());
1035 BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
1036 if (BI.getSuccessor(1) == NextBB) {
1037 if (BI.getSuccessor(0) != NextBB)
1038 BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
1040 BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
1042 if (BI.getSuccessor(0) != NextBB)
1043 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
1048 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1049 MachineBasicBlock::iterator MII = BB->end();
1050 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1052 const Type *CompTy = SCI->getOperand(0)->getType();
1053 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
1056 // LLVM -> X86 signed X86 unsigned
1057 // ----- ---------- ------------
1065 // js // Used by comparison with 0 optimization
1068 static const unsigned OpcodeTab[2][8] = {
1069 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
1070 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
1071 X86::JS, X86::JNS },
1074 if (BI.getSuccessor(0) != NextBB) {
1075 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
1076 if (BI.getSuccessor(1) != NextBB)
1077 BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
1079 // Change to the inverse condition...
1080 if (BI.getSuccessor(1) != NextBB) {
1082 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
1088 /// doCall - This emits an abstract call instruction, setting up the arguments
1089 /// and the return value as appropriate. For the actual function call itself,
1090 /// it inserts the specified CallMI instruction into the stream.
1092 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1093 const std::vector<ValueRecord> &Args) {
1095 // Count how many bytes are to be pushed on the stack...
1096 unsigned NumBytes = 0;
1098 if (!Args.empty()) {
1099 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1100 switch (getClassB(Args[i].Ty)) {
1101 case cByte: case cShort: case cInt:
1102 NumBytes += 4; break;
1104 NumBytes += 8; break;
1106 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
1108 default: assert(0 && "Unknown class!");
1111 // Adjust the stack pointer for the new arguments...
1112 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(NumBytes);
1114 // Arguments go on the stack in reverse order, as specified by the ABI.
1115 unsigned ArgOffset = 0;
1116 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1117 unsigned ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1118 switch (getClassB(Args[i].Ty)) {
1121 // Promote arg to 32 bits wide into a temporary register...
1122 unsigned R = makeAnotherReg(Type::UIntTy);
1123 promote32(R, Args[i]);
1124 addRegOffset(BuildMI(BB, X86::MOVmr32, 5),
1125 X86::ESP, ArgOffset).addReg(R);
1129 addRegOffset(BuildMI(BB, X86::MOVmr32, 5),
1130 X86::ESP, ArgOffset).addReg(ArgReg);
1133 addRegOffset(BuildMI(BB, X86::MOVmr32, 5),
1134 X86::ESP, ArgOffset).addReg(ArgReg);
1135 addRegOffset(BuildMI(BB, X86::MOVmr32, 5),
1136 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
1137 ArgOffset += 4; // 8 byte entry, not 4.
1141 if (Args[i].Ty == Type::FloatTy) {
1142 addRegOffset(BuildMI(BB, X86::FSTr32, 5),
1143 X86::ESP, ArgOffset).addReg(ArgReg);
1145 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
1146 addRegOffset(BuildMI(BB, X86::FSTr64, 5),
1147 X86::ESP, ArgOffset).addReg(ArgReg);
1148 ArgOffset += 4; // 8 byte entry, not 4.
1152 default: assert(0 && "Unknown class!");
1157 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addZImm(0);
1160 BB->push_back(CallMI);
1162 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addZImm(NumBytes);
1164 // If there is a return value, scavenge the result from the location the call
1167 if (Ret.Ty != Type::VoidTy) {
1168 unsigned DestClass = getClassB(Ret.Ty);
1169 switch (DestClass) {
1173 // Integral results are in %eax, or the appropriate portion
1175 static const unsigned regRegMove[] = {
1176 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32
1178 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
1179 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
1182 case cFP: // Floating-point return values live in %ST(0)
1183 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
1185 case cLong: // Long values are left in EDX:EAX
1186 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg).addReg(X86::EAX);
1187 BuildMI(BB, X86::MOVrr32, 1, Ret.Reg+1).addReg(X86::EDX);
1189 default: assert(0 && "Unknown class!");
1195 /// visitCallInst - Push args on stack and do a procedure call instruction.
1196 void ISel::visitCallInst(CallInst &CI) {
1197 MachineInstr *TheCall;
1198 if (Function *F = CI.getCalledFunction()) {
1199 // Is it an intrinsic function call?
1200 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1201 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1205 // Emit a CALL instruction with PC-relative displacement.
1206 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
1207 } else { // Emit an indirect call...
1208 unsigned Reg = getReg(CI.getCalledValue());
1209 TheCall = BuildMI(X86::CALLr32, 1).addReg(Reg);
1212 std::vector<ValueRecord> Args;
1213 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1214 Args.push_back(ValueRecord(CI.getOperand(i)));
1216 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1217 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1221 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1222 /// function, lowering any calls to unknown intrinsic functions into the
1223 /// equivalent LLVM code.
1224 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1225 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1226 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1227 if (CallInst *CI = dyn_cast<CallInst>(I++))
1228 if (Function *F = CI->getCalledFunction())
1229 switch (F->getIntrinsicID()) {
1230 case Intrinsic::not_intrinsic:
1231 case Intrinsic::va_start:
1232 case Intrinsic::va_copy:
1233 case Intrinsic::va_end:
1234 case Intrinsic::returnaddress:
1235 case Intrinsic::frameaddress:
1236 case Intrinsic::memcpy:
1237 case Intrinsic::memset:
1238 // We directly implement these intrinsics
1241 // All other intrinsic calls we must lower.
1242 Instruction *Before = CI->getPrev();
1243 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1244 if (Before) { // Move iterator to instruction after call
1253 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1254 unsigned TmpReg1, TmpReg2;
1256 case Intrinsic::va_start:
1257 // Get the address of the first vararg value...
1258 TmpReg1 = getReg(CI);
1259 addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
1262 case Intrinsic::va_copy:
1263 TmpReg1 = getReg(CI);
1264 TmpReg2 = getReg(CI.getOperand(1));
1265 BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2);
1267 case Intrinsic::va_end: return; // Noop on X86
1269 case Intrinsic::returnaddress:
1270 case Intrinsic::frameaddress:
1271 TmpReg1 = getReg(CI);
1272 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1273 if (ID == Intrinsic::returnaddress) {
1274 // Just load the return address
1275 addFrameReference(BuildMI(BB, X86::MOVrm32, 4, TmpReg1),
1276 ReturnAddressIndex);
1278 addFrameReference(BuildMI(BB, X86::LEAr32, 4, TmpReg1),
1279 ReturnAddressIndex, -4);
1282 // Values other than zero are not implemented yet.
1283 BuildMI(BB, X86::MOVri32, 1, TmpReg1).addZImm(0);
1287 case Intrinsic::memcpy: {
1288 assert(CI.getNumOperands() == 5 && "Illegal llvm.memcpy call!");
1290 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1291 Align = AlignC->getRawValue();
1292 if (Align == 0) Align = 1;
1295 // Turn the byte code into # iterations
1299 switch (Align & 3) {
1300 case 2: // WORD aligned
1301 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1302 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1304 CountReg = makeAnotherReg(Type::IntTy);
1305 BuildMI(BB, X86::SHRri32, 2, CountReg).addReg(ByteReg).addZImm(1);
1307 Opcode = X86::REP_MOVSW;
1309 case 0: // DWORD aligned
1310 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1311 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1313 CountReg = makeAnotherReg(Type::IntTy);
1314 BuildMI(BB, X86::SHRri32, 2, CountReg).addReg(ByteReg).addZImm(2);
1316 Opcode = X86::REP_MOVSD;
1318 case 1: // BYTE aligned
1319 case 3: // BYTE aligned
1320 CountReg = getReg(CI.getOperand(3));
1321 Opcode = X86::REP_MOVSB;
1325 // No matter what the alignment is, we put the source in ESI, the
1326 // destination in EDI, and the count in ECX.
1327 TmpReg1 = getReg(CI.getOperand(1));
1328 TmpReg2 = getReg(CI.getOperand(2));
1329 BuildMI(BB, X86::MOVrr32, 1, X86::ECX).addReg(CountReg);
1330 BuildMI(BB, X86::MOVrr32, 1, X86::EDI).addReg(TmpReg1);
1331 BuildMI(BB, X86::MOVrr32, 1, X86::ESI).addReg(TmpReg2);
1332 BuildMI(BB, Opcode, 0);
1335 case Intrinsic::memset: {
1336 assert(CI.getNumOperands() == 5 && "Illegal llvm.memset call!");
1338 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1339 Align = AlignC->getRawValue();
1340 if (Align == 0) Align = 1;
1343 // Turn the byte code into # iterations
1347 if (ConstantInt *ValC = dyn_cast<ConstantInt>(CI.getOperand(2))) {
1348 unsigned Val = ValC->getRawValue() & 255;
1350 // If the value is a constant, then we can potentially use larger copies.
1351 switch (Align & 3) {
1352 case 2: // WORD aligned
1353 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1354 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1356 CountReg = makeAnotherReg(Type::IntTy);
1357 BuildMI(BB, X86::SHRri32, 2, CountReg).addReg(ByteReg).addZImm(1);
1359 BuildMI(BB, X86::MOVri16, 1, X86::AX).addZImm((Val << 8) | Val);
1360 Opcode = X86::REP_STOSW;
1362 case 0: // DWORD aligned
1363 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1364 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1366 CountReg = makeAnotherReg(Type::IntTy);
1367 BuildMI(BB, X86::SHRri32, 2, CountReg).addReg(ByteReg).addZImm(2);
1369 Val = (Val << 8) | Val;
1370 BuildMI(BB, X86::MOVri32, 1, X86::EAX).addZImm((Val << 16) | Val);
1371 Opcode = X86::REP_STOSD;
1373 case 1: // BYTE aligned
1374 case 3: // BYTE aligned
1375 CountReg = getReg(CI.getOperand(3));
1376 BuildMI(BB, X86::MOVri8, 1, X86::AL).addZImm(Val);
1377 Opcode = X86::REP_STOSB;
1381 // If it's not a constant value we are storing, just fall back. We could
1382 // try to be clever to form 16 bit and 32 bit values, but we don't yet.
1383 unsigned ValReg = getReg(CI.getOperand(2));
1384 BuildMI(BB, X86::MOVrr8, 1, X86::AL).addReg(ValReg);
1385 CountReg = getReg(CI.getOperand(3));
1386 Opcode = X86::REP_STOSB;
1389 // No matter what the alignment is, we put the source in ESI, the
1390 // destination in EDI, and the count in ECX.
1391 TmpReg1 = getReg(CI.getOperand(1));
1392 //TmpReg2 = getReg(CI.getOperand(2));
1393 BuildMI(BB, X86::MOVrr32, 1, X86::ECX).addReg(CountReg);
1394 BuildMI(BB, X86::MOVrr32, 1, X86::EDI).addReg(TmpReg1);
1395 BuildMI(BB, Opcode, 0);
1399 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1404 /// visitSimpleBinary - Implement simple binary operators for integral types...
1405 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1407 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1408 unsigned DestReg = getReg(B);
1409 MachineBasicBlock::iterator MI = BB->end();
1410 emitSimpleBinaryOperation(BB, MI, B.getOperand(0), B.getOperand(1),
1411 OperatorClass, DestReg);
1414 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1415 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1418 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1419 /// and constant expression support.
1421 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1422 MachineBasicBlock::iterator IP,
1423 Value *Op0, Value *Op1,
1424 unsigned OperatorClass, unsigned DestReg) {
1425 unsigned Class = getClassB(Op0->getType());
1427 // sub 0, X -> neg X
1428 if (OperatorClass == 1 && Class != cLong)
1429 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0)) {
1430 if (CI->isNullValue()) {
1431 unsigned op1Reg = getReg(Op1, MBB, IP);
1433 default: assert(0 && "Unknown class for this function!");
1435 BMI(MBB, IP, X86::NEGr8, 1, DestReg).addReg(op1Reg);
1438 BMI(MBB, IP, X86::NEGr16, 1, DestReg).addReg(op1Reg);
1441 BMI(MBB, IP, X86::NEGr32, 1, DestReg).addReg(op1Reg);
1445 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
1446 if (CFP->isExactlyValue(-0.0)) {
1448 unsigned op1Reg = getReg(Op1, MBB, IP);
1449 BMI(MBB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg);
1453 if (!isa<ConstantInt>(Op1) || Class == cLong) {
1454 static const unsigned OpcodeTab[][4] = {
1455 // Arithmetic operators
1456 { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
1457 { X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
1459 // Bitwise operators
1460 { X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
1461 { X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
1462 { X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
1465 bool isLong = false;
1466 if (Class == cLong) {
1468 Class = cInt; // Bottom 32 bits are handled just like ints
1471 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1472 assert(Opcode && "Floating point arguments to logical inst?");
1473 unsigned Op0r = getReg(Op0, MBB, IP);
1474 unsigned Op1r = getReg(Op1, MBB, IP);
1475 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1477 if (isLong) { // Handle the upper 32 bits of long values...
1478 static const unsigned TopTab[] = {
1479 X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
1481 BMI(MBB, IP, TopTab[OperatorClass], 2,
1482 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
1487 // Special case: op Reg, <const>
1488 ConstantInt *Op1C = cast<ConstantInt>(Op1);
1489 unsigned Op0r = getReg(Op0, MBB, IP);
1491 // xor X, -1 -> not X
1492 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1493 static unsigned const NOTTab[] = { X86::NOTr8, X86::NOTr16, X86::NOTr32 };
1494 BMI(MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
1498 // add X, -1 -> dec X
1499 if (OperatorClass == 0 && Op1C->isAllOnesValue()) {
1500 static unsigned const DECTab[] = { X86::DECr8, X86::DECr16, X86::DECr32 };
1501 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1505 // add X, 1 -> inc X
1506 if (OperatorClass == 0 && Op1C->equalsInt(1)) {
1507 static unsigned const DECTab[] = { X86::INCr8, X86::INCr16, X86::INCr32 };
1508 BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
1512 static const unsigned OpcodeTab[][3] = {
1513 // Arithmetic operators
1514 { X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
1515 { X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
1517 // Bitwise operators
1518 { X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
1519 { X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
1520 { X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
1523 assert(Class < 3 && "General code handles 64-bit integer types!");
1524 unsigned Opcode = OpcodeTab[OperatorClass][Class];
1525 uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
1527 // Mask off any upper bits of the constant, if there are any...
1528 Op1v &= (1ULL << (8 << Class)) - 1;
1529 BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addZImm(Op1v);
1532 /// doMultiply - Emit appropriate instructions to multiply together the
1533 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1534 /// result should be given as DestTy.
1536 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
1537 unsigned DestReg, const Type *DestTy,
1538 unsigned op0Reg, unsigned op1Reg) {
1539 unsigned Class = getClass(DestTy);
1541 case cFP: // Floating point multiply
1542 BMI(BB, MBBI, X86::FpMUL, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1546 BMI(BB, MBBI, Class == cInt ? X86::IMULrr32 : X86::IMULrr16, 2, DestReg)
1547 .addReg(op0Reg).addReg(op1Reg);
1550 // Must use the MUL instruction, which forces use of AL...
1551 BMI(MBB, MBBI, X86::MOVrr8, 1, X86::AL).addReg(op0Reg);
1552 BMI(MBB, MBBI, X86::MULr8, 1).addReg(op1Reg);
1553 BMI(MBB, MBBI, X86::MOVrr8, 1, DestReg).addReg(X86::AL);
1556 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
1560 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1561 // returns zero when the input is not exactly a power of two.
1562 static unsigned ExactLog2(unsigned Val) {
1563 if (Val == 0) return 0;
1566 if (Val & 1) return 0;
1573 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
1574 MachineBasicBlock::iterator IP,
1575 unsigned DestReg, const Type *DestTy,
1576 unsigned op0Reg, unsigned ConstRHS) {
1577 unsigned Class = getClass(DestTy);
1579 // If the element size is exactly a power of 2, use a shift to get it.
1580 if (unsigned Shift = ExactLog2(ConstRHS)) {
1582 default: assert(0 && "Unknown class for this function!");
1584 BMI(MBB, IP, X86::SHLri32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1587 BMI(MBB, IP, X86::SHLri32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1590 BMI(MBB, IP, X86::SHLri32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
1595 if (Class == cShort) {
1596 BMI(MBB, IP, X86::IMULrri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1598 } else if (Class == cInt) {
1599 BMI(MBB, IP, X86::IMULrri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
1603 // Most general case, emit a normal multiply...
1604 static const unsigned MOVriTab[] = {
1605 X86::MOVri8, X86::MOVri16, X86::MOVri32
1608 unsigned TmpReg = makeAnotherReg(DestTy);
1609 BMI(MBB, IP, MOVriTab[Class], 1, TmpReg).addZImm(ConstRHS);
1611 // Emit a MUL to multiply the register holding the index by
1612 // elementSize, putting the result in OffsetReg.
1613 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
1616 /// visitMul - Multiplies are not simple binary operators because they must deal
1617 /// with the EAX register explicitly.
1619 void ISel::visitMul(BinaryOperator &I) {
1620 unsigned Op0Reg = getReg(I.getOperand(0));
1621 unsigned DestReg = getReg(I);
1623 // Simple scalar multiply?
1624 if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
1625 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1))) {
1626 unsigned Val = (unsigned)CI->getRawValue(); // Cannot be 64-bit constant
1627 MachineBasicBlock::iterator MBBI = BB->end();
1628 doMultiplyConst(BB, MBBI, DestReg, I.getType(), Op0Reg, Val);
1630 unsigned Op1Reg = getReg(I.getOperand(1));
1631 MachineBasicBlock::iterator MBBI = BB->end();
1632 doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
1635 unsigned Op1Reg = getReg(I.getOperand(1));
1637 // Long value. We have to do things the hard way...
1638 // Multiply the two low parts... capturing carry into EDX
1639 BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
1640 BuildMI(BB, X86::MULr32, 1).addReg(Op1Reg); // AL*BL
1642 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1643 BuildMI(BB, X86::MOVrr32, 1, DestReg).addReg(X86::EAX); // AL*BL
1644 BuildMI(BB, X86::MOVrr32, 1, OverflowReg).addReg(X86::EDX); // AL*BL >> 32
1646 MachineBasicBlock::iterator MBBI = BB->end();
1647 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
1648 BMI(BB, MBBI, X86::IMULrr32, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
1650 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1651 BuildMI(BB, X86::ADDrr32, 2, // AH*BL+(AL*BL >> 32)
1652 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1655 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1656 BMI(BB, MBBI, X86::IMULrr32, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
1658 BuildMI(BB, X86::ADDrr32, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1659 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1664 /// visitDivRem - Handle division and remainder instructions... these
1665 /// instruction both require the same instructions to be generated, they just
1666 /// select the result from a different register. Note that both of these
1667 /// instructions work differently for signed and unsigned operands.
1669 void ISel::visitDivRem(BinaryOperator &I) {
1670 unsigned Op0Reg = getReg(I.getOperand(0));
1671 unsigned Op1Reg = getReg(I.getOperand(1));
1672 unsigned ResultReg = getReg(I);
1674 MachineBasicBlock::iterator IP = BB->end();
1675 emitDivRemOperation(BB, IP, Op0Reg, Op1Reg, I.getOpcode() == Instruction::Div,
1676 I.getType(), ResultReg);
1679 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1680 MachineBasicBlock::iterator IP,
1681 unsigned Op0Reg, unsigned Op1Reg, bool isDiv,
1682 const Type *Ty, unsigned ResultReg) {
1683 unsigned Class = getClass(Ty);
1685 case cFP: // Floating point divide
1687 BMI(BB, IP, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1688 } else { // Floating point remainder...
1689 MachineInstr *TheCall =
1690 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
1691 std::vector<ValueRecord> Args;
1692 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1693 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1694 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1698 static const char *FnName[] =
1699 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1701 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
1702 MachineInstr *TheCall =
1703 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
1705 std::vector<ValueRecord> Args;
1706 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1707 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1708 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1711 case cByte: case cShort: case cInt:
1712 break; // Small integrals, handled below...
1713 default: assert(0 && "Unknown class!");
1716 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
1717 static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
1718 static const unsigned SarOpcode[]={ X86::SARri8, X86::SARri16, X86::SARri32 };
1719 static const unsigned ClrOpcode[]={ X86::MOVri8, X86::MOVri16, X86::MOVri32 };
1720 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
1722 static const unsigned DivOpcode[][4] = {
1723 { X86::DIVr8 , X86::DIVr16 , X86::DIVr32 , 0 }, // Unsigned division
1724 { X86::IDIVr8, X86::IDIVr16, X86::IDIVr32, 0 }, // Signed division
1727 bool isSigned = Ty->isSigned();
1728 unsigned Reg = Regs[Class];
1729 unsigned ExtReg = ExtRegs[Class];
1731 // Put the first operand into one of the A registers...
1732 BMI(BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
1735 // Emit a sign extension instruction...
1736 unsigned ShiftResult = makeAnotherReg(Ty);
1737 BMI(BB, IP, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31);
1738 BMI(BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
1740 // If unsigned, emit a zeroing instruction... (reg = 0)
1741 BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addZImm(0);
1744 // Emit the appropriate divide or remainder instruction...
1745 BMI(BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
1747 // Figure out which register we want to pick the result out of...
1748 unsigned DestReg = isDiv ? Reg : ExtReg;
1750 // Put the result into the destination register...
1751 BMI(BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
1755 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1756 /// for constant immediate shift values, and for constant immediate
1757 /// shift values equal to 1. Even the general case is sort of special,
1758 /// because the shift amount has to be in CL, not just any old register.
1760 void ISel::visitShiftInst(ShiftInst &I) {
1761 MachineBasicBlock::iterator IP = BB->end ();
1762 emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1),
1763 I.getOpcode () == Instruction::Shl, I.getType (),
1767 /// emitShiftOperation - Common code shared between visitShiftInst and
1768 /// constant expression support.
1769 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
1770 MachineBasicBlock::iterator IP,
1771 Value *Op, Value *ShiftAmount, bool isLeftShift,
1772 const Type *ResultTy, unsigned DestReg) {
1773 unsigned SrcReg = getReg (Op, MBB, IP);
1774 bool isSigned = ResultTy->isSigned ();
1775 unsigned Class = getClass (ResultTy);
1777 static const unsigned ConstantOperand[][4] = {
1778 { X86::SHRri8, X86::SHRri16, X86::SHRri32, X86::SHRDri32 }, // SHR
1779 { X86::SARri8, X86::SARri16, X86::SARri32, X86::SHRDri32 }, // SAR
1780 { X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDri32 }, // SHL
1781 { X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDri32 }, // SAL = SHL
1784 static const unsigned NonConstantOperand[][4] = {
1785 { X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
1786 { X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
1787 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
1788 { X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
1791 // Longs, as usual, are handled specially...
1792 if (Class == cLong) {
1793 // If we have a constant shift, we can generate much more efficient code
1794 // than otherwise...
1796 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
1797 unsigned Amount = CUI->getValue();
1799 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1801 BMI(MBB, IP, Opc[3], 3,
1802 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addZImm(Amount);
1803 BMI(MBB, IP, Opc[2], 2, DestReg).addReg(SrcReg).addZImm(Amount);
1805 BMI(MBB, IP, Opc[3], 3,
1806 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addZImm(Amount);
1807 BMI(MBB, IP, Opc[2], 2, DestReg+1).addReg(SrcReg+1).addZImm(Amount);
1809 } else { // Shifting more than 32 bits
1812 BMI(MBB, IP, X86::SHLri32, 2,
1813 DestReg + 1).addReg(SrcReg).addZImm(Amount);
1814 BMI(MBB, IP, X86::MOVri32, 1,
1815 DestReg).addZImm(0);
1817 unsigned Opcode = isSigned ? X86::SARri32 : X86::SHRri32;
1818 BMI(MBB, IP, Opcode, 2, DestReg).addReg(SrcReg+1).addZImm(Amount);
1819 BMI(MBB, IP, X86::MOVri32, 1, DestReg+1).addZImm(0);
1823 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1825 if (!isLeftShift && isSigned) {
1826 // If this is a SHR of a Long, then we need to do funny sign extension
1827 // stuff. TmpReg gets the value to use as the high-part if we are
1828 // shifting more than 32 bits.
1829 BMI(MBB, IP, X86::SARri32, 2, TmpReg).addReg(SrcReg).addZImm(31);
1831 // Other shifts use a fixed zero value if the shift is more than 32
1833 BMI(MBB, IP, X86::MOVri32, 1, TmpReg).addZImm(0);
1836 // Initialize CL with the shift amount...
1837 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
1838 BMI(MBB, IP, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmountReg);
1840 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
1841 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
1843 // TmpReg2 = shld inHi, inLo
1844 BMI(MBB, IP, X86::SHLDrr32, 2, TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
1845 // TmpReg3 = shl inLo, CL
1846 BMI(MBB, IP, X86::SHLrr32, 1, TmpReg3).addReg(SrcReg);
1848 // Set the flags to indicate whether the shift was by more than 32 bits.
1849 BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1851 // DestHi = (>32) ? TmpReg3 : TmpReg2;
1852 BMI(MBB, IP, X86::CMOVNErr32, 2,
1853 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
1854 // DestLo = (>32) ? TmpReg : TmpReg3;
1855 BMI(MBB, IP, X86::CMOVNErr32, 2,
1856 DestReg).addReg(TmpReg3).addReg(TmpReg);
1858 // TmpReg2 = shrd inLo, inHi
1859 BMI(MBB, IP, X86::SHRDrr32, 2, TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
1860 // TmpReg3 = s[ah]r inHi, CL
1861 BMI(MBB, IP, isSigned ? X86::SARrr32 : X86::SHRrr32, 1, TmpReg3)
1864 // Set the flags to indicate whether the shift was by more than 32 bits.
1865 BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
1867 // DestLo = (>32) ? TmpReg3 : TmpReg2;
1868 BMI(MBB, IP, X86::CMOVNErr32, 2,
1869 DestReg).addReg(TmpReg2).addReg(TmpReg3);
1871 // DestHi = (>32) ? TmpReg : TmpReg3;
1872 BMI(MBB, IP, X86::CMOVNErr32, 2,
1873 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
1879 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
1880 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
1881 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
1883 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
1884 BMI(MBB, IP, Opc[Class], 2,
1885 DestReg).addReg(SrcReg).addZImm(CUI->getValue());
1886 } else { // The shift amount is non-constant.
1887 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
1888 BMI(MBB, IP, X86::MOVrr8, 1, X86::CL).addReg(ShiftAmountReg);
1890 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
1891 BMI(MBB, IP, Opc[Class], 1, DestReg).addReg(SrcReg);
1896 /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
1897 /// instruction. The load and store instructions are the only place where we
1898 /// need to worry about the memory layout of the target machine.
1900 void ISel::visitLoadInst(LoadInst &I) {
1901 unsigned DestReg = getReg(I);
1902 unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
1903 Value *Addr = I.getOperand(0);
1904 if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Addr)) {
1905 if (isGEPFoldable(BB, GEP->getOperand(0), GEP->op_begin()+1, GEP->op_end(),
1906 BaseReg, Scale, IndexReg, Disp))
1907 Addr = 0; // Address is consumed!
1908 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Addr)) {
1909 if (CE->getOpcode() == Instruction::GetElementPtr)
1910 if (isGEPFoldable(BB, CE->getOperand(0), CE->op_begin()+1, CE->op_end(),
1911 BaseReg, Scale, IndexReg, Disp))
1916 // If it's not foldable, reset addr mode.
1917 BaseReg = getReg(Addr);
1918 Scale = 1; IndexReg = 0; Disp = 0;
1921 unsigned Class = getClassB(I.getType());
1922 if (Class == cLong) {
1923 addFullAddress(BuildMI(BB, X86::MOVrm32, 4, DestReg),
1924 BaseReg, Scale, IndexReg, Disp);
1925 addFullAddress(BuildMI(BB, X86::MOVrm32, 4, DestReg+1),
1926 BaseReg, Scale, IndexReg, Disp+4);
1930 static const unsigned Opcodes[] = {
1931 X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FLDr32
1933 unsigned Opcode = Opcodes[Class];
1934 if (I.getType() == Type::DoubleTy) Opcode = X86::FLDr64;
1935 addFullAddress(BuildMI(BB, Opcode, 4, DestReg),
1936 BaseReg, Scale, IndexReg, Disp);
1939 /// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
1942 void ISel::visitStoreInst(StoreInst &I) {
1943 unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
1944 Value *Addr = I.getOperand(1);
1945 if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Addr)) {
1946 if (isGEPFoldable(BB, GEP->getOperand(0), GEP->op_begin()+1, GEP->op_end(),
1947 BaseReg, Scale, IndexReg, Disp))
1948 Addr = 0; // Address is consumed!
1949 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Addr)) {
1950 if (CE->getOpcode() == Instruction::GetElementPtr)
1951 if (isGEPFoldable(BB, CE->getOperand(0), CE->op_begin()+1, CE->op_end(),
1952 BaseReg, Scale, IndexReg, Disp))
1957 // If it's not foldable, reset addr mode.
1958 BaseReg = getReg(Addr);
1959 Scale = 1; IndexReg = 0; Disp = 0;
1962 const Type *ValTy = I.getOperand(0)->getType();
1963 unsigned Class = getClassB(ValTy);
1965 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(0))) {
1966 uint64_t Val = CI->getRawValue();
1967 if (Class == cLong) {
1968 addFullAddress(BuildMI(BB, X86::MOVmi32, 5),
1969 BaseReg, Scale, IndexReg, Disp).addZImm(Val & ~0U);
1970 addFullAddress(BuildMI(BB, X86::MOVmi32, 5),
1971 BaseReg, Scale, IndexReg, Disp+4).addZImm(Val>>32);
1973 static const unsigned Opcodes[] = {
1974 X86::MOVmi8, X86::MOVmi16, X86::MOVmi32
1976 unsigned Opcode = Opcodes[Class];
1977 addFullAddress(BuildMI(BB, Opcode, 5),
1978 BaseReg, Scale, IndexReg, Disp).addZImm(Val);
1980 } else if (ConstantBool *CB = dyn_cast<ConstantBool>(I.getOperand(0))) {
1981 addFullAddress(BuildMI(BB, X86::MOVmi8, 5),
1982 BaseReg, Scale, IndexReg, Disp).addZImm(CB->getValue());
1984 if (Class == cLong) {
1985 unsigned ValReg = getReg(I.getOperand(0));
1986 addFullAddress(BuildMI(BB, X86::MOVmr32, 5),
1987 BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
1988 addFullAddress(BuildMI(BB, X86::MOVmr32, 5),
1989 BaseReg, Scale, IndexReg, Disp+4).addReg(ValReg+1);
1991 unsigned ValReg = getReg(I.getOperand(0));
1992 static const unsigned Opcodes[] = {
1993 X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FSTr32
1995 unsigned Opcode = Opcodes[Class];
1996 if (ValTy == Type::DoubleTy) Opcode = X86::FSTr64;
1997 addFullAddress(BuildMI(BB, Opcode, 1+4),
1998 BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
2004 /// visitCastInst - Here we have various kinds of copying with or without
2005 /// sign extension going on.
2006 void ISel::visitCastInst(CastInst &CI) {
2007 Value *Op = CI.getOperand(0);
2008 // If this is a cast from a 32-bit integer to a Long type, and the only uses
2009 // of the case are GEP instructions, then the cast does not need to be
2010 // generated explicitly, it will be folded into the GEP.
2011 if (CI.getType() == Type::LongTy &&
2012 (Op->getType() == Type::IntTy || Op->getType() == Type::UIntTy)) {
2013 bool AllUsesAreGEPs = true;
2014 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
2015 if (!isa<GetElementPtrInst>(*I)) {
2016 AllUsesAreGEPs = false;
2020 // No need to codegen this cast if all users are getelementptr instrs...
2021 if (AllUsesAreGEPs) return;
2024 unsigned DestReg = getReg(CI);
2025 MachineBasicBlock::iterator MI = BB->end();
2026 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
2029 /// emitCastOperation - Common code shared between visitCastInst and
2030 /// constant expression cast support.
2031 void ISel::emitCastOperation(MachineBasicBlock *BB,
2032 MachineBasicBlock::iterator IP,
2033 Value *Src, const Type *DestTy,
2035 unsigned SrcReg = getReg(Src, BB, IP);
2036 const Type *SrcTy = Src->getType();
2037 unsigned SrcClass = getClassB(SrcTy);
2038 unsigned DestClass = getClassB(DestTy);
2040 // Implement casts to bool by using compare on the operand followed by set if
2041 // not zero on the result.
2042 if (DestTy == Type::BoolTy) {
2045 BMI(BB, IP, X86::TESTrr8, 2).addReg(SrcReg).addReg(SrcReg);
2048 BMI(BB, IP, X86::TESTrr16, 2).addReg(SrcReg).addReg(SrcReg);
2051 BMI(BB, IP, X86::TESTrr32, 2).addReg(SrcReg).addReg(SrcReg);
2054 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2055 BMI(BB, IP, X86::ORrr32, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
2059 BMI(BB, IP, X86::FTST, 1).addReg(SrcReg);
2060 BMI(BB, IP, X86::FNSTSWr8, 0);
2061 BMI(BB, IP, X86::SAHF, 1);
2065 // If the zero flag is not set, then the value is true, set the byte to
2067 BMI(BB, IP, X86::SETNEr, 1, DestReg);
2071 static const unsigned RegRegMove[] = {
2072 X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV, X86::MOVrr32
2075 // Implement casts between values of the same type class (as determined by
2076 // getClass) by using a register-to-register move.
2077 if (SrcClass == DestClass) {
2078 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
2079 BMI(BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
2080 } else if (SrcClass == cFP) {
2081 if (SrcTy == Type::FloatTy) { // double -> float
2082 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
2083 BMI(BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
2084 } else { // float -> double
2085 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
2086 "Unknown cFP member!");
2087 // Truncate from double to float by storing to memory as short, then
2089 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
2090 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
2091 addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg);
2092 addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx);
2094 } else if (SrcClass == cLong) {
2095 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
2096 BMI(BB, IP, X86::MOVrr32, 1, DestReg+1).addReg(SrcReg+1);
2098 assert(0 && "Cannot handle this type of cast instruction!");
2104 // Handle cast of SMALLER int to LARGER int using a move with sign extension
2105 // or zero extension, depending on whether the source type was signed.
2106 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
2107 SrcClass < DestClass) {
2108 bool isLong = DestClass == cLong;
2109 if (isLong) DestClass = cInt;
2111 static const unsigned Opc[][4] = {
2112 { X86::MOVSXr16r8, X86::MOVSXr32r8, X86::MOVSXr32r16, X86::MOVrr32 }, // s
2113 { X86::MOVZXr16r8, X86::MOVZXr32r8, X86::MOVZXr32r16, X86::MOVrr32 } // u
2116 bool isUnsigned = SrcTy->isUnsigned();
2117 BMI(BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
2118 DestReg).addReg(SrcReg);
2120 if (isLong) { // Handle upper 32 bits as appropriate...
2121 if (isUnsigned) // Zero out top bits...
2122 BMI(BB, IP, X86::MOVri32, 1, DestReg+1).addZImm(0);
2123 else // Sign extend bottom half...
2124 BMI(BB, IP, X86::SARri32, 2, DestReg+1).addReg(DestReg).addZImm(31);
2129 // Special case long -> int ...
2130 if (SrcClass == cLong && DestClass == cInt) {
2131 BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
2135 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
2136 // move out of AX or AL.
2137 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
2138 && SrcClass > DestClass) {
2139 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
2140 BMI(BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
2141 BMI(BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
2145 // Handle casts from integer to floating point now...
2146 if (DestClass == cFP) {
2147 // Promote the integer to a type supported by FLD. We do this because there
2148 // are no unsigned FLD instructions, so we must promote an unsigned value to
2149 // a larger signed value, then use FLD on the larger value.
2151 const Type *PromoteType = 0;
2152 unsigned PromoteOpcode;
2153 unsigned RealDestReg = DestReg;
2154 switch (SrcTy->getPrimitiveID()) {
2155 case Type::BoolTyID:
2156 case Type::SByteTyID:
2157 // We don't have the facilities for directly loading byte sized data from
2158 // memory (even signed). Promote it to 16 bits.
2159 PromoteType = Type::ShortTy;
2160 PromoteOpcode = X86::MOVSXr16r8;
2162 case Type::UByteTyID:
2163 PromoteType = Type::ShortTy;
2164 PromoteOpcode = X86::MOVZXr16r8;
2166 case Type::UShortTyID:
2167 PromoteType = Type::IntTy;
2168 PromoteOpcode = X86::MOVZXr32r16;
2170 case Type::UIntTyID: {
2171 // Make a 64 bit temporary... and zero out the top of it...
2172 unsigned TmpReg = makeAnotherReg(Type::LongTy);
2173 BMI(BB, IP, X86::MOVrr32, 1, TmpReg).addReg(SrcReg);
2174 BMI(BB, IP, X86::MOVri32, 1, TmpReg+1).addZImm(0);
2175 SrcTy = Type::LongTy;
2180 case Type::ULongTyID:
2181 // Don't fild into the read destination.
2182 DestReg = makeAnotherReg(Type::DoubleTy);
2184 default: // No promotion needed...
2189 unsigned TmpReg = makeAnotherReg(PromoteType);
2190 unsigned Opc = SrcTy->isSigned() ? X86::MOVSXr16r8 : X86::MOVZXr16r8;
2191 BMI(BB, IP, Opc, 1, TmpReg).addReg(SrcReg);
2192 SrcTy = PromoteType;
2193 SrcClass = getClass(PromoteType);
2197 // Spill the integer to memory and reload it from there...
2199 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
2201 if (SrcClass == cLong) {
2202 addFrameReference(BMI(BB, IP, X86::MOVmr32, 5), FrameIdx).addReg(SrcReg);
2203 addFrameReference(BMI(BB, IP, X86::MOVmr32, 5),
2204 FrameIdx, 4).addReg(SrcReg+1);
2206 static const unsigned Op1[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
2207 addFrameReference(BMI(BB, IP, Op1[SrcClass], 5), FrameIdx).addReg(SrcReg);
2210 static const unsigned Op2[] =
2211 { 0/*byte*/, X86::FILDr16, X86::FILDr32, 0/*FP*/, X86::FILDr64 };
2212 addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
2214 // We need special handling for unsigned 64-bit integer sources. If the
2215 // input number has the "sign bit" set, then we loaded it incorrectly as a
2216 // negative 64-bit number. In this case, add an offset value.
2217 if (SrcTy == Type::ULongTy) {
2218 // Emit a test instruction to see if the dynamic input value was signed.
2219 BMI(BB, IP, X86::TESTrr32, 2).addReg(SrcReg+1).addReg(SrcReg+1);
2221 // If the sign bit is set, get a pointer to an offset, otherwise get a
2222 // pointer to a zero.
2223 MachineConstantPool *CP = F->getConstantPool();
2224 unsigned Zero = makeAnotherReg(Type::IntTy);
2225 Constant *Null = Constant::getNullValue(Type::UIntTy);
2226 addConstantPoolReference(BMI(BB, IP, X86::LEAr32, 5, Zero),
2227 CP->getConstantPoolIndex(Null));
2228 unsigned Offset = makeAnotherReg(Type::IntTy);
2229 Constant *OffsetCst = ConstantUInt::get(Type::UIntTy, 0x5f800000);
2231 addConstantPoolReference(BMI(BB, IP, X86::LEAr32, 5, Offset),
2232 CP->getConstantPoolIndex(OffsetCst));
2233 unsigned Addr = makeAnotherReg(Type::IntTy);
2234 BMI(BB, IP, X86::CMOVSrr32, 2, Addr).addReg(Zero).addReg(Offset);
2236 // Load the constant for an add. FIXME: this could make an 'fadd' that
2237 // reads directly from memory, but we don't support these yet.
2238 unsigned ConstReg = makeAnotherReg(Type::DoubleTy);
2239 addDirectMem(BMI(BB, IP, X86::FLDr32, 4, ConstReg), Addr);
2241 BMI(BB, IP, X86::FpADD, 2, RealDestReg).addReg(ConstReg).addReg(DestReg);
2247 // Handle casts from floating point to integer now...
2248 if (SrcClass == cFP) {
2249 // Change the floating point control register to use "round towards zero"
2250 // mode when truncating to an integer value.
2252 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
2253 addFrameReference(BMI(BB, IP, X86::FNSTCWm16, 4), CWFrameIdx);
2255 // Load the old value of the high byte of the control word...
2256 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
2257 addFrameReference(BMI(BB, IP, X86::MOVrm8, 4, HighPartOfCW), CWFrameIdx, 1);
2259 // Set the high part to be round to zero...
2260 addFrameReference(BMI(BB, IP, X86::MOVmi8, 5), CWFrameIdx, 1).addZImm(12);
2262 // Reload the modified control word now...
2263 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
2265 // Restore the memory image of control word to original value
2266 addFrameReference(BMI(BB, IP, X86::MOVmr8, 5),
2267 CWFrameIdx, 1).addReg(HighPartOfCW);
2269 // We don't have the facilities for directly storing byte sized data to
2270 // memory. Promote it to 16 bits. We also must promote unsigned values to
2271 // larger classes because we only have signed FP stores.
2272 unsigned StoreClass = DestClass;
2273 const Type *StoreTy = DestTy;
2274 if (StoreClass == cByte || DestTy->isUnsigned())
2275 switch (StoreClass) {
2276 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
2277 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
2278 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
2279 // The following treatment of cLong may not be perfectly right,
2280 // but it survives chains of casts of the form
2281 // double->ulong->double.
2282 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
2283 default: assert(0 && "Unknown store class!");
2286 // Spill the integer to memory and reload it from there...
2288 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
2290 static const unsigned Op1[] =
2291 { 0, X86::FISTr16, X86::FISTr32, 0, X86::FISTPr64 };
2292 addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg);
2294 if (DestClass == cLong) {
2295 addFrameReference(BMI(BB, IP, X86::MOVrm32, 4, DestReg), FrameIdx);
2296 addFrameReference(BMI(BB, IP, X86::MOVrm32, 4, DestReg+1), FrameIdx, 4);
2298 static const unsigned Op2[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
2299 addFrameReference(BMI(BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
2302 // Reload the original control word now...
2303 addFrameReference(BMI(BB, IP, X86::FLDCWm16, 4), CWFrameIdx);
2307 // Anything we haven't handled already, we can't (yet) handle at all.
2308 assert(0 && "Unhandled cast instruction!");
2312 /// visitVANextInst - Implement the va_next instruction...
2314 void ISel::visitVANextInst(VANextInst &I) {
2315 unsigned VAList = getReg(I.getOperand(0));
2316 unsigned DestReg = getReg(I);
2319 switch (I.getArgType()->getPrimitiveID()) {
2322 assert(0 && "Error: bad type for va_next instruction!");
2324 case Type::PointerTyID:
2325 case Type::UIntTyID:
2329 case Type::ULongTyID:
2330 case Type::LongTyID:
2331 case Type::DoubleTyID:
2336 // Increment the VAList pointer...
2337 BuildMI(BB, X86::ADDri32, 2, DestReg).addReg(VAList).addZImm(Size);
2340 void ISel::visitVAArgInst(VAArgInst &I) {
2341 unsigned VAList = getReg(I.getOperand(0));
2342 unsigned DestReg = getReg(I);
2344 switch (I.getType()->getPrimitiveID()) {
2347 assert(0 && "Error: bad type for va_next instruction!");
2349 case Type::PointerTyID:
2350 case Type::UIntTyID:
2352 addDirectMem(BuildMI(BB, X86::MOVrm32, 4, DestReg), VAList);
2354 case Type::ULongTyID:
2355 case Type::LongTyID:
2356 addDirectMem(BuildMI(BB, X86::MOVrm32, 4, DestReg), VAList);
2357 addRegOffset(BuildMI(BB, X86::MOVrm32, 4, DestReg+1), VAList, 4);
2359 case Type::DoubleTyID:
2360 addDirectMem(BuildMI(BB, X86::FLDr64, 4, DestReg), VAList);
2366 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
2367 // If this GEP instruction will be folded into all of its users, we don't need
2368 // to explicitly calculate it!
2369 unsigned A, B, C, D;
2370 if (isGEPFoldable(0, I.getOperand(0), I.op_begin()+1, I.op_end(), A,B,C,D)) {
2371 // Check all of the users of the instruction to see if they are loads and
2373 bool AllWillFold = true;
2374 for (Value::use_iterator UI = I.use_begin(), E = I.use_end(); UI != E; ++UI)
2375 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Load)
2376 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Store ||
2377 cast<Instruction>(*UI)->getOperand(0) == &I) {
2378 AllWillFold = false;
2382 // If the instruction is foldable, and will be folded into all users, don't
2384 if (AllWillFold) return;
2387 unsigned outputReg = getReg(I);
2388 emitGEPOperation(BB, BB->end(), I.getOperand(0),
2389 I.op_begin()+1, I.op_end(), outputReg);
2392 /// getGEPIndex - Inspect the getelementptr operands specified with GEPOps and
2393 /// GEPTypes (the derived types being stepped through at each level). On return
2394 /// from this function, if some indexes of the instruction are representable as
2395 /// an X86 lea instruction, the machine operands are put into the Ops
2396 /// instruction and the consumed indexes are poped from the GEPOps/GEPTypes
2397 /// lists. Otherwise, GEPOps.size() is returned. If this returns a an
2398 /// addressing mode that only partially consumes the input, the BaseReg input of
2399 /// the addressing mode must be left free.
2401 /// Note that there is one fewer entry in GEPTypes than there is in GEPOps.
2403 void ISel::getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
2404 std::vector<Value*> &GEPOps,
2405 std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
2406 unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
2407 const TargetData &TD = TM.getTargetData();
2409 // Clear out the state we are working with...
2410 BaseReg = 0; // No base register
2411 Scale = 1; // Unit scale
2412 IndexReg = 0; // No index register
2413 Disp = 0; // No displacement
2415 // While there are GEP indexes that can be folded into the current address,
2416 // keep processing them.
2417 while (!GEPTypes.empty()) {
2418 if (const StructType *StTy = dyn_cast<StructType>(GEPTypes.back())) {
2419 // It's a struct access. CUI is the index into the structure,
2420 // which names the field. This index must have unsigned type.
2421 const ConstantUInt *CUI = cast<ConstantUInt>(GEPOps.back());
2423 // Use the TargetData structure to pick out what the layout of the
2424 // structure is in memory. Since the structure index must be constant, we
2425 // can get its value and use it to find the right byte offset from the
2426 // StructLayout class's list of structure member offsets.
2427 Disp += TD.getStructLayout(StTy)->MemberOffsets[CUI->getValue()];
2428 GEPOps.pop_back(); // Consume a GEP operand
2429 GEPTypes.pop_back();
2431 // It's an array or pointer access: [ArraySize x ElementType].
2432 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
2433 Value *idx = GEPOps.back();
2435 // idx is the index into the array. Unlike with structure
2436 // indices, we may not know its actual value at code-generation
2438 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
2440 // If idx is a constant, fold it into the offset.
2441 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
2442 Disp += TD.getTypeSize(SqTy->getElementType())*CSI->getValue();
2444 // If we can't handle it, return.
2448 GEPOps.pop_back(); // Consume a GEP operand
2449 GEPTypes.pop_back();
2453 // GEPTypes is empty, which means we have a single operand left. See if we
2454 // can set it as the base register.
2456 // FIXME: When addressing modes are more powerful/correct, we could load
2457 // global addresses directly as 32-bit immediates.
2458 assert(BaseReg == 0);
2459 BaseReg = MBB ? getReg(GEPOps[0], MBB, IP) : 0;
2460 GEPOps.pop_back(); // Consume the last GEP operand
2464 /// isGEPFoldable - Return true if the specified GEP can be completely
2465 /// folded into the addressing mode of a load/store or lea instruction.
2466 bool ISel::isGEPFoldable(MachineBasicBlock *MBB,
2467 Value *Src, User::op_iterator IdxBegin,
2468 User::op_iterator IdxEnd, unsigned &BaseReg,
2469 unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
2470 if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
2471 Src = CPR->getValue();
2473 std::vector<Value*> GEPOps;
2474 GEPOps.resize(IdxEnd-IdxBegin+1);
2476 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
2478 std::vector<const Type*> GEPTypes;
2479 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
2480 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
2482 MachineBasicBlock::iterator IP;
2483 if (MBB) IP = MBB->end();
2484 getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
2486 // We can fold it away iff the getGEPIndex call eliminated all operands.
2487 return GEPOps.empty();
2490 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
2491 MachineBasicBlock::iterator IP,
2492 Value *Src, User::op_iterator IdxBegin,
2493 User::op_iterator IdxEnd, unsigned TargetReg) {
2494 const TargetData &TD = TM.getTargetData();
2495 if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
2496 Src = CPR->getValue();
2498 std::vector<Value*> GEPOps;
2499 GEPOps.resize(IdxEnd-IdxBegin+1);
2501 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
2503 std::vector<const Type*> GEPTypes;
2504 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
2505 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
2507 // Keep emitting instructions until we consume the entire GEP instruction.
2508 while (!GEPOps.empty()) {
2509 unsigned OldSize = GEPOps.size();
2510 unsigned BaseReg, Scale, IndexReg, Disp;
2511 getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
2513 if (GEPOps.size() != OldSize) {
2514 // getGEPIndex consumed some of the input. Build an LEA instruction here.
2515 unsigned NextTarget = 0;
2516 if (!GEPOps.empty()) {
2517 assert(BaseReg == 0 &&
2518 "getGEPIndex should have left the base register open for chaining!");
2519 NextTarget = BaseReg = makeAnotherReg(Type::UIntTy);
2522 if (IndexReg == 0 && Disp == 0)
2523 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
2525 addFullAddress(BMI(MBB, IP, X86::LEAr32, 5, TargetReg),
2526 BaseReg, Scale, IndexReg, Disp);
2528 TargetReg = NextTarget;
2529 } else if (GEPTypes.empty()) {
2530 // The getGEPIndex operation didn't want to build an LEA. Check to see if
2531 // all operands are consumed but the base pointer. If so, just load it
2532 // into the register.
2533 if (GlobalValue *GV = dyn_cast<GlobalValue>(GEPOps[0])) {
2534 BMI(MBB, IP, X86::MOVri32, 1, TargetReg).addGlobalAddress(GV);
2536 unsigned BaseReg = getReg(GEPOps[0], MBB, IP);
2537 BMI(MBB, IP, X86::MOVrr32, 1, TargetReg).addReg(BaseReg);
2539 break; // we are now done
2541 } else if (const StructType *StTy = dyn_cast<StructType>(GEPTypes.back())) {
2542 // It's a struct access. CUI is the index into the structure,
2543 // which names the field. This index must have unsigned type.
2544 const ConstantUInt *CUI = cast<ConstantUInt>(GEPOps.back());
2545 GEPOps.pop_back(); // Consume a GEP operand
2546 GEPTypes.pop_back();
2548 // Use the TargetData structure to pick out what the layout of the
2549 // structure is in memory. Since the structure index must be constant, we
2550 // can get its value and use it to find the right byte offset from the
2551 // StructLayout class's list of structure member offsets.
2552 unsigned idxValue = CUI->getValue();
2553 unsigned FieldOff = TD.getStructLayout(StTy)->MemberOffsets[idxValue];
2555 unsigned Reg = makeAnotherReg(Type::UIntTy);
2556 // Emit an ADD to add FieldOff to the basePtr.
2557 BMI(MBB, IP, X86::ADDri32, 2, TargetReg).addReg(Reg).addZImm(FieldOff);
2558 --IP; // Insert the next instruction before this one.
2559 TargetReg = Reg; // Codegen the rest of the GEP into this
2562 // It's an array or pointer access: [ArraySize x ElementType].
2563 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
2564 Value *idx = GEPOps.back();
2565 GEPOps.pop_back(); // Consume a GEP operand
2566 GEPTypes.pop_back();
2568 // idx is the index into the array. Unlike with structure
2569 // indices, we may not know its actual value at code-generation
2571 assert(idx->getType() == Type::LongTy && "Bad GEP array index!");
2573 // Most GEP instructions use a [cast (int/uint) to LongTy] as their
2574 // operand on X86. Handle this case directly now...
2575 if (CastInst *CI = dyn_cast<CastInst>(idx))
2576 if (CI->getOperand(0)->getType() == Type::IntTy ||
2577 CI->getOperand(0)->getType() == Type::UIntTy)
2578 idx = CI->getOperand(0);
2580 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
2581 // must find the size of the pointed-to type (Not coincidentally, the next
2582 // type is the type of the elements in the array).
2583 const Type *ElTy = SqTy->getElementType();
2584 unsigned elementSize = TD.getTypeSize(ElTy);
2586 // If idxReg is a constant, we don't need to perform the multiply!
2587 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
2588 if (!CSI->isNullValue()) {
2589 unsigned Offset = elementSize*CSI->getValue();
2590 unsigned Reg = makeAnotherReg(Type::UIntTy);
2591 BMI(MBB, IP, X86::ADDri32, 2, TargetReg).addReg(Reg).addZImm(Offset);
2592 --IP; // Insert the next instruction before this one.
2593 TargetReg = Reg; // Codegen the rest of the GEP into this
2595 } else if (elementSize == 1) {
2596 // If the element size is 1, we don't have to multiply, just add
2597 unsigned idxReg = getReg(idx, MBB, IP);
2598 unsigned Reg = makeAnotherReg(Type::UIntTy);
2599 BMI(MBB, IP, X86::ADDrr32, 2, TargetReg).addReg(Reg).addReg(idxReg);
2600 --IP; // Insert the next instruction before this one.
2601 TargetReg = Reg; // Codegen the rest of the GEP into this
2603 unsigned idxReg = getReg(idx, MBB, IP);
2604 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
2606 // Make sure we can back the iterator up to point to the first
2607 // instruction emitted.
2608 MachineBasicBlock::iterator BeforeIt = IP;
2609 if (IP == MBB->begin())
2610 BeforeIt = MBB->end();
2613 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
2615 // Emit an ADD to add OffsetReg to the basePtr.
2616 unsigned Reg = makeAnotherReg(Type::UIntTy);
2617 BMI(MBB, IP, X86::ADDrr32, 2, TargetReg).addReg(Reg).addReg(OffsetReg);
2619 // Step to the first instruction of the multiply.
2620 if (BeforeIt == MBB->end())
2625 TargetReg = Reg; // Codegen the rest of the GEP into this
2632 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2633 /// frame manager, otherwise do it the hard way.
2635 void ISel::visitAllocaInst(AllocaInst &I) {
2636 // Find the data size of the alloca inst's getAllocatedType.
2637 const Type *Ty = I.getAllocatedType();
2638 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2640 // If this is a fixed size alloca in the entry block for the function,
2641 // statically stack allocate the space.
2643 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(I.getArraySize())) {
2644 if (I.getParent() == I.getParent()->getParent()->begin()) {
2645 TySize *= CUI->getValue(); // Get total allocated size...
2646 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
2648 // Create a new stack object using the frame manager...
2649 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
2650 addFrameReference(BuildMI(BB, X86::LEAr32, 5, getReg(I)), FrameIdx);
2655 // Create a register to hold the temporary result of multiplying the type size
2656 // constant by the variable amount.
2657 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2658 unsigned SrcReg1 = getReg(I.getArraySize());
2660 // TotalSizeReg = mul <numelements>, <TypeSize>
2661 MachineBasicBlock::iterator MBBI = BB->end();
2662 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
2664 // AddedSize = add <TotalSizeReg>, 15
2665 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2666 BuildMI(BB, X86::ADDri32, 2, AddedSizeReg).addReg(TotalSizeReg).addZImm(15);
2668 // AlignedSize = and <AddedSize>, ~15
2669 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2670 BuildMI(BB, X86::ANDri32, 2, AlignedSize).addReg(AddedSizeReg).addZImm(~15);
2672 // Subtract size from stack pointer, thereby allocating some space.
2673 BuildMI(BB, X86::SUBrr32, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
2675 // Put a pointer to the space into the result register, by copying
2676 // the stack pointer.
2677 BuildMI(BB, X86::MOVrr32, 1, getReg(I)).addReg(X86::ESP);
2679 // Inform the Frame Information that we have just allocated a variable-sized
2681 F->getFrameInfo()->CreateVariableSizedObject();
2684 /// visitMallocInst - Malloc instructions are code generated into direct calls
2685 /// to the library malloc.
2687 void ISel::visitMallocInst(MallocInst &I) {
2688 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2691 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2692 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2694 Arg = makeAnotherReg(Type::UIntTy);
2695 unsigned Op0Reg = getReg(I.getOperand(0));
2696 MachineBasicBlock::iterator MBBI = BB->end();
2697 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
2700 std::vector<ValueRecord> Args;
2701 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2702 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2703 1).addExternalSymbol("malloc", true);
2704 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
2708 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2711 void ISel::visitFreeInst(FreeInst &I) {
2712 std::vector<ValueRecord> Args;
2713 Args.push_back(ValueRecord(I.getOperand(0)));
2714 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
2715 1).addExternalSymbol("free", true);
2716 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
2719 /// createX86SimpleInstructionSelector - This pass converts an LLVM function
2720 /// into a machine code representation is a very simple peep-hole fashion. The
2721 /// generated code sucks but the implementation is nice and simple.
2723 FunctionPass *llvm::createX86SimpleInstructionSelector(TargetMachine &TM) {
2724 return new ISel(TM);