1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "MCTargetDesc/X86FixupKinds.h"
12 #include "llvm/MC/MCAsmBackend.h"
13 #include "llvm/MC/MCAssembler.h"
14 #include "llvm/MC/MCELFObjectWriter.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixupKindInfo.h"
17 #include "llvm/MC/MCMachObjectWriter.h"
18 #include "llvm/MC/MCObjectWriter.h"
19 #include "llvm/MC/MCSectionCOFF.h"
20 #include "llvm/MC/MCSectionELF.h"
21 #include "llvm/MC/MCSectionMachO.h"
22 #include "llvm/Object/MachOFormat.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/ELF.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
30 // Option to allow disabling arithmetic relaxation to workaround PR9807, which
31 // is useful when running bitwise comparison experiments on Darwin. We should be
32 // able to remove this once PR9807 is resolved.
34 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
35 cl::desc("Disable relaxation of arithmetic instruction for X86"));
37 static unsigned getFixupKindLog2Size(unsigned Kind) {
39 default: llvm_unreachable("invalid fixup kind!");
42 case FK_Data_1: return 0;
45 case FK_Data_2: return 1;
47 case X86::reloc_riprel_4byte:
48 case X86::reloc_riprel_4byte_movq_load:
49 case X86::reloc_signed_4byte:
50 case X86::reloc_global_offset_table:
52 case FK_Data_4: return 2;
55 case FK_Data_8: return 3;
61 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
63 X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
64 bool HasRelocationAddend, bool foobar)
65 : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
68 class X86AsmBackend : public MCAsmBackend {
71 X86AsmBackend(const Target &T, StringRef _CPU)
72 : MCAsmBackend(), CPU(_CPU) {}
74 unsigned getNumFixupKinds() const {
75 return X86::NumTargetFixupKinds;
78 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
79 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
80 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
81 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
82 { "reloc_signed_4byte", 0, 4 * 8, 0},
83 { "reloc_global_offset_table", 0, 4 * 8, 0}
86 if (Kind < FirstTargetFixupKind)
87 return MCAsmBackend::getFixupKindInfo(Kind);
89 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
91 return Infos[Kind - FirstTargetFixupKind];
94 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
95 uint64_t Value) const {
96 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
98 assert(Fixup.getOffset() + Size <= DataSize &&
99 "Invalid fixup offset!");
101 // Check that uppper bits are either all zeros or all ones.
102 // Specifically ignore overflow/underflow as long as the leakage is
103 // limited to the lower bits. This is to remain compatible with
105 assert(isIntN(Size * 8 + 1, Value) &&
106 "Value does not fit in the Fixup field");
108 for (unsigned i = 0; i != Size; ++i)
109 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
112 bool mayNeedRelaxation(const MCInst &Inst) const;
114 bool fixupNeedsRelaxation(const MCFixup &Fixup,
116 const MCInstFragment *DF,
117 const MCAsmLayout &Layout) const;
119 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
121 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
123 } // end anonymous namespace
125 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
130 case X86::JAE_1: return X86::JAE_4;
131 case X86::JA_1: return X86::JA_4;
132 case X86::JBE_1: return X86::JBE_4;
133 case X86::JB_1: return X86::JB_4;
134 case X86::JE_1: return X86::JE_4;
135 case X86::JGE_1: return X86::JGE_4;
136 case X86::JG_1: return X86::JG_4;
137 case X86::JLE_1: return X86::JLE_4;
138 case X86::JL_1: return X86::JL_4;
139 case X86::JMP_1: return X86::JMP_4;
140 case X86::JNE_1: return X86::JNE_4;
141 case X86::JNO_1: return X86::JNO_4;
142 case X86::JNP_1: return X86::JNP_4;
143 case X86::JNS_1: return X86::JNS_4;
144 case X86::JO_1: return X86::JO_4;
145 case X86::JP_1: return X86::JP_4;
146 case X86::JS_1: return X86::JS_4;
150 static unsigned getRelaxedOpcodeArith(unsigned Op) {
156 case X86::IMUL16rri8: return X86::IMUL16rri;
157 case X86::IMUL16rmi8: return X86::IMUL16rmi;
158 case X86::IMUL32rri8: return X86::IMUL32rri;
159 case X86::IMUL32rmi8: return X86::IMUL32rmi;
160 case X86::IMUL64rri8: return X86::IMUL64rri32;
161 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
164 case X86::AND16ri8: return X86::AND16ri;
165 case X86::AND16mi8: return X86::AND16mi;
166 case X86::AND32ri8: return X86::AND32ri;
167 case X86::AND32mi8: return X86::AND32mi;
168 case X86::AND64ri8: return X86::AND64ri32;
169 case X86::AND64mi8: return X86::AND64mi32;
172 case X86::OR16ri8: return X86::OR16ri;
173 case X86::OR16mi8: return X86::OR16mi;
174 case X86::OR32ri8: return X86::OR32ri;
175 case X86::OR32mi8: return X86::OR32mi;
176 case X86::OR64ri8: return X86::OR64ri32;
177 case X86::OR64mi8: return X86::OR64mi32;
180 case X86::XOR16ri8: return X86::XOR16ri;
181 case X86::XOR16mi8: return X86::XOR16mi;
182 case X86::XOR32ri8: return X86::XOR32ri;
183 case X86::XOR32mi8: return X86::XOR32mi;
184 case X86::XOR64ri8: return X86::XOR64ri32;
185 case X86::XOR64mi8: return X86::XOR64mi32;
188 case X86::ADD16ri8: return X86::ADD16ri;
189 case X86::ADD16mi8: return X86::ADD16mi;
190 case X86::ADD32ri8: return X86::ADD32ri;
191 case X86::ADD32mi8: return X86::ADD32mi;
192 case X86::ADD64ri8: return X86::ADD64ri32;
193 case X86::ADD64mi8: return X86::ADD64mi32;
196 case X86::SUB16ri8: return X86::SUB16ri;
197 case X86::SUB16mi8: return X86::SUB16mi;
198 case X86::SUB32ri8: return X86::SUB32ri;
199 case X86::SUB32mi8: return X86::SUB32mi;
200 case X86::SUB64ri8: return X86::SUB64ri32;
201 case X86::SUB64mi8: return X86::SUB64mi32;
204 case X86::CMP16ri8: return X86::CMP16ri;
205 case X86::CMP16mi8: return X86::CMP16mi;
206 case X86::CMP32ri8: return X86::CMP32ri;
207 case X86::CMP32mi8: return X86::CMP32mi;
208 case X86::CMP64ri8: return X86::CMP64ri32;
209 case X86::CMP64mi8: return X86::CMP64mi32;
212 case X86::PUSHi8: return X86::PUSHi32;
213 case X86::PUSHi16: return X86::PUSHi32;
214 case X86::PUSH64i8: return X86::PUSH64i32;
215 case X86::PUSH64i16: return X86::PUSH64i32;
219 static unsigned getRelaxedOpcode(unsigned Op) {
220 unsigned R = getRelaxedOpcodeArith(Op);
223 return getRelaxedOpcodeBranch(Op);
226 bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
227 // Branches can always be relaxed.
228 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
231 if (MCDisableArithRelaxation)
234 // Check if this instruction is ever relaxable.
235 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
239 // Check if it has an expression and is not RIP relative.
242 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
243 const MCOperand &Op = Inst.getOperand(i);
247 if (Op.isReg() && Op.getReg() == X86::RIP)
251 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
252 // how we do relaxations?
253 return hasExp && !hasRIP;
256 bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
258 const MCInstFragment *DF,
259 const MCAsmLayout &Layout) const {
260 // Relax if the value is too big for a (signed) i8.
261 return int64_t(Value) != int64_t(int8_t(Value));
264 // FIXME: Can tblgen help at all here to verify there aren't other instructions
266 void X86AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
267 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
268 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
270 if (RelaxedOp == Inst.getOpcode()) {
271 SmallString<256> Tmp;
272 raw_svector_ostream OS(Tmp);
273 Inst.dump_pretty(OS);
275 report_fatal_error("unexpected instruction to relax: " + OS.str());
279 Res.setOpcode(RelaxedOp);
282 /// \brief Write a sequence of optimal nops to the output, covering \p Count
284 /// \return - true on success, false on failure
285 bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
286 static const uint8_t Nops[10][10] = {
294 {0x0f, 0x1f, 0x40, 0x00},
295 // nopl 0(%[re]ax,%[re]ax,1)
296 {0x0f, 0x1f, 0x44, 0x00, 0x00},
297 // nopw 0(%[re]ax,%[re]ax,1)
298 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
300 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
301 // nopl 0L(%[re]ax,%[re]ax,1)
302 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
303 // nopw 0L(%[re]ax,%[re]ax,1)
304 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
305 // nopw %cs:0L(%[re]ax,%[re]ax,1)
306 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
309 // This CPU doesnt support long nops. If needed add more.
310 // FIXME: Can we get this from the subtarget somehow?
311 if (CPU == "generic" || CPU == "i386" || CPU == "i486" || CPU == "i586" ||
312 CPU == "pentium" || CPU == "pentium-mmx" || CPU == "geode") {
313 for (uint64_t i = 0; i < Count; ++i)
318 // Write an optimal sequence for the first 15 bytes.
319 const uint64_t OptimalCount = (Count < 16) ? Count : 15;
320 const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10;
321 for (uint64_t i = 0, e = Prefixes; i != e; i++)
323 const uint64_t Rest = OptimalCount - Prefixes;
324 for (uint64_t i = 0, e = Rest; i != e; i++)
325 OW->Write8(Nops[Rest - 1][i]);
327 // Finish with single byte nops.
328 for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
337 class ELFX86AsmBackend : public X86AsmBackend {
340 ELFX86AsmBackend(const Target &T, uint8_t _OSABI, StringRef CPU)
341 : X86AsmBackend(T, CPU), OSABI(_OSABI) {
342 HasReliableSymbolDifference = true;
345 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
346 const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
347 return ES.getFlags() & ELF::SHF_MERGE;
351 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
353 ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
354 : ELFX86AsmBackend(T, OSABI, CPU) {}
356 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
357 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386);
361 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
363 ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
364 : ELFX86AsmBackend(T, OSABI, CPU) {}
366 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
367 return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64);
371 class WindowsX86AsmBackend : public X86AsmBackend {
375 WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
376 : X86AsmBackend(T, CPU)
380 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
381 return createX86WinCOFFObjectWriter(OS, Is64Bit);
385 class DarwinX86AsmBackend : public X86AsmBackend {
387 DarwinX86AsmBackend(const Target &T, StringRef CPU)
388 : X86AsmBackend(T, CPU) { }
391 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
393 DarwinX86_32AsmBackend(const Target &T, StringRef CPU)
394 : DarwinX86AsmBackend(T, CPU) {}
396 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
397 return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
398 object::mach::CTM_i386,
399 object::mach::CSX86_ALL);
403 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
405 DarwinX86_64AsmBackend(const Target &T, StringRef CPU)
406 : DarwinX86AsmBackend(T, CPU) {
407 HasReliableSymbolDifference = true;
410 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
411 return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
412 object::mach::CTM_x86_64,
413 object::mach::CSX86_ALL);
416 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
417 // Temporary labels in the string literals sections require symbols. The
418 // issue is that the x86_64 relocation format does not allow symbol +
419 // offset, and so the linker does not have enough information to resolve the
420 // access to the appropriate atom unless an external relocation is used. For
421 // non-cstring sections, we expect the compiler to use a non-temporary label
422 // for anything that could have an addend pointing outside the symbol.
424 // See <rdar://problem/4765733>.
425 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
426 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
429 virtual bool isSectionAtomizable(const MCSection &Section) const {
430 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
431 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
432 switch (SMO.getType()) {
436 case MCSectionMachO::S_4BYTE_LITERALS:
437 case MCSectionMachO::S_8BYTE_LITERALS:
438 case MCSectionMachO::S_16BYTE_LITERALS:
439 case MCSectionMachO::S_LITERAL_POINTERS:
440 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
441 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
442 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
443 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
444 case MCSectionMachO::S_INTERPOSING:
450 } // end anonymous namespace
452 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, StringRef TT, StringRef CPU) {
453 Triple TheTriple(TT);
455 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
456 return new DarwinX86_32AsmBackend(T, CPU);
458 if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
459 return new WindowsX86AsmBackend(T, false, CPU);
461 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
462 return new ELFX86_32AsmBackend(T, OSABI, CPU);
465 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, StringRef TT, StringRef CPU) {
466 Triple TheTriple(TT);
468 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
469 return new DarwinX86_64AsmBackend(T, CPU);
471 if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
472 return new WindowsX86AsmBackend(T, true, CPU);
474 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
475 return new ELFX86_64AsmBackend(T, OSABI, CPU);