1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCAsmBackend.h"
11 #include "MCTargetDesc/X86BaseInfo.h"
12 #include "MCTargetDesc/X86FixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCELFObjectWriter.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCFixupKindInfo.h"
18 #include "llvm/MC/MCMachObjectWriter.h"
19 #include "llvm/MC/MCObjectWriter.h"
20 #include "llvm/MC/MCSectionCOFF.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSectionMachO.h"
23 #include "llvm/Object/MachOFormat.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/ELF.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/Target/TargetRegistry.h"
31 // Option to allow disabling arithmetic relaxation to workaround PR9807, which
32 // is useful when running bitwise comparison experiments on Darwin. We should be
33 // able to remove this once PR9807 is resolved.
35 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
36 cl::desc("Disable relaxation of arithmetic instruction for X86"));
38 static unsigned getFixupKindLog2Size(unsigned Kind) {
40 default: assert(0 && "invalid fixup kind!");
42 case FK_Data_1: return 0;
44 case FK_Data_2: return 1;
46 case X86::reloc_riprel_4byte:
47 case X86::reloc_riprel_4byte_movq_load:
48 case X86::reloc_signed_4byte:
49 case X86::reloc_global_offset_table:
50 case FK_Data_4: return 2;
52 case FK_Data_8: return 3;
58 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
60 X86ELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine,
61 bool HasRelocationAddend)
62 : MCELFObjectTargetWriter(is64Bit, OSType, EMachine, HasRelocationAddend) {}
65 class X86AsmBackend : public MCAsmBackend {
67 X86AsmBackend(const Target &T)
70 unsigned getNumFixupKinds() const {
71 return X86::NumTargetFixupKinds;
74 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
75 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
76 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
77 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
78 { "reloc_signed_4byte", 0, 4 * 8, 0},
79 { "reloc_global_offset_table", 0, 4 * 8, 0}
82 if (Kind < FirstTargetFixupKind)
83 return MCAsmBackend::getFixupKindInfo(Kind);
85 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
87 return Infos[Kind - FirstTargetFixupKind];
90 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
91 uint64_t Value) const {
92 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
94 assert(Fixup.getOffset() + Size <= DataSize &&
95 "Invalid fixup offset!");
97 // Check that uppper bits are either all zeros or all ones.
98 // Specifically ignore overflow/underflow as long as the leakage is
99 // limited to the lower bits. This is to remain compatible with
102 const uint64_t Mask = ~0ULL;
103 const uint64_t UpperV = (Value >> (Size * 8));
104 const uint64_t MaskF = (Mask >> (Size * 8));
107 assert(((Size == 8) ||
108 ((UpperV & MaskF) == 0ULL) || ((UpperV & MaskF) == MaskF)) &&
109 "Value does not fit in the Fixup field");
111 for (unsigned i = 0; i != Size; ++i)
112 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
115 bool MayNeedRelaxation(const MCInst &Inst) const;
117 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
119 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
121 } // end anonymous namespace
123 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
128 case X86::JAE_1: return X86::JAE_4;
129 case X86::JA_1: return X86::JA_4;
130 case X86::JBE_1: return X86::JBE_4;
131 case X86::JB_1: return X86::JB_4;
132 case X86::JE_1: return X86::JE_4;
133 case X86::JGE_1: return X86::JGE_4;
134 case X86::JG_1: return X86::JG_4;
135 case X86::JLE_1: return X86::JLE_4;
136 case X86::JL_1: return X86::JL_4;
137 case X86::JMP_1: return X86::JMP_4;
138 case X86::JNE_1: return X86::JNE_4;
139 case X86::JNO_1: return X86::JNO_4;
140 case X86::JNP_1: return X86::JNP_4;
141 case X86::JNS_1: return X86::JNS_4;
142 case X86::JO_1: return X86::JO_4;
143 case X86::JP_1: return X86::JP_4;
144 case X86::JS_1: return X86::JS_4;
148 static unsigned getRelaxedOpcodeArith(unsigned Op) {
154 case X86::IMUL16rri8: return X86::IMUL16rri;
155 case X86::IMUL16rmi8: return X86::IMUL16rmi;
156 case X86::IMUL32rri8: return X86::IMUL32rri;
157 case X86::IMUL32rmi8: return X86::IMUL32rmi;
158 case X86::IMUL64rri8: return X86::IMUL64rri32;
159 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
162 case X86::AND16ri8: return X86::AND16ri;
163 case X86::AND16mi8: return X86::AND16mi;
164 case X86::AND32ri8: return X86::AND32ri;
165 case X86::AND32mi8: return X86::AND32mi;
166 case X86::AND64ri8: return X86::AND64ri32;
167 case X86::AND64mi8: return X86::AND64mi32;
170 case X86::OR16ri8: return X86::OR16ri;
171 case X86::OR16mi8: return X86::OR16mi;
172 case X86::OR32ri8: return X86::OR32ri;
173 case X86::OR32mi8: return X86::OR32mi;
174 case X86::OR64ri8: return X86::OR64ri32;
175 case X86::OR64mi8: return X86::OR64mi32;
178 case X86::XOR16ri8: return X86::XOR16ri;
179 case X86::XOR16mi8: return X86::XOR16mi;
180 case X86::XOR32ri8: return X86::XOR32ri;
181 case X86::XOR32mi8: return X86::XOR32mi;
182 case X86::XOR64ri8: return X86::XOR64ri32;
183 case X86::XOR64mi8: return X86::XOR64mi32;
186 case X86::ADD16ri8: return X86::ADD16ri;
187 case X86::ADD16mi8: return X86::ADD16mi;
188 case X86::ADD32ri8: return X86::ADD32ri;
189 case X86::ADD32mi8: return X86::ADD32mi;
190 case X86::ADD64ri8: return X86::ADD64ri32;
191 case X86::ADD64mi8: return X86::ADD64mi32;
194 case X86::SUB16ri8: return X86::SUB16ri;
195 case X86::SUB16mi8: return X86::SUB16mi;
196 case X86::SUB32ri8: return X86::SUB32ri;
197 case X86::SUB32mi8: return X86::SUB32mi;
198 case X86::SUB64ri8: return X86::SUB64ri32;
199 case X86::SUB64mi8: return X86::SUB64mi32;
202 case X86::CMP16ri8: return X86::CMP16ri;
203 case X86::CMP16mi8: return X86::CMP16mi;
204 case X86::CMP32ri8: return X86::CMP32ri;
205 case X86::CMP32mi8: return X86::CMP32mi;
206 case X86::CMP64ri8: return X86::CMP64ri32;
207 case X86::CMP64mi8: return X86::CMP64mi32;
210 case X86::PUSHi8: return X86::PUSHi32;
211 case X86::PUSHi16: return X86::PUSHi32;
212 case X86::PUSH64i8: return X86::PUSH64i32;
213 case X86::PUSH64i16: return X86::PUSH64i32;
217 static unsigned getRelaxedOpcode(unsigned Op) {
218 unsigned R = getRelaxedOpcodeArith(Op);
221 return getRelaxedOpcodeBranch(Op);
224 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
225 // Branches can always be relaxed.
226 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
229 if (MCDisableArithRelaxation)
232 // Check if this instruction is ever relaxable.
233 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
237 // Check if it has an expression and is not RIP relative.
240 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
241 const MCOperand &Op = Inst.getOperand(i);
245 if (Op.isReg() && Op.getReg() == X86::RIP)
249 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
250 // how we do relaxations?
251 return hasExp && !hasRIP;
254 // FIXME: Can tblgen help at all here to verify there aren't other instructions
256 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
257 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
258 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
260 if (RelaxedOp == Inst.getOpcode()) {
261 SmallString<256> Tmp;
262 raw_svector_ostream OS(Tmp);
263 Inst.dump_pretty(OS);
265 report_fatal_error("unexpected instruction to relax: " + OS.str());
269 Res.setOpcode(RelaxedOp);
272 /// WriteNopData - Write optimal nops to the output file for the \arg Count
273 /// bytes. This returns the number of bytes written. It may return 0 if
274 /// the \arg Count is more than the maximum optimal nops.
275 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
276 static const uint8_t Nops[10][10] = {
284 {0x0f, 0x1f, 0x40, 0x00},
285 // nopl 0(%[re]ax,%[re]ax,1)
286 {0x0f, 0x1f, 0x44, 0x00, 0x00},
287 // nopw 0(%[re]ax,%[re]ax,1)
288 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
290 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
291 // nopl 0L(%[re]ax,%[re]ax,1)
292 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
293 // nopw 0L(%[re]ax,%[re]ax,1)
294 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
295 // nopw %cs:0L(%[re]ax,%[re]ax,1)
296 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
299 // Write an optimal sequence for the first 15 bytes.
300 const uint64_t OptimalCount = (Count < 16) ? Count : 15;
301 const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10;
302 for (uint64_t i = 0, e = Prefixes; i != e; i++)
304 const uint64_t Rest = OptimalCount - Prefixes;
305 for (uint64_t i = 0, e = Rest; i != e; i++)
306 OW->Write8(Nops[Rest - 1][i]);
308 // Finish with single byte nops.
309 for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
318 class ELFX86AsmBackend : public X86AsmBackend {
320 Triple::OSType OSType;
321 ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
322 : X86AsmBackend(T), OSType(_OSType) {
323 HasReliableSymbolDifference = true;
326 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
327 const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
328 return ES.getFlags() & ELF::SHF_MERGE;
332 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
334 ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
335 : ELFX86AsmBackend(T, OSType) {}
337 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
338 return createELFObjectWriter(createELFObjectTargetWriter(),
339 OS, /*IsLittleEndian*/ true);
342 MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
343 return new X86ELFObjectWriter(false, OSType, ELF::EM_386, false);
347 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
349 ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
350 : ELFX86AsmBackend(T, OSType) {}
352 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
353 return createELFObjectWriter(createELFObjectTargetWriter(),
354 OS, /*IsLittleEndian*/ true);
357 MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
358 return new X86ELFObjectWriter(true, OSType, ELF::EM_X86_64, true);
362 class WindowsX86AsmBackend : public X86AsmBackend {
366 WindowsX86AsmBackend(const Target &T, bool is64Bit)
371 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
372 return createWinCOFFObjectWriter(OS, Is64Bit);
376 class DarwinX86AsmBackend : public X86AsmBackend {
378 DarwinX86AsmBackend(const Target &T)
379 : X86AsmBackend(T) { }
382 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
384 DarwinX86_32AsmBackend(const Target &T)
385 : DarwinX86AsmBackend(T) {}
387 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
388 return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
389 object::mach::CTM_i386,
390 object::mach::CSX86_ALL);
394 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
396 DarwinX86_64AsmBackend(const Target &T)
397 : DarwinX86AsmBackend(T) {
398 HasReliableSymbolDifference = true;
401 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
402 return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
403 object::mach::CTM_x86_64,
404 object::mach::CSX86_ALL);
407 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
408 // Temporary labels in the string literals sections require symbols. The
409 // issue is that the x86_64 relocation format does not allow symbol +
410 // offset, and so the linker does not have enough information to resolve the
411 // access to the appropriate atom unless an external relocation is used. For
412 // non-cstring sections, we expect the compiler to use a non-temporary label
413 // for anything that could have an addend pointing outside the symbol.
415 // See <rdar://problem/4765733>.
416 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
417 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
420 virtual bool isSectionAtomizable(const MCSection &Section) const {
421 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
422 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
423 switch (SMO.getType()) {
427 case MCSectionMachO::S_4BYTE_LITERALS:
428 case MCSectionMachO::S_8BYTE_LITERALS:
429 case MCSectionMachO::S_16BYTE_LITERALS:
430 case MCSectionMachO::S_LITERAL_POINTERS:
431 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
432 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
433 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
434 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
435 case MCSectionMachO::S_INTERPOSING:
441 } // end anonymous namespace
443 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, StringRef TT) {
444 Triple TheTriple(TT);
446 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
447 return new DarwinX86_32AsmBackend(T);
449 if (TheTriple.isOSWindows())
450 return new WindowsX86AsmBackend(T, false);
452 return new ELFX86_32AsmBackend(T, TheTriple.getOS());
455 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, StringRef TT) {
456 Triple TheTriple(TT);
458 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
459 return new DarwinX86_64AsmBackend(T);
461 if (TheTriple.isOSWindows())
462 return new WindowsX86AsmBackend(T, true);
464 return new ELFX86_64AsmBackend(T, TheTriple.getOS());