1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains small standalone helper functions and enum definitions for
11 // the X86 target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
15 //===----------------------------------------------------------------------===//
20 #include "X86MCTargetDesc.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/Support/DataTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
28 // Enums for memory operand decoding. Each memory operand is represented with
29 // a 5 operand sequence in the form:
30 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
31 // These enums help decode this.
38 /// AddrSegmentReg - The operand # of the segment in the memory operand.
41 /// AddrNumOperands - Total number of operands in a memory reference.
44 } // end namespace X86;
46 /// X86II - This namespace holds all of the target specific flags that
47 /// instruction info tracks.
50 /// Target Operand Flag enum.
52 //===------------------------------------------------------------------===//
53 // X86 Specific MachineOperand flags.
57 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
59 /// SYMBOL_LABEL + [. - PICBASELABEL]
60 MO_GOT_ABSOLUTE_ADDRESS,
62 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
63 /// immediate should get the value of the symbol minus the PIC base label:
64 /// SYMBOL_LABEL - PICBASELABEL
67 /// MO_GOT - On a symbol operand this indicates that the immediate is the
68 /// offset to the GOT entry for the symbol name from the base of the GOT.
70 /// See the X86-64 ELF ABI supplement for more details.
74 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
75 /// the offset to the location of the symbol name from the base of the GOT.
77 /// See the X86-64 ELF ABI supplement for more details.
78 /// SYMBOL_LABEL @GOTOFF
81 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
82 /// offset to the GOT entry for the symbol name from the current code
85 /// See the X86-64 ELF ABI supplement for more details.
86 /// SYMBOL_LABEL @GOTPCREL
89 /// MO_PLT - On a symbol operand this indicates that the immediate is
90 /// offset to the PLT entry of symbol name from the current code location.
92 /// See the X86-64 ELF ABI supplement for more details.
96 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
97 /// the offset of the GOT entry with the TLS index structure that contains
98 /// the module number and variable offset for the symbol. Used in the
99 /// general dynamic TLS access model.
101 /// See 'ELF Handling for Thread-Local Storage' for more details.
102 /// SYMBOL_LABEL @TLSGD
105 /// MO_TLSLD - On a symbol operand this indicates that the immediate is
106 /// the offset of the GOT entry with the TLS index for the module that
107 /// contains the symbol. When this index is passed to a call to
108 /// __tls_get_addr, the function will return the base address of the TLS
109 /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
111 /// See 'ELF Handling for Thread-Local Storage' for more details.
112 /// SYMBOL_LABEL @TLSLD
115 /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
116 /// the offset of the GOT entry with the TLS index for the module that
117 /// contains the symbol. When this index is passed to a call to
118 /// ___tls_get_addr, the function will return the base address of the TLS
119 /// block for the symbol. Used in the IA32 local dynamic TLS access model.
121 /// See 'ELF Handling for Thread-Local Storage' for more details.
122 /// SYMBOL_LABEL @TLSLDM
125 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
126 /// the offset of the GOT entry with the thread-pointer offset for the
127 /// symbol. Used in the x86-64 initial exec TLS access model.
129 /// See 'ELF Handling for Thread-Local Storage' for more details.
130 /// SYMBOL_LABEL @GOTTPOFF
133 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
134 /// the absolute address of the GOT entry with the negative thread-pointer
135 /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
138 /// See 'ELF Handling for Thread-Local Storage' for more details.
139 /// SYMBOL_LABEL @INDNTPOFF
142 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
143 /// the thread-pointer offset for the symbol. Used in the x86-64 local
144 /// exec TLS access model.
146 /// See 'ELF Handling for Thread-Local Storage' for more details.
147 /// SYMBOL_LABEL @TPOFF
150 /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
151 /// the offset of the GOT entry with the TLS offset of the symbol. Used
152 /// in the local dynamic TLS access model.
154 /// See 'ELF Handling for Thread-Local Storage' for more details.
155 /// SYMBOL_LABEL @DTPOFF
158 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
159 /// the negative thread-pointer offset for the symbol. Used in the IA32
160 /// local exec TLS access model.
162 /// See 'ELF Handling for Thread-Local Storage' for more details.
163 /// SYMBOL_LABEL @NTPOFF
166 /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
167 /// the offset of the GOT entry with the negative thread-pointer offset for
168 /// the symbol. Used in the PIC IA32 initial exec TLS access model.
170 /// See 'ELF Handling for Thread-Local Storage' for more details.
171 /// SYMBOL_LABEL @GOTNTPOFF
174 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
175 /// reference is actually to the "__imp_FOO" symbol. This is used for
176 /// dllimport linkage on windows.
179 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
180 /// reference is actually to the "FOO$stub" symbol. This is used for calls
181 /// and jumps to external functions on Tiger and earlier.
184 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
185 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
186 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
189 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
190 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
191 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
192 MO_DARWIN_NONLAZY_PIC_BASE,
194 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
195 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
196 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer
198 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE,
200 /// MO_TLVP - On a symbol operand this indicates that the immediate is
203 /// This is the TLS offset for the Darwin TLS mechanism.
206 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
207 /// is some TLS offset from the picbase.
209 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
212 /// MO_SECREL - On a symbol operand this indicates that the immediate is
213 /// the offset from beginning of section.
215 /// This is the TLS offset for the COFF/Windows TLS mechanism.
220 //===------------------------------------------------------------------===//
221 // Instruction encodings. These are the standard/most common forms for X86
225 // PseudoFrm - This represents an instruction that is a pseudo instruction
226 // or one that has not been implemented yet. It is illegal to code generate
227 // it, but tolerated for intermediate implementation stages.
230 /// Raw - This form is for instructions that don't have any operands, so
231 /// they are just a fixed opcode value, like 'leave'.
234 /// AddRegFrm - This form is used for instructions like 'push r32' that have
235 /// their one register operand added to their opcode.
238 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
239 /// to specify a destination, which in this case is a register.
243 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
244 /// to specify a destination, which in this case is memory.
248 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
249 /// to specify a source, which in this case is a register.
253 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
254 /// to specify a source, which in this case is memory.
258 /// RawFrmMemOffs - This form is for instructions that store an absolute
259 /// memory offset as an immediate with a possible segment override.
262 /// RawFrmSrc - This form is for instructions that use the source index
263 /// register SI/ESI/RSI with a possible segment override.
266 /// MRM[0-7][rm] - These forms are used to represent instructions that use
267 /// a Mod/RM byte, and use the middle field to hold extended opcode
268 /// information. In the intel manual these are represented as /0, /1, ...
271 // First, instructions that operate on a register r/m operand...
272 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
273 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
275 // Next, instructions that operate on a memory r/m operand...
276 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
277 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
279 //// MRM_XX - A mod/rm byte of exactly 0xXX.
280 MRM_C1 = 33, MRM_C2 = 34, MRM_C3 = 35, MRM_C4 = 36,
281 MRM_C8 = 37, MRM_C9 = 38, MRM_CA = 39, MRM_CB = 40,
282 MRM_E8 = 41, MRM_F0 = 42, MRM_F8 = 45, MRM_F9 = 46,
283 MRM_D0 = 47, MRM_D1 = 48, MRM_D4 = 49, MRM_D5 = 50,
284 MRM_D6 = 51, MRM_D8 = 52, MRM_D9 = 53, MRM_DA = 54,
285 MRM_DB = 55, MRM_DC = 56, MRM_DD = 57, MRM_DE = 58,
288 /// RawFrmImm8 - This is used for the ENTER instruction, which has two
289 /// immediates, the first of which is a 16-bit immediate (specified by
290 /// the imm encoding) and the second is a 8-bit fixed value.
293 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
294 /// immediates, the first of which is a 16 or 32-bit immediate (specified by
295 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
296 /// manual, this operand is described as pntr16:32 and pntr16:16
301 //===------------------------------------------------------------------===//
304 // OpSize - Set if this instruction requires an operand size prefix (0x66),
305 // which most often indicates that the instruction operates on 16 bit data
306 // instead of 32 bit data. OpSize16 in 16 bit mode indicates that the
307 // instruction operates on 32 bit data instead of 16 bit data.
311 // AsSize - Set if this instruction requires an operand size prefix (0x67),
312 // which most often indicates that the instruction address 16 bit address
313 // instead of 32 bit address (or 32 bit address in 64 bit mode).
316 //===------------------------------------------------------------------===//
317 // Op0Mask - There are several prefix bytes that are used to form two byte
318 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
319 // used to obtain the setting of this field. If no bits in this field is
320 // set, there is no prefix byte for obtaining a multibyte opcode.
323 Op0Mask = 0x1F << Op0Shift,
325 // TB - TwoByte - Set if this instruction has a two byte opcode, which
326 // starts with a 0x0F byte before the real opcode.
329 // REP - The 0xF3 prefix byte indicating repetition of the following
333 // D8-DF - These escape opcodes are used by the floating point unit. These
334 // values must remain sequential.
335 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
336 DA = 5 << Op0Shift, DB = 6 << Op0Shift,
337 DC = 7 << Op0Shift, DD = 8 << Op0Shift,
338 DE = 9 << Op0Shift, DF = 10 << Op0Shift,
340 // XS, XD - These prefix codes are for single and double precision scalar
341 // floating point operations performed in the SSE registers.
342 XD = 11 << Op0Shift, XS = 12 << Op0Shift,
344 // T8, TA, A6, A7 - Prefix after the 0x0F prefix.
345 T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
346 A6 = 15 << Op0Shift, A7 = 16 << Op0Shift,
348 // T8XD - Prefix before and after 0x0F. Combination of T8 and XD.
349 T8XD = 17 << Op0Shift,
351 // T8XS - Prefix before and after 0x0F. Combination of T8 and XS.
352 T8XS = 18 << Op0Shift,
354 // TAXD - Prefix before and after 0x0F. Combination of TA and XD.
355 TAXD = 19 << Op0Shift,
357 // XOP8 - Prefix to include use of imm byte.
358 XOP8 = 20 << Op0Shift,
360 // XOP9 - Prefix to exclude use of imm byte.
361 XOP9 = 21 << Op0Shift,
363 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
364 XOPA = 22 << Op0Shift,
366 // PD - Prefix code for packed double precision vector floating point
367 // operations performed in the SSE registers.
370 // T8PD - Prefix before and after 0x0F. Combination of T8 and PD.
371 T8PD = 24 << Op0Shift,
373 // TAPD - Prefix before and after 0x0F. Combination of TA and PD.
374 TAPD = 25 << Op0Shift,
376 //===------------------------------------------------------------------===//
377 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
378 // They are used to specify GPRs and SSE registers, 64-bit operand size,
379 // etc. We only cares about REX.W and REX.R bits and only the former is
380 // statically determined.
382 REXShift = Op0Shift + 5,
383 REX_W = 1 << REXShift,
385 //===------------------------------------------------------------------===//
386 // This three-bit field describes the size of an immediate operand. Zero is
387 // unused so that we can tell if we forgot to set a value.
388 ImmShift = REXShift + 1,
389 ImmMask = 7 << ImmShift,
390 Imm8 = 1 << ImmShift,
391 Imm8PCRel = 2 << ImmShift,
392 Imm16 = 3 << ImmShift,
393 Imm16PCRel = 4 << ImmShift,
394 Imm32 = 5 << ImmShift,
395 Imm32PCRel = 6 << ImmShift,
396 Imm64 = 7 << ImmShift,
398 //===------------------------------------------------------------------===//
399 // FP Instruction Classification... Zero is non-fp instruction.
401 // FPTypeMask - Mask for all of the FP types...
402 FPTypeShift = ImmShift + 3,
403 FPTypeMask = 7 << FPTypeShift,
405 // NotFP - The default, set for instructions that do not use FP registers.
406 NotFP = 0 << FPTypeShift,
408 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
409 ZeroArgFP = 1 << FPTypeShift,
411 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
412 OneArgFP = 2 << FPTypeShift,
414 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
415 // result back to ST(0). For example, fcos, fsqrt, etc.
417 OneArgFPRW = 3 << FPTypeShift,
419 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
420 // explicit argument, storing the result to either ST(0) or the implicit
421 // argument. For example: fadd, fsub, fmul, etc...
422 TwoArgFP = 4 << FPTypeShift,
424 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
425 // explicit argument, but have no destination. Example: fucom, fucomi, ...
426 CompareFP = 5 << FPTypeShift,
428 // CondMovFP - "2 operand" floating point conditional move instructions.
429 CondMovFP = 6 << FPTypeShift,
431 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
432 SpecialFP = 7 << FPTypeShift,
435 LOCKShift = FPTypeShift + 3,
436 LOCK = 1 << LOCKShift,
438 // Execution domain for SSE instructions in bits 23, 24.
439 // 0 in bits 23-24 means normal, non-SSE instruction.
440 SSEDomainShift = LOCKShift + 1,
442 OpcodeShift = SSEDomainShift + 2,
444 //===------------------------------------------------------------------===//
445 /// VEX - The opcode prefix used by AVX instructions
446 VEXShift = OpcodeShift + 8,
449 /// VEX_W - Has a opcode specific functionality, but is used in the same
450 /// way as REX_W is for regular SSE instructions.
453 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
454 /// address instructions in SSE are represented as 3 address ones in AVX
455 /// and the additional register is encoded in VEX_VVVV prefix.
458 /// VEX_4VOp3 - Similar to VEX_4V, but used on instructions that encode
459 /// operand 3 with VEX.vvvv.
462 /// VEX_I8IMM - Specifies that the last register used in a AVX instruction,
463 /// must be encoded in the i8 immediate field. This usually happens in
464 /// instructions with 4 operands.
467 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
468 /// instruction uses 256-bit wide registers. This is usually auto detected
469 /// if a VR256 register is used, but some AVX instructions also have this
470 /// field marked when using a f256 memory references.
473 // VEX_LIG - Specifies that this instruction ignores the L-bit in the VEX
474 // prefix. Usually used for scalar instructions. Needed by disassembler.
477 // TODO: we should combine VEX_L and VEX_LIG together to form a 2-bit field
478 // with following encoding:
482 // - 11 LIG (but, in insn encoding, leave VEX.L and EVEX.L in zeros.
483 // this will save 1 tsflag bit
485 // VEX_EVEX - Specifies that this instruction use EVEX form which provides
486 // syntax support up to 32 512-bit register operands and up to 7 16-bit
487 // mask operands as well as source operand data swizzling/memory operand
488 // conversion, eviction hint, and rounding mode.
491 // EVEX_K - Set if this instruction requires masking
494 // EVEX_Z - Set if this instruction has EVEX.Z field set.
497 // EVEX_L2 - Set if this instruction has EVEX.L' field set.
500 // EVEX_B - Set if this instruction has EVEX.B field set.
503 // EVEX_CD8E - compressed disp8 form, element-size
504 EVEX_CD8EShift = VEXShift + 12,
507 // EVEX_CD8V - compressed disp8 form, vector-width
508 EVEX_CD8VShift = EVEX_CD8EShift + 2,
511 /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the
512 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
513 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
514 /// storing a classifier in the imm8 field. To simplify our implementation,
515 /// we handle this by storeing the classifier in the opcode field and using
516 /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
517 Has3DNow0F0FOpcode = 1U << 17,
519 /// MemOp4 - Used to indicate swapping of operand 3 and 4 to be encoded in
520 /// ModRM or I8IMM. This is used for FMA4 and XOP instructions.
523 /// XOP - Opcode prefix used by XOP instructions.
526 /// Explicitly specified rounding control
530 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
531 // specified machine instruction.
533 inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
534 return TSFlags >> X86II::OpcodeShift;
537 inline bool hasImm(uint64_t TSFlags) {
538 return (TSFlags & X86II::ImmMask) != 0;
541 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
542 /// of the specified instruction.
543 inline unsigned getSizeOfImm(uint64_t TSFlags) {
544 switch (TSFlags & X86II::ImmMask) {
545 default: llvm_unreachable("Unknown immediate size");
547 case X86II::Imm8PCRel: return 1;
549 case X86II::Imm16PCRel: return 2;
551 case X86II::Imm32PCRel: return 4;
552 case X86II::Imm64: return 8;
556 /// isImmPCRel - Return true if the immediate of the specified instruction's
557 /// TSFlags indicates that it is pc relative.
558 inline unsigned isImmPCRel(uint64_t TSFlags) {
559 switch (TSFlags & X86II::ImmMask) {
560 default: llvm_unreachable("Unknown immediate size");
561 case X86II::Imm8PCRel:
562 case X86II::Imm16PCRel:
563 case X86II::Imm32PCRel:
573 /// getOperandBias - compute any additional adjustment needed to
574 /// the offset to the start of the memory operand
575 /// in this instruction.
576 /// If this is a two-address instruction,skip one of the register operands.
577 /// FIXME: This should be handled during MCInst lowering.
578 inline int getOperandBias(const MCInstrDesc& Desc)
580 unsigned NumOps = Desc.getNumOperands();
582 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
584 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
585 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
586 // Special case for AVX-512 GATHER with 2 TIED_TO operands
587 // Skip the first 2 operands: dst, mask_wb
589 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
590 Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1)
591 // Special case for GATHER with 2 TIED_TO operands
592 // Skip the first 2 operands: dst, mask_wb
594 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0)
600 /// getMemoryOperandNo - The function returns the MCInst operand # for the
601 /// first field of the memory operand. If the instruction doesn't have a
602 /// memory operand, this returns -1.
604 /// Note that this ignores tied operands. If there is a tied register which
605 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
606 /// counted as one operand.
608 inline int getMemoryOperandNo(uint64_t TSFlags, unsigned Opcode) {
609 switch (TSFlags & X86II::FormMask) {
610 default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
613 case X86II::AddRegFrm:
614 case X86II::MRMDestReg:
615 case X86II::MRMSrcReg:
616 case X86II::RawFrmImm8:
617 case X86II::RawFrmImm16:
618 case X86II::RawFrmMemOffs:
619 case X86II::RawFrmSrc:
621 case X86II::MRMDestMem:
623 case X86II::MRMSrcMem: {
624 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
625 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
626 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
627 bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
628 unsigned FirstMemOp = 1;
630 ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
632 ++FirstMemOp;// Skip the register source (which is encoded in I8IMM).
634 ++FirstMemOp;// Skip the mask register
635 // FIXME: Maybe lea should have its own form? This is a horrible hack.
636 //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
637 // Opcode == X86::LEA16r || Opcode == X86::LEA32r)
640 case X86II::MRM0r: case X86II::MRM1r:
641 case X86II::MRM2r: case X86II::MRM3r:
642 case X86II::MRM4r: case X86II::MRM5r:
643 case X86II::MRM6r: case X86II::MRM7r:
645 case X86II::MRM0m: case X86II::MRM1m:
646 case X86II::MRM2m: case X86II::MRM3m:
647 case X86II::MRM4m: case X86II::MRM5m:
648 case X86II::MRM6m: case X86II::MRM7m: {
649 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
650 unsigned FirstMemOp = 0;
652 ++FirstMemOp;// Skip the register dest (which is encoded in VEX_VVVV).
655 case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3:
656 case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9:
657 case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_E8:
658 case X86II::MRM_F0: case X86II::MRM_F8: case X86II::MRM_F9:
659 case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4:
660 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8:
661 case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB:
662 case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE:
668 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
669 /// higher) register? e.g. r8, xmm8, xmm13, etc.
670 inline bool isX86_64ExtendedReg(unsigned RegNo) {
671 if ((RegNo > X86::XMM7 && RegNo <= X86::XMM15) ||
672 (RegNo > X86::XMM23 && RegNo <= X86::XMM31) ||
673 (RegNo > X86::YMM7 && RegNo <= X86::YMM15) ||
674 (RegNo > X86::YMM23 && RegNo <= X86::YMM31) ||
675 (RegNo > X86::ZMM7 && RegNo <= X86::ZMM15) ||
676 (RegNo > X86::ZMM23 && RegNo <= X86::ZMM31))
681 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
682 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
683 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
684 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
685 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
686 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
687 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
688 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
689 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
690 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
696 /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher)
697 /// registers? e.g. zmm21, etc.
698 static inline bool is32ExtendedReg(unsigned RegNo) {
699 return ((RegNo > X86::XMM15 && RegNo <= X86::XMM31) ||
700 (RegNo > X86::YMM15 && RegNo <= X86::YMM31) ||
701 (RegNo > X86::ZMM15 && RegNo <= X86::ZMM31));
705 inline bool isX86_64NonExtLowByteReg(unsigned reg) {
706 return (reg == X86::SPL || reg == X86::BPL ||
707 reg == X86::SIL || reg == X86::DIL);
711 } // end namespace llvm;