1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/X86MCTargetDesc.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "MCTargetDesc/X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCSymbol.h"
26 #include "llvm/Support/raw_ostream.h"
31 class X86MCCodeEmitter : public MCCodeEmitter {
32 X86MCCodeEmitter(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION;
33 void operator=(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION;
34 const MCInstrInfo &MCII;
37 X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
38 : MCII(mcii), Ctx(ctx) {
41 ~X86MCCodeEmitter() {}
43 bool is64BitMode(const MCSubtargetInfo &STI) const {
44 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
47 bool is32BitMode(const MCSubtargetInfo &STI) const {
48 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
51 bool is16BitMode(const MCSubtargetInfo &STI) const {
52 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
55 /// Is16BitMemOperand - Return true if the specified instruction has
56 /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
57 bool Is16BitMemOperand(const MCInst &MI, unsigned Op,
58 const MCSubtargetInfo &STI) const {
59 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
60 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
61 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
63 if (is16BitMode(STI) && BaseReg.getReg() == 0 &&
64 Disp.isImm() && Disp.getImm() < 0x10000)
66 if ((BaseReg.getReg() != 0 &&
67 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
68 (IndexReg.getReg() != 0 &&
69 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
74 unsigned GetX86RegNum(const MCOperand &MO) const {
75 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
78 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
79 // 0-7 and the difference between the 2 groups is given by the REX prefix.
80 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
81 // in 1's complement form, example:
83 // ModRM field => XMM9 => 1
84 // VEX.VVVV => XMM9 => ~9
86 // See table 4-35 of Intel AVX Programming Reference for details.
87 unsigned char getVEXRegisterEncoding(const MCInst &MI,
88 unsigned OpNum) const {
89 unsigned SrcReg = MI.getOperand(OpNum).getReg();
90 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
91 if (X86II::isX86_64ExtendedReg(SrcReg))
94 // The registers represented through VEX_VVVV should
95 // be encoded in 1's complement form.
96 return (~SrcRegNum) & 0xf;
99 unsigned char getWriteMaskRegisterEncoding(const MCInst &MI,
100 unsigned OpNum) const {
101 assert(X86::K0 != MI.getOperand(OpNum).getReg() &&
102 "Invalid mask register as write-mask!");
103 unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum));
107 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
112 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
113 raw_ostream &OS) const {
114 // Output the constant in little endian byte order.
115 for (unsigned i = 0; i != Size; ++i) {
116 EmitByte(Val & 255, CurByte, OS);
121 void EmitImmediate(const MCOperand &Disp, SMLoc Loc,
122 unsigned ImmSize, MCFixupKind FixupKind,
123 unsigned &CurByte, raw_ostream &OS,
124 SmallVectorImpl<MCFixup> &Fixups,
125 int ImmOffset = 0) const;
127 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
129 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
130 return RM | (RegOpcode << 3) | (Mod << 6);
133 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
134 unsigned &CurByte, raw_ostream &OS) const {
135 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
138 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
139 unsigned &CurByte, raw_ostream &OS) const {
140 // SIB byte is in the same format as the ModRMByte.
141 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
145 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
146 unsigned RegOpcodeField,
147 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
148 SmallVectorImpl<MCFixup> &Fixups,
149 const MCSubtargetInfo &STI) const;
151 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
152 SmallVectorImpl<MCFixup> &Fixups,
153 const MCSubtargetInfo &STI) const;
155 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
156 const MCInst &MI, const MCInstrDesc &Desc,
157 raw_ostream &OS) const;
159 void EmitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand,
160 const MCInst &MI, raw_ostream &OS) const;
162 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
163 const MCInst &MI, const MCInstrDesc &Desc,
164 const MCSubtargetInfo &STI,
165 raw_ostream &OS) const;
168 } // end anonymous namespace
171 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
172 const MCRegisterInfo &MRI,
173 const MCSubtargetInfo &STI,
175 return new X86MCCodeEmitter(MCII, Ctx);
178 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
179 /// sign-extended field.
180 static bool isDisp8(int Value) {
181 return Value == (signed char)Value;
184 /// isCDisp8 - Return true if this signed displacement fits in a 8-bit
185 /// compressed dispacement field.
186 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
187 assert((TSFlags & X86II::EncodingMask) >> X86II::EncodingShift == X86II::EVEX &&
188 "Compressed 8-bit displacement is only valid for EVEX inst.");
190 unsigned CD8E = (TSFlags >> X86II::EVEX_CD8EShift) & X86II::EVEX_CD8EMask;
191 unsigned CD8V = (TSFlags >> X86II::EVEX_CD8VShift) & X86II::EVEX_CD8VMask;
193 if (CD8V == 0 && CD8E == 0) {
195 return isDisp8(Value);
198 unsigned MemObjSize = 1U << CD8E;
200 // Fixed vector length
201 MemObjSize *= 1U << (CD8V & 0x3);
203 // Modified vector length
204 bool EVEX_b = (TSFlags >> X86II::VEXShift) & X86II::EVEX_B;
206 unsigned EVEX_LL = ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) ? 1 : 0;
207 EVEX_LL += ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2) ? 2 : 0;
208 assert(EVEX_LL < 3 && "");
210 unsigned NumElems = (1U << (EVEX_LL + 4)) / MemObjSize;
211 NumElems /= 1U << (CD8V & 0x3);
213 MemObjSize *= NumElems;
217 unsigned MemObjMask = MemObjSize - 1;
218 assert((MemObjSize & MemObjMask) == 0 && "Invalid memory object size.");
220 if (Value & MemObjMask) // Unaligned offset
222 Value /= (int)MemObjSize;
223 bool Ret = (Value == (signed char)Value);
230 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
231 /// in an instruction with the specified TSFlags.
232 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
233 unsigned Size = X86II::getSizeOfImm(TSFlags);
234 bool isPCRel = X86II::isImmPCRel(TSFlags);
236 if (X86II::isImmSigned(TSFlags)) {
238 default: llvm_unreachable("Unsupported signed fixup size!");
239 case 4: return MCFixupKind(X86::reloc_signed_4byte);
242 return MCFixup::getKindForSize(Size, isPCRel);
245 /// Is32BitMemOperand - Return true if the specified instruction has
246 /// a 32-bit memory operand. Op specifies the operand # of the memoperand.
247 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
248 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
249 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
251 if ((BaseReg.getReg() != 0 &&
252 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
253 (IndexReg.getReg() != 0 &&
254 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
259 /// Is64BitMemOperand - Return true if the specified instruction has
260 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
262 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
263 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
264 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
266 if ((BaseReg.getReg() != 0 &&
267 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
268 (IndexReg.getReg() != 0 &&
269 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
275 /// StartsWithGlobalOffsetTable - Check if this expression starts with
276 /// _GLOBAL_OFFSET_TABLE_ and if it is of the form
277 /// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF
278 /// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
279 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
280 /// of a binary expression.
281 enum GlobalOffsetTableExprKind {
286 static GlobalOffsetTableExprKind
287 StartsWithGlobalOffsetTable(const MCExpr *Expr) {
288 const MCExpr *RHS = 0;
289 if (Expr->getKind() == MCExpr::Binary) {
290 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
295 if (Expr->getKind() != MCExpr::SymbolRef)
298 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
299 const MCSymbol &S = Ref->getSymbol();
300 if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
302 if (RHS && RHS->getKind() == MCExpr::SymbolRef)
307 static bool HasSecRelSymbolRef(const MCExpr *Expr) {
308 if (Expr->getKind() == MCExpr::SymbolRef) {
309 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
310 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL;
315 void X86MCCodeEmitter::
316 EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size,
317 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS,
318 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
319 const MCExpr *Expr = NULL;
320 if (DispOp.isImm()) {
321 // If this is a simple integer displacement that doesn't require a
322 // relocation, emit it now.
323 if (FixupKind != FK_PCRel_1 &&
324 FixupKind != FK_PCRel_2 &&
325 FixupKind != FK_PCRel_4) {
326 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
329 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx);
331 Expr = DispOp.getExpr();
334 // If we have an immoffset, add it to the expression.
335 if ((FixupKind == FK_Data_4 ||
336 FixupKind == FK_Data_8 ||
337 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
338 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr);
339 if (Kind != GOT_None) {
340 assert(ImmOffset == 0);
342 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
343 if (Kind == GOT_Normal)
345 } else if (Expr->getKind() == MCExpr::SymbolRef) {
346 if (HasSecRelSymbolRef(Expr)) {
347 FixupKind = MCFixupKind(FK_SecRel_4);
349 } else if (Expr->getKind() == MCExpr::Binary) {
350 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr);
351 if (HasSecRelSymbolRef(Bin->getLHS())
352 || HasSecRelSymbolRef(Bin->getRHS())) {
353 FixupKind = MCFixupKind(FK_SecRel_4);
358 // If the fixup is pc-relative, we need to bias the value to be relative to
359 // the start of the field, not the end of the field.
360 if (FixupKind == FK_PCRel_4 ||
361 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
362 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
364 if (FixupKind == FK_PCRel_2)
366 if (FixupKind == FK_PCRel_1)
370 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
373 // Emit a symbolic constant as a fixup and 4 zeros.
374 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc));
375 EmitConstant(0, Size, CurByte, OS);
378 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
379 unsigned RegOpcodeField,
380 uint64_t TSFlags, unsigned &CurByte,
382 SmallVectorImpl<MCFixup> &Fixups,
383 const MCSubtargetInfo &STI) const{
384 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
385 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
386 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
387 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
388 unsigned BaseReg = Base.getReg();
389 unsigned char Encoding = (TSFlags & X86II::EncodingMask) >>
390 X86II::EncodingShift;
391 bool HasEVEX = (Encoding == X86II::EVEX);
393 // Handle %rip relative addressing.
394 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
395 assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode");
396 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
397 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
399 unsigned FixupKind = X86::reloc_riprel_4byte;
401 // movq loads are handled with a special relocation form which allows the
402 // linker to eliminate some loads for GOT references which end up in the
403 // same linkage unit.
404 if (MI.getOpcode() == X86::MOV64rm)
405 FixupKind = X86::reloc_riprel_4byte_movq_load;
407 // rip-relative addressing is actually relative to the *next* instruction.
408 // Since an immediate can follow the mod/rm byte for an instruction, this
409 // means that we need to bias the immediate field of the instruction with
410 // the size of the immediate field. If we have this case, add it into the
411 // expression to emit.
412 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
414 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind),
415 CurByte, OS, Fixups, -ImmSize);
419 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
421 // 16-bit addressing forms of the ModR/M byte have a different encoding for
422 // the R/M field and are far more limited in which registers can be used.
423 if (Is16BitMemOperand(MI, Op, STI)) {
425 // For 32-bit addressing, the row and column values in Table 2-2 are
426 // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
427 // some special cases. And GetX86RegNum reflects that numbering.
428 // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
429 // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
430 // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
431 // while values 0-3 indicate the allowed combinations (base+index) of
432 // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
434 // R16Table[] is a lookup from the normal RegNo, to the row values from
435 // Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
436 static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 };
437 unsigned RMfield = R16Table[BaseRegNo];
439 assert(RMfield && "invalid 16-bit base register");
441 if (IndexReg.getReg()) {
442 unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)];
444 assert(IndexReg16 && "invalid 16-bit index register");
445 // We must have one of SI/DI (4,5), and one of BP/BX (6,7).
446 assert(((IndexReg16 ^ RMfield) & 2) &&
447 "invalid 16-bit base/index register combination");
448 assert(Scale.getImm() == 1 &&
449 "invalid scale for 16-bit memory reference");
451 // Allow base/index to appear in either order (although GAS doesn't).
453 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
455 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
458 if (Disp.isImm() && isDisp8(Disp.getImm())) {
459 if (Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
460 // There is no displacement; just the register.
461 EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS);
464 // Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
465 EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS);
466 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
469 // This is the [REG]+disp16 case.
470 EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS);
472 // There is no BaseReg; this is the plain [disp16] case.
473 EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS);
476 // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
477 EmitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups);
481 // Determine whether a SIB byte is needed.
482 // If no BaseReg, issue a RIP relative instruction only if the MCE can
483 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
484 // 2-7) and absolute references.
486 if (// The SIB byte must be used if there is an index register.
487 IndexReg.getReg() == 0 &&
488 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
489 // encode to an R/M value of 4, which indicates that a SIB byte is
491 BaseRegNo != N86::ESP &&
492 // If there is no base register and we're in 64-bit mode, we need a SIB
493 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
494 (!is64BitMode(STI) || BaseReg != 0)) {
496 if (BaseReg == 0) { // [disp32] in X86-32 mode
497 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
498 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups);
502 // If the base is not EBP/ESP and there is no displacement, use simple
503 // indirect register encoding, this handles addresses like [EAX]. The
504 // encoding for [EBP] with no displacement means [disp32] so we handle it
505 // by emitting a displacement of 0 below.
506 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
507 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
511 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
513 if (!HasEVEX && isDisp8(Disp.getImm())) {
514 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
515 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
518 // Try EVEX compressed 8-bit displacement first; if failed, fall back to
519 // 32-bit displacement.
521 if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
522 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
523 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups,
524 CDisp8 - Disp.getImm());
529 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
530 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
531 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
536 // We need a SIB byte, so start by outputting the ModR/M byte first
537 assert(IndexReg.getReg() != X86::ESP &&
538 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
540 bool ForceDisp32 = false;
541 bool ForceDisp8 = false;
545 // If there is no base register, we emit the special case SIB byte with
546 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
547 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
549 } else if (!Disp.isImm()) {
550 // Emit the normal disp32 encoding.
551 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
553 } else if (Disp.getImm() == 0 &&
554 // Base reg can't be anything that ends up with '5' as the base
555 // reg, it is the magic [*] nomenclature that indicates no base.
556 BaseRegNo != N86::EBP) {
557 // Emit no displacement ModR/M byte
558 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
559 } else if (!HasEVEX && isDisp8(Disp.getImm())) {
560 // Emit the disp8 encoding.
561 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
562 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
563 } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
564 // Emit the disp8 encoding.
565 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
566 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
567 ImmOffset = CDisp8 - Disp.getImm();
569 // Emit the normal disp32 encoding.
570 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
573 // Calculate what the SS field value should be...
574 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
575 unsigned SS = SSTable[Scale.getImm()];
578 // Handle the SIB byte for the case where there is no base, see Intel
579 // Manual 2A, table 2-7. The displacement has already been output.
581 if (IndexReg.getReg())
582 IndexRegNo = GetX86RegNum(IndexReg);
583 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
585 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
588 if (IndexReg.getReg())
589 IndexRegNo = GetX86RegNum(IndexReg);
591 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
592 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
595 // Do we need to output a displacement?
597 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset);
598 else if (ForceDisp32 || Disp.getImm() != 0)
599 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
600 CurByte, OS, Fixups);
603 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
605 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
606 int MemOperand, const MCInst &MI,
607 const MCInstrDesc &Desc,
608 raw_ostream &OS) const {
609 unsigned char Encoding = (TSFlags & X86II::EncodingMask) >>
610 X86II::EncodingShift;
611 bool HasEVEX_K = ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
612 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
613 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
614 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
615 bool HasEVEX_RC = (TSFlags >> X86II::VEXShift) & X86II::EVEX_RC;
617 // VEX_R: opcode externsion equivalent to REX.R in
618 // 1's complement (inverted) form
620 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
621 // 0: Same as REX_R=1 (64 bit mode only)
623 unsigned char VEX_R = 0x1;
624 unsigned char EVEX_R2 = 0x1;
626 // VEX_X: equivalent to REX.X, only used when a
627 // register is used for index in SIB Byte.
629 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
630 // 0: Same as REX.X=1 (64-bit mode only)
631 unsigned char VEX_X = 0x1;
635 // 1: Same as REX_B=0 (ignored in 32-bit mode)
636 // 0: Same as REX_B=1 (64 bit mode only)
638 unsigned char VEX_B = 0x1;
640 // VEX_W: opcode specific (use like REX.W, or used for
641 // opcode extension, or ignored, depending on the opcode byte)
642 unsigned char VEX_W = 0;
644 // VEX_5M (VEX m-mmmmm field):
646 // 0b00000: Reserved for future use
647 // 0b00001: implied 0F leading opcode
648 // 0b00010: implied 0F 38 leading opcode bytes
649 // 0b00011: implied 0F 3A leading opcode bytes
650 // 0b00100-0b11111: Reserved for future use
651 // 0b01000: XOP map select - 08h instructions with imm byte
652 // 0b01001: XOP map select - 09h instructions with no imm byte
653 // 0b01010: XOP map select - 0Ah instructions with imm dword
654 unsigned char VEX_5M = 0;
656 // VEX_4V (VEX vvvv field): a register specifier
657 // (in 1's complement form) or 1111 if unused.
658 unsigned char VEX_4V = 0xf;
659 unsigned char EVEX_V2 = 0x1;
661 // VEX_L (Vector Length):
663 // 0: scalar or 128-bit vector
666 unsigned char VEX_L = 0;
667 unsigned char EVEX_L2 = 0;
669 // VEX_PP: opcode extension providing equivalent
670 // functionality of a SIMD prefix
677 unsigned char VEX_PP = 0;
680 unsigned char EVEX_U = 1; // Always '1' so far
683 unsigned char EVEX_z = 0;
686 unsigned char EVEX_b = 0;
689 unsigned char EVEX_rc = 0;
692 unsigned char EVEX_aaa = 0;
694 bool EncodeRC = false;
696 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
699 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
701 if (((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2))
704 if (HasEVEX_K && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_Z))
707 if (((TSFlags >> X86II::VEXShift) & X86II::EVEX_B))
710 switch (TSFlags & X86II::OpPrefixMask) {
711 default: break; // VEX_PP already correct
712 case X86II::PD: VEX_PP = 0x1; break; // 66
713 case X86II::XS: VEX_PP = 0x2; break; // F3
714 case X86II::XD: VEX_PP = 0x3; break; // F2
717 switch (TSFlags & X86II::OpMapMask) {
718 default: llvm_unreachable("Invalid prefix!");
719 case X86II::TB: VEX_5M = 0x1; break; // 0F
720 case X86II::T8: VEX_5M = 0x2; break; // 0F 38
721 case X86II::TA: VEX_5M = 0x3; break; // 0F 3A
722 case X86II::XOP8: VEX_5M = 0x8; break;
723 case X86II::XOP9: VEX_5M = 0x9; break;
724 case X86II::XOPA: VEX_5M = 0xA; break;
727 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
728 unsigned NumOps = Desc.getNumOperands();
729 unsigned CurOp = X86II::getOperandBias(Desc);
731 switch (TSFlags & X86II::FormMask) {
732 default: llvm_unreachable("Unexpected form in EmitVEXOpcodePrefix!");
735 case X86II::MRMDestMem: {
736 // MRMDestMem instructions forms:
737 // MemAddr, src1(ModR/M)
738 // MemAddr, src1(VEX_4V), src2(ModR/M)
739 // MemAddr, src1(ModR/M), imm8
741 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
742 X86::AddrBaseReg).getReg()))
744 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
745 X86::AddrIndexReg).getReg()))
747 if (X86II::is32ExtendedReg(MI.getOperand(MemOperand +
748 X86::AddrIndexReg).getReg()))
751 CurOp += X86::AddrNumOperands;
754 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
757 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
758 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
763 const MCOperand &MO = MI.getOperand(CurOp);
765 if (X86II::isX86_64ExtendedReg(MO.getReg()))
767 if (X86II::is32ExtendedReg(MO.getReg()))
772 case X86II::MRMSrcMem:
773 // MRMSrcMem instructions forms:
774 // src1(ModR/M), MemAddr
775 // src1(ModR/M), src2(VEX_4V), MemAddr
776 // src1(ModR/M), MemAddr, imm8
777 // src1(ModR/M), MemAddr, src2(VEX_I8IMM)
780 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
781 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
782 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
784 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
789 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
792 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
793 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
798 if (X86II::isX86_64ExtendedReg(
799 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
801 if (X86II::isX86_64ExtendedReg(
802 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
804 if (X86II::is32ExtendedReg(MI.getOperand(MemOperand +
805 X86::AddrIndexReg).getReg()))
809 // Instruction format for 4VOp3:
810 // src1(ModR/M), MemAddr, src3(VEX_4V)
811 // CurOp points to start of the MemoryOperand,
812 // it skips TIED_TO operands if exist, then increments past src1.
813 // CurOp + X86::AddrNumOperands will point to src3.
814 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands);
816 case X86II::MRM0m: case X86II::MRM1m:
817 case X86II::MRM2m: case X86II::MRM3m:
818 case X86II::MRM4m: case X86II::MRM5m:
819 case X86II::MRM6m: case X86II::MRM7m: {
820 // MRM[0-9]m instructions forms:
822 // src1(VEX_4V), MemAddr
824 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
825 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
831 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
833 if (X86II::isX86_64ExtendedReg(
834 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
836 if (X86II::isX86_64ExtendedReg(
837 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
841 case X86II::MRMSrcReg:
842 // MRMSrcReg instructions forms:
843 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
844 // dst(ModR/M), src1(ModR/M)
845 // dst(ModR/M), src1(ModR/M), imm8
848 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
849 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
850 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
852 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
857 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
860 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
861 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
866 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
869 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
871 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
875 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
878 unsigned RcOperand = NumOps-1;
879 assert(RcOperand >= CurOp);
880 EVEX_rc = MI.getOperand(RcOperand).getImm() & 0x3;
885 case X86II::MRMDestReg:
886 // MRMDestReg instructions forms:
887 // dst(ModR/M), src(ModR/M)
888 // dst(ModR/M), src(ModR/M), imm8
889 // dst(ModR/M), src1(VEX_4V), src2(ModR/M)
890 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
892 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
897 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
900 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
901 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
906 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
908 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
913 case X86II::MRM0r: case X86II::MRM1r:
914 case X86II::MRM2r: case X86II::MRM3r:
915 case X86II::MRM4r: case X86II::MRM5r:
916 case X86II::MRM6r: case X86II::MRM7r:
917 // MRM0r-MRM7r instructions forms:
918 // dst(VEX_4V), src(ModR/M), imm8
920 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
921 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
926 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
928 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
930 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
935 if (Encoding == X86II::VEX || Encoding == X86II::XOP) {
936 // VEX opcode prefix can have 2 or 3 bytes
939 // +-----+ +--------------+ +-------------------+
940 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
941 // +-----+ +--------------+ +-------------------+
943 // +-----+ +-------------------+
944 // | C5h | | R | vvvv | L | pp |
945 // +-----+ +-------------------+
947 // XOP uses a similar prefix:
948 // +-----+ +--------------+ +-------------------+
949 // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp |
950 // +-----+ +--------------+ +-------------------+
951 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
953 // Can we use the 2 byte VEX prefix?
954 if (Encoding == X86II::VEX && VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) {
955 EmitByte(0xC5, CurByte, OS);
956 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
961 EmitByte(Encoding == X86II::XOP ? 0x8F : 0xC4, CurByte, OS);
962 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
963 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
965 assert(Encoding == X86II::EVEX && "unknown encoding!");
966 // EVEX opcode prefix can have 4 bytes
968 // +-----+ +--------------+ +-------------------+ +------------------------+
969 // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
970 // +-----+ +--------------+ +-------------------+ +------------------------+
971 assert((VEX_5M & 0x3) == VEX_5M
972 && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!");
976 EmitByte(0x62, CurByte, OS);
977 EmitByte((VEX_R << 7) |
981 VEX_5M, CurByte, OS);
982 EmitByte((VEX_W << 7) |
985 VEX_PP, CurByte, OS);
987 EmitByte((EVEX_z << 7) |
991 EVEX_aaa, CurByte, OS);
993 EmitByte((EVEX_z << 7) |
998 EVEX_aaa, CurByte, OS);
1002 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
1003 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
1004 /// size, and 3) use of X86-64 extended registers.
1005 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
1006 const MCInstrDesc &Desc) {
1008 if (TSFlags & X86II::REX_W)
1009 REX |= 1 << 3; // set REX.W
1011 if (MI.getNumOperands() == 0) return REX;
1013 unsigned NumOps = MI.getNumOperands();
1014 // FIXME: MCInst should explicitize the two-addrness.
1015 bool isTwoAddr = NumOps > 1 &&
1016 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
1018 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
1019 unsigned i = isTwoAddr ? 1 : 0;
1020 for (; i != NumOps; ++i) {
1021 const MCOperand &MO = MI.getOperand(i);
1022 if (!MO.isReg()) continue;
1023 unsigned Reg = MO.getReg();
1024 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
1025 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
1026 // that returns non-zero.
1027 REX |= 0x40; // REX fixed encoding prefix
1031 switch (TSFlags & X86II::FormMask) {
1032 case X86II::MRMSrcReg:
1033 if (MI.getOperand(0).isReg() &&
1034 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1035 REX |= 1 << 2; // set REX.R
1036 i = isTwoAddr ? 2 : 1;
1037 for (; i != NumOps; ++i) {
1038 const MCOperand &MO = MI.getOperand(i);
1039 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
1040 REX |= 1 << 0; // set REX.B
1043 case X86II::MRMSrcMem: {
1044 if (MI.getOperand(0).isReg() &&
1045 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1046 REX |= 1 << 2; // set REX.R
1048 i = isTwoAddr ? 2 : 1;
1049 for (; i != NumOps; ++i) {
1050 const MCOperand &MO = MI.getOperand(i);
1052 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1053 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
1060 case X86II::MRM0m: case X86II::MRM1m:
1061 case X86II::MRM2m: case X86II::MRM3m:
1062 case X86II::MRM4m: case X86II::MRM5m:
1063 case X86II::MRM6m: case X86II::MRM7m:
1064 case X86II::MRMDestMem: {
1065 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
1066 i = isTwoAddr ? 1 : 0;
1067 if (NumOps > e && MI.getOperand(e).isReg() &&
1068 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
1069 REX |= 1 << 2; // set REX.R
1071 for (; i != e; ++i) {
1072 const MCOperand &MO = MI.getOperand(i);
1074 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1075 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
1082 if (MI.getOperand(0).isReg() &&
1083 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1084 REX |= 1 << 0; // set REX.B
1085 i = isTwoAddr ? 2 : 1;
1086 for (unsigned e = NumOps; i != e; ++i) {
1087 const MCOperand &MO = MI.getOperand(i);
1088 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
1089 REX |= 1 << 2; // set REX.R
1096 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
1097 void X86MCCodeEmitter::EmitSegmentOverridePrefix(unsigned &CurByte,
1098 unsigned SegOperand,
1100 raw_ostream &OS) const {
1101 // Check for explicit segment override on memory operand.
1102 switch (MI.getOperand(SegOperand).getReg()) {
1103 default: llvm_unreachable("Unknown segment register!");
1105 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
1106 case X86::SS: EmitByte(0x36, CurByte, OS); break;
1107 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
1108 case X86::ES: EmitByte(0x26, CurByte, OS); break;
1109 case X86::FS: EmitByte(0x64, CurByte, OS); break;
1110 case X86::GS: EmitByte(0x65, CurByte, OS); break;
1114 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
1116 /// MemOperand is the operand # of the start of a memory operand if present. If
1117 /// Not present, it is -1.
1118 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
1119 int MemOperand, const MCInst &MI,
1120 const MCInstrDesc &Desc,
1121 const MCSubtargetInfo &STI,
1122 raw_ostream &OS) const {
1124 // Emit the operand size opcode prefix as needed.
1125 unsigned char OpSize = (TSFlags & X86II::OpSizeMask) >> X86II::OpSizeShift;
1126 if (OpSize == (is16BitMode(STI) ? X86II::OpSize32 : X86II::OpSize16))
1127 EmitByte(0x66, CurByte, OS);
1129 switch (TSFlags & X86II::OpPrefixMask) {
1130 case X86II::PD: // 66
1131 EmitByte(0x66, CurByte, OS);
1133 case X86II::XS: // F3
1134 EmitByte(0xF3, CurByte, OS);
1136 case X86II::XD: // F2
1137 EmitByte(0xF2, CurByte, OS);
1141 // Handle REX prefix.
1142 // FIXME: Can this come before F2 etc to simplify emission?
1143 if (is64BitMode(STI)) {
1144 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
1145 EmitByte(0x40 | REX, CurByte, OS);
1148 // 0x0F escape code must be emitted just before the opcode.
1149 switch (TSFlags & X86II::OpMapMask) {
1150 case X86II::TB: // Two-byte opcode map
1151 case X86II::T8: // 0F 38
1152 case X86II::TA: // 0F 3A
1153 EmitByte(0x0F, CurByte, OS);
1157 switch (TSFlags & X86II::OpMapMask) {
1158 case X86II::T8: // 0F 38
1159 EmitByte(0x38, CurByte, OS);
1161 case X86II::TA: // 0F 3A
1162 EmitByte(0x3A, CurByte, OS);
1167 void X86MCCodeEmitter::
1168 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1169 SmallVectorImpl<MCFixup> &Fixups,
1170 const MCSubtargetInfo &STI) const {
1171 unsigned Opcode = MI.getOpcode();
1172 const MCInstrDesc &Desc = MCII.get(Opcode);
1173 uint64_t TSFlags = Desc.TSFlags;
1175 // Pseudo instructions don't get encoded.
1176 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
1179 unsigned NumOps = Desc.getNumOperands();
1180 unsigned CurOp = X86II::getOperandBias(Desc);
1182 // Keep track of the current byte being emitted.
1183 unsigned CurByte = 0;
1185 // Encoding type for this instruction.
1186 unsigned char Encoding = (TSFlags & X86II::EncodingMask) >>
1187 X86II::EncodingShift;
1189 // It uses the VEX.VVVV field?
1190 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
1191 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
1192 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
1193 const unsigned MemOp4_I8IMMOperand = 2;
1195 // It uses the EVEX.aaa field?
1196 bool HasEVEX_K = ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
1197 bool HasEVEX_RC = ((TSFlags >> X86II::VEXShift) & X86II::EVEX_RC);
1199 // Determine where the memory operand starts, if present.
1200 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
1201 if (MemoryOperand != -1) MemoryOperand += CurOp;
1203 // Emit the lock opcode prefix as needed.
1204 if (TSFlags & X86II::LOCK)
1205 EmitByte(0xF0, CurByte, OS);
1207 // Emit segment override opcode prefix as needed.
1208 if (MemoryOperand >= 0)
1209 EmitSegmentOverridePrefix(CurByte, MemoryOperand+X86::AddrSegmentReg,
1212 // Emit the repeat opcode prefix as needed.
1213 if (TSFlags & X86II::REP)
1214 EmitByte(0xF3, CurByte, OS);
1216 // Emit the address size opcode prefix as needed.
1217 bool need_address_override;
1218 // The AdSize prefix is only for 32-bit and 64-bit modes. Hm, perhaps we
1219 // should introduce an AdSize16 bit instead of having seven special cases?
1220 if ((!is16BitMode(STI) && TSFlags & X86II::AdSize) ||
1221 (is16BitMode(STI) && (MI.getOpcode() == X86::JECXZ_32 ||
1222 MI.getOpcode() == X86::MOV8o8a ||
1223 MI.getOpcode() == X86::MOV16o16a ||
1224 MI.getOpcode() == X86::MOV32o32a ||
1225 MI.getOpcode() == X86::MOV8ao8 ||
1226 MI.getOpcode() == X86::MOV16ao16 ||
1227 MI.getOpcode() == X86::MOV32ao32))) {
1228 need_address_override = true;
1229 } else if (MemoryOperand < 0) {
1230 need_address_override = false;
1231 } else if (is64BitMode(STI)) {
1232 assert(!Is16BitMemOperand(MI, MemoryOperand, STI));
1233 need_address_override = Is32BitMemOperand(MI, MemoryOperand);
1234 } else if (is32BitMode(STI)) {
1235 assert(!Is64BitMemOperand(MI, MemoryOperand));
1236 need_address_override = Is16BitMemOperand(MI, MemoryOperand, STI);
1238 assert(is16BitMode(STI));
1239 assert(!Is64BitMemOperand(MI, MemoryOperand));
1240 need_address_override = !Is16BitMemOperand(MI, MemoryOperand, STI);
1243 if (need_address_override)
1244 EmitByte(0x67, CurByte, OS);
1247 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS);
1249 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1251 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1253 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1254 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1256 unsigned SrcRegNum = 0;
1257 switch (TSFlags & X86II::FormMask) {
1258 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
1259 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1261 llvm_unreachable("Pseudo instruction shouldn't be emitted");
1262 case X86II::RawFrmDstSrc: {
1263 unsigned siReg = MI.getOperand(1).getReg();
1264 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) ||
1265 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) ||
1266 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&
1267 "SI and DI register sizes do not match");
1268 // Emit segment override opcode prefix as needed (not for %ds).
1269 if (MI.getOperand(2).getReg() != X86::DS)
1270 EmitSegmentOverridePrefix(CurByte, 2, MI, OS);
1271 // Emit AdSize prefix as needed.
1272 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1273 (is32BitMode(STI) && siReg == X86::SI))
1274 EmitByte(0x67, CurByte, OS);
1275 CurOp += 3; // Consume operands.
1276 EmitByte(BaseOpcode, CurByte, OS);
1279 case X86II::RawFrmSrc: {
1280 unsigned siReg = MI.getOperand(0).getReg();
1281 // Emit segment override opcode prefix as needed (not for %ds).
1282 if (MI.getOperand(1).getReg() != X86::DS)
1283 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1284 // Emit AdSize prefix as needed.
1285 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1286 (is32BitMode(STI) && siReg == X86::SI))
1287 EmitByte(0x67, CurByte, OS);
1288 CurOp += 2; // Consume operands.
1289 EmitByte(BaseOpcode, CurByte, OS);
1292 case X86II::RawFrmDst: {
1293 unsigned siReg = MI.getOperand(0).getReg();
1294 // Emit AdSize prefix as needed.
1295 if ((!is32BitMode(STI) && siReg == X86::EDI) ||
1296 (is32BitMode(STI) && siReg == X86::DI))
1297 EmitByte(0x67, CurByte, OS);
1298 ++CurOp; // Consume operand.
1299 EmitByte(BaseOpcode, CurByte, OS);
1303 EmitByte(BaseOpcode, CurByte, OS);
1305 case X86II::RawFrmMemOffs:
1306 // Emit segment override opcode prefix as needed.
1307 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1308 EmitByte(BaseOpcode, CurByte, OS);
1309 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1310 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1311 CurByte, OS, Fixups);
1312 ++CurOp; // skip segment operand
1314 case X86II::RawFrmImm8:
1315 EmitByte(BaseOpcode, CurByte, OS);
1316 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1317 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1318 CurByte, OS, Fixups);
1319 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte,
1322 case X86II::RawFrmImm16:
1323 EmitByte(BaseOpcode, CurByte, OS);
1324 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1325 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1326 CurByte, OS, Fixups);
1327 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte,
1331 case X86II::AddRegFrm:
1332 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
1335 case X86II::MRMDestReg:
1336 EmitByte(BaseOpcode, CurByte, OS);
1337 SrcRegNum = CurOp + 1;
1339 if (HasEVEX_K) // Skip writemask
1342 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1345 EmitRegModRMByte(MI.getOperand(CurOp),
1346 GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS);
1347 CurOp = SrcRegNum + 1;
1350 case X86II::MRMDestMem:
1351 EmitByte(BaseOpcode, CurByte, OS);
1352 SrcRegNum = CurOp + X86::AddrNumOperands;
1354 if (HasEVEX_K) // Skip writemask
1357 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1360 EmitMemModRMByte(MI, CurOp,
1361 GetX86RegNum(MI.getOperand(SrcRegNum)),
1362 TSFlags, CurByte, OS, Fixups, STI);
1363 CurOp = SrcRegNum + 1;
1366 case X86II::MRMSrcReg:
1367 EmitByte(BaseOpcode, CurByte, OS);
1368 SrcRegNum = CurOp + 1;
1370 if (HasEVEX_K) // Skip writemask
1373 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1376 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
1379 EmitRegModRMByte(MI.getOperand(SrcRegNum),
1380 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1382 // 2 operands skipped with HasMemOp4, compensate accordingly
1383 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
1386 // do not count the rounding control operand
1391 case X86II::MRMSrcMem: {
1392 int AddrOperands = X86::AddrNumOperands;
1393 unsigned FirstMemOp = CurOp+1;
1395 if (HasEVEX_K) { // Skip writemask
1402 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1404 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
1407 EmitByte(BaseOpcode, CurByte, OS);
1409 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1410 TSFlags, CurByte, OS, Fixups, STI);
1411 CurOp += AddrOperands + 1;
1418 case X86II::MRM0r: case X86II::MRM1r:
1419 case X86II::MRM2r: case X86II::MRM3r:
1420 case X86II::MRM4r: case X86II::MRM5r:
1421 case X86II::MRM6r: case X86II::MRM7r: {
1422 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1424 EmitByte(BaseOpcode, CurByte, OS);
1425 uint64_t Form = TSFlags & X86II::FormMask;
1426 EmitRegModRMByte(MI.getOperand(CurOp++),
1427 (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r,
1433 case X86II::MRM0m: case X86II::MRM1m:
1434 case X86II::MRM2m: case X86II::MRM3m:
1435 case X86II::MRM4m: case X86II::MRM5m:
1436 case X86II::MRM6m: case X86II::MRM7m: {
1437 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1439 EmitByte(BaseOpcode, CurByte, OS);
1440 uint64_t Form = TSFlags & X86II::FormMask;
1441 EmitMemModRMByte(MI, CurOp, (Form == X86II::MRMXm) ? 0 : Form-X86II::MRM0m,
1442 TSFlags, CurByte, OS, Fixups, STI);
1443 CurOp += X86::AddrNumOperands;
1446 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
1447 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8:
1448 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
1449 case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4:
1450 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8:
1451 case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB:
1452 case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE:
1453 case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E1:
1454 case X86II::MRM_E2: case X86II::MRM_E3: case X86II::MRM_E4:
1455 case X86II::MRM_E5: case X86II::MRM_E8: case X86II::MRM_E9:
1456 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
1457 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_F0:
1458 case X86II::MRM_F1: case X86II::MRM_F2: case X86II::MRM_F3:
1459 case X86II::MRM_F4: case X86II::MRM_F5: case X86II::MRM_F6:
1460 case X86II::MRM_F7: case X86II::MRM_F8: case X86II::MRM_F9:
1461 case X86II::MRM_FA: case X86II::MRM_FB: case X86II::MRM_FC:
1462 case X86II::MRM_FD: case X86II::MRM_FE: case X86II::MRM_FF:
1463 EmitByte(BaseOpcode, CurByte, OS);
1466 switch (TSFlags & X86II::FormMask) {
1467 default: llvm_unreachable("Invalid Form");
1468 case X86II::MRM_C0: MRM = 0xC0; break;
1469 case X86II::MRM_C1: MRM = 0xC1; break;
1470 case X86II::MRM_C2: MRM = 0xC2; break;
1471 case X86II::MRM_C3: MRM = 0xC3; break;
1472 case X86II::MRM_C4: MRM = 0xC4; break;
1473 case X86II::MRM_C8: MRM = 0xC8; break;
1474 case X86II::MRM_C9: MRM = 0xC9; break;
1475 case X86II::MRM_CA: MRM = 0xCA; break;
1476 case X86II::MRM_CB: MRM = 0xCB; break;
1477 case X86II::MRM_D0: MRM = 0xD0; break;
1478 case X86II::MRM_D1: MRM = 0xD1; break;
1479 case X86II::MRM_D4: MRM = 0xD4; break;
1480 case X86II::MRM_D5: MRM = 0xD5; break;
1481 case X86II::MRM_D6: MRM = 0xD6; break;
1482 case X86II::MRM_D8: MRM = 0xD8; break;
1483 case X86II::MRM_D9: MRM = 0xD9; break;
1484 case X86II::MRM_DA: MRM = 0xDA; break;
1485 case X86II::MRM_DB: MRM = 0xDB; break;
1486 case X86II::MRM_DC: MRM = 0xDC; break;
1487 case X86II::MRM_DD: MRM = 0xDD; break;
1488 case X86II::MRM_DE: MRM = 0xDE; break;
1489 case X86II::MRM_DF: MRM = 0xDF; break;
1490 case X86II::MRM_E0: MRM = 0xE0; break;
1491 case X86II::MRM_E1: MRM = 0xE1; break;
1492 case X86II::MRM_E2: MRM = 0xE2; break;
1493 case X86II::MRM_E3: MRM = 0xE3; break;
1494 case X86II::MRM_E4: MRM = 0xE4; break;
1495 case X86II::MRM_E5: MRM = 0xE5; break;
1496 case X86II::MRM_E8: MRM = 0xE8; break;
1497 case X86II::MRM_E9: MRM = 0xE9; break;
1498 case X86II::MRM_EA: MRM = 0xEA; break;
1499 case X86II::MRM_EB: MRM = 0xEB; break;
1500 case X86II::MRM_EC: MRM = 0xEC; break;
1501 case X86II::MRM_ED: MRM = 0xED; break;
1502 case X86II::MRM_EE: MRM = 0xEE; break;
1503 case X86II::MRM_F0: MRM = 0xF0; break;
1504 case X86II::MRM_F1: MRM = 0xF1; break;
1505 case X86II::MRM_F2: MRM = 0xF2; break;
1506 case X86II::MRM_F3: MRM = 0xF3; break;
1507 case X86II::MRM_F4: MRM = 0xF4; break;
1508 case X86II::MRM_F5: MRM = 0xF5; break;
1509 case X86II::MRM_F6: MRM = 0xF6; break;
1510 case X86II::MRM_F7: MRM = 0xF7; break;
1511 case X86II::MRM_F8: MRM = 0xF8; break;
1512 case X86II::MRM_F9: MRM = 0xF9; break;
1513 case X86II::MRM_FA: MRM = 0xFA; break;
1514 case X86II::MRM_FB: MRM = 0xFB; break;
1515 case X86II::MRM_FC: MRM = 0xFC; break;
1516 case X86II::MRM_FD: MRM = 0xFD; break;
1517 case X86II::MRM_FE: MRM = 0xFE; break;
1518 case X86II::MRM_FF: MRM = 0xFF; break;
1520 EmitByte(MRM, CurByte, OS);
1524 // If there is a remaining operand, it must be a trailing immediate. Emit it
1525 // according to the right size for the instruction. Some instructions
1526 // (SSE4a extrq and insertq) have two trailing immediates.
1527 while (CurOp != NumOps && NumOps - CurOp <= 2) {
1528 // The last source register of a 4 operand instruction in AVX is encoded
1529 // in bits[7:4] of a immediate byte.
1530 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
1531 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
1534 unsigned RegNum = GetX86RegNum(MO) << 4;
1535 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1537 // If there is an additional 5th operand it must be an immediate, which
1538 // is encoded in bits[3:0]
1539 if (CurOp != NumOps) {
1540 const MCOperand &MIMM = MI.getOperand(CurOp++);
1542 unsigned Val = MIMM.getImm();
1543 assert(Val < 16 && "Immediate operand value out of range");
1547 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1,
1548 CurByte, OS, Fixups);
1550 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1551 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1552 CurByte, OS, Fixups);
1556 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1557 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1561 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1562 errs() << "Cannot encode all operands of: ";