1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "MCTargetDesc/X86BaseInfo.h"
16 #include "MCTargetDesc/X86FixupKinds.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "mccodeemitter"
32 class X86MCCodeEmitter : public MCCodeEmitter {
33 X86MCCodeEmitter(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION;
34 void operator=(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION;
35 const MCInstrInfo &MCII;
38 X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
39 : MCII(mcii), Ctx(ctx) {
42 ~X86MCCodeEmitter() {}
44 bool is64BitMode(const MCSubtargetInfo &STI) const {
45 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
48 bool is32BitMode(const MCSubtargetInfo &STI) const {
49 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
52 bool is16BitMode(const MCSubtargetInfo &STI) const {
53 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
56 /// Is16BitMemOperand - Return true if the specified instruction has
57 /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
58 bool Is16BitMemOperand(const MCInst &MI, unsigned Op,
59 const MCSubtargetInfo &STI) const {
60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
62 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
64 if (is16BitMode(STI) && BaseReg.getReg() == 0 &&
65 Disp.isImm() && Disp.getImm() < 0x10000)
67 if ((BaseReg.getReg() != 0 &&
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
69 (IndexReg.getReg() != 0 &&
70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
75 unsigned GetX86RegNum(const MCOperand &MO) const {
76 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
79 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
80 // 0-7 and the difference between the 2 groups is given by the REX prefix.
81 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
82 // in 1's complement form, example:
84 // ModRM field => XMM9 => 1
85 // VEX.VVVV => XMM9 => ~9
87 // See table 4-35 of Intel AVX Programming Reference for details.
88 unsigned char getVEXRegisterEncoding(const MCInst &MI,
89 unsigned OpNum) const {
90 unsigned SrcReg = MI.getOperand(OpNum).getReg();
91 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
92 if (X86II::isX86_64ExtendedReg(SrcReg))
95 // The registers represented through VEX_VVVV should
96 // be encoded in 1's complement form.
97 return (~SrcRegNum) & 0xf;
100 unsigned char getWriteMaskRegisterEncoding(const MCInst &MI,
101 unsigned OpNum) const {
102 assert(X86::K0 != MI.getOperand(OpNum).getReg() &&
103 "Invalid mask register as write-mask!");
104 unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum));
108 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
113 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
114 raw_ostream &OS) const {
115 // Output the constant in little endian byte order.
116 for (unsigned i = 0; i != Size; ++i) {
117 EmitByte(Val & 255, CurByte, OS);
122 void EmitImmediate(const MCOperand &Disp, SMLoc Loc,
123 unsigned ImmSize, MCFixupKind FixupKind,
124 unsigned &CurByte, raw_ostream &OS,
125 SmallVectorImpl<MCFixup> &Fixups,
126 int ImmOffset = 0) const;
128 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
130 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
131 return RM | (RegOpcode << 3) | (Mod << 6);
134 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
135 unsigned &CurByte, raw_ostream &OS) const {
136 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
139 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
140 unsigned &CurByte, raw_ostream &OS) const {
141 // SIB byte is in the same format as the ModRMByte.
142 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
146 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
147 unsigned RegOpcodeField,
148 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
149 SmallVectorImpl<MCFixup> &Fixups,
150 const MCSubtargetInfo &STI) const;
152 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
153 SmallVectorImpl<MCFixup> &Fixups,
154 const MCSubtargetInfo &STI) const override;
156 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
157 const MCInst &MI, const MCInstrDesc &Desc,
158 raw_ostream &OS) const;
160 void EmitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand,
161 const MCInst &MI, raw_ostream &OS) const;
163 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
164 const MCInst &MI, const MCInstrDesc &Desc,
165 const MCSubtargetInfo &STI,
166 raw_ostream &OS) const;
169 } // end anonymous namespace
172 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
173 const MCRegisterInfo &MRI,
174 const MCSubtargetInfo &STI,
176 return new X86MCCodeEmitter(MCII, Ctx);
179 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
180 /// sign-extended field.
181 static bool isDisp8(int Value) {
182 return Value == (signed char)Value;
185 /// isCDisp8 - Return true if this signed displacement fits in a 8-bit
186 /// compressed dispacement field.
187 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
188 assert(((TSFlags & X86II::EncodingMask) >>
189 X86II::EncodingShift == X86II::EVEX) &&
190 "Compressed 8-bit displacement is only valid for EVEX inst.");
193 (TSFlags >> X86II::CD8_Scale_Shift) & X86II::CD8_Scale_Mask;
194 if (CD8_Scale == 0) {
196 return isDisp8(Value);
199 unsigned Mask = CD8_Scale - 1;
200 assert((CD8_Scale & Mask) == 0 && "Invalid memory object size.");
201 if (Value & Mask) // Unaligned offset
203 Value /= (int)CD8_Scale;
204 bool Ret = (Value == (signed char)Value);
211 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
212 /// in an instruction with the specified TSFlags.
213 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
214 unsigned Size = X86II::getSizeOfImm(TSFlags);
215 bool isPCRel = X86II::isImmPCRel(TSFlags);
217 if (X86II::isImmSigned(TSFlags)) {
219 default: llvm_unreachable("Unsupported signed fixup size!");
220 case 4: return MCFixupKind(X86::reloc_signed_4byte);
223 return MCFixup::getKindForSize(Size, isPCRel);
226 /// Is32BitMemOperand - Return true if the specified instruction has
227 /// a 32-bit memory operand. Op specifies the operand # of the memoperand.
228 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
229 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
230 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
232 if ((BaseReg.getReg() != 0 &&
233 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
234 (IndexReg.getReg() != 0 &&
235 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
240 /// Is64BitMemOperand - Return true if the specified instruction has
241 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
243 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
244 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
245 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
247 if ((BaseReg.getReg() != 0 &&
248 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
249 (IndexReg.getReg() != 0 &&
250 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
256 /// StartsWithGlobalOffsetTable - Check if this expression starts with
257 /// _GLOBAL_OFFSET_TABLE_ and if it is of the form
258 /// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF
259 /// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
260 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
261 /// of a binary expression.
262 enum GlobalOffsetTableExprKind {
267 static GlobalOffsetTableExprKind
268 StartsWithGlobalOffsetTable(const MCExpr *Expr) {
269 const MCExpr *RHS = nullptr;
270 if (Expr->getKind() == MCExpr::Binary) {
271 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
276 if (Expr->getKind() != MCExpr::SymbolRef)
279 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
280 const MCSymbol &S = Ref->getSymbol();
281 if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
283 if (RHS && RHS->getKind() == MCExpr::SymbolRef)
288 static bool HasSecRelSymbolRef(const MCExpr *Expr) {
289 if (Expr->getKind() == MCExpr::SymbolRef) {
290 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
291 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL;
296 void X86MCCodeEmitter::
297 EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size,
298 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS,
299 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
300 const MCExpr *Expr = nullptr;
301 if (DispOp.isImm()) {
302 // If this is a simple integer displacement that doesn't require a
303 // relocation, emit it now.
304 if (FixupKind != FK_PCRel_1 &&
305 FixupKind != FK_PCRel_2 &&
306 FixupKind != FK_PCRel_4) {
307 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
310 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx);
312 Expr = DispOp.getExpr();
315 // If we have an immoffset, add it to the expression.
316 if ((FixupKind == FK_Data_4 ||
317 FixupKind == FK_Data_8 ||
318 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
319 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr);
320 if (Kind != GOT_None) {
321 assert(ImmOffset == 0);
324 FixupKind = MCFixupKind(X86::reloc_global_offset_table8);
327 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
330 if (Kind == GOT_Normal)
332 } else if (Expr->getKind() == MCExpr::SymbolRef) {
333 if (HasSecRelSymbolRef(Expr)) {
334 FixupKind = MCFixupKind(FK_SecRel_4);
336 } else if (Expr->getKind() == MCExpr::Binary) {
337 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr);
338 if (HasSecRelSymbolRef(Bin->getLHS())
339 || HasSecRelSymbolRef(Bin->getRHS())) {
340 FixupKind = MCFixupKind(FK_SecRel_4);
345 // If the fixup is pc-relative, we need to bias the value to be relative to
346 // the start of the field, not the end of the field.
347 if (FixupKind == FK_PCRel_4 ||
348 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
349 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
351 if (FixupKind == FK_PCRel_2)
353 if (FixupKind == FK_PCRel_1)
357 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
360 // Emit a symbolic constant as a fixup and 4 zeros.
361 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc));
362 EmitConstant(0, Size, CurByte, OS);
365 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
366 unsigned RegOpcodeField,
367 uint64_t TSFlags, unsigned &CurByte,
369 SmallVectorImpl<MCFixup> &Fixups,
370 const MCSubtargetInfo &STI) const{
371 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
372 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
373 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
374 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
375 unsigned BaseReg = Base.getReg();
376 unsigned char Encoding = (TSFlags & X86II::EncodingMask) >>
377 X86II::EncodingShift;
378 bool HasEVEX = (Encoding == X86II::EVEX);
380 // Handle %rip relative addressing.
381 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
382 assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode");
383 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
384 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
386 unsigned FixupKind = X86::reloc_riprel_4byte;
388 // movq loads are handled with a special relocation form which allows the
389 // linker to eliminate some loads for GOT references which end up in the
390 // same linkage unit.
391 if (MI.getOpcode() == X86::MOV64rm)
392 FixupKind = X86::reloc_riprel_4byte_movq_load;
394 // rip-relative addressing is actually relative to the *next* instruction.
395 // Since an immediate can follow the mod/rm byte for an instruction, this
396 // means that we need to bias the immediate field of the instruction with
397 // the size of the immediate field. If we have this case, add it into the
398 // expression to emit.
399 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
401 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind),
402 CurByte, OS, Fixups, -ImmSize);
406 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
408 // 16-bit addressing forms of the ModR/M byte have a different encoding for
409 // the R/M field and are far more limited in which registers can be used.
410 if (Is16BitMemOperand(MI, Op, STI)) {
412 // For 32-bit addressing, the row and column values in Table 2-2 are
413 // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
414 // some special cases. And GetX86RegNum reflects that numbering.
415 // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
416 // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
417 // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
418 // while values 0-3 indicate the allowed combinations (base+index) of
419 // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
421 // R16Table[] is a lookup from the normal RegNo, to the row values from
422 // Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
423 static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 };
424 unsigned RMfield = R16Table[BaseRegNo];
426 assert(RMfield && "invalid 16-bit base register");
428 if (IndexReg.getReg()) {
429 unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)];
431 assert(IndexReg16 && "invalid 16-bit index register");
432 // We must have one of SI/DI (4,5), and one of BP/BX (6,7).
433 assert(((IndexReg16 ^ RMfield) & 2) &&
434 "invalid 16-bit base/index register combination");
435 assert(Scale.getImm() == 1 &&
436 "invalid scale for 16-bit memory reference");
438 // Allow base/index to appear in either order (although GAS doesn't).
440 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
442 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
445 if (Disp.isImm() && isDisp8(Disp.getImm())) {
446 if (Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
447 // There is no displacement; just the register.
448 EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS);
451 // Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
452 EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS);
453 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
456 // This is the [REG]+disp16 case.
457 EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS);
459 // There is no BaseReg; this is the plain [disp16] case.
460 EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS);
463 // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
464 EmitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups);
468 // Determine whether a SIB byte is needed.
469 // If no BaseReg, issue a RIP relative instruction only if the MCE can
470 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
471 // 2-7) and absolute references.
473 if (// The SIB byte must be used if there is an index register.
474 IndexReg.getReg() == 0 &&
475 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
476 // encode to an R/M value of 4, which indicates that a SIB byte is
478 BaseRegNo != N86::ESP &&
479 // If there is no base register and we're in 64-bit mode, we need a SIB
480 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
481 (!is64BitMode(STI) || BaseReg != 0)) {
483 if (BaseReg == 0) { // [disp32] in X86-32 mode
484 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
485 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups);
489 // If the base is not EBP/ESP and there is no displacement, use simple
490 // indirect register encoding, this handles addresses like [EAX]. The
491 // encoding for [EBP] with no displacement means [disp32] so we handle it
492 // by emitting a displacement of 0 below.
493 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
494 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
498 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
500 if (!HasEVEX && isDisp8(Disp.getImm())) {
501 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
502 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
505 // Try EVEX compressed 8-bit displacement first; if failed, fall back to
506 // 32-bit displacement.
508 if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
509 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
510 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups,
511 CDisp8 - Disp.getImm());
516 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
517 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
518 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
523 // We need a SIB byte, so start by outputting the ModR/M byte first
524 assert(IndexReg.getReg() != X86::ESP &&
525 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
527 bool ForceDisp32 = false;
528 bool ForceDisp8 = false;
532 // If there is no base register, we emit the special case SIB byte with
533 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
534 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
536 } else if (!Disp.isImm()) {
537 // Emit the normal disp32 encoding.
538 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
540 } else if (Disp.getImm() == 0 &&
541 // Base reg can't be anything that ends up with '5' as the base
542 // reg, it is the magic [*] nomenclature that indicates no base.
543 BaseRegNo != N86::EBP) {
544 // Emit no displacement ModR/M byte
545 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
546 } else if (!HasEVEX && isDisp8(Disp.getImm())) {
547 // Emit the disp8 encoding.
548 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
549 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
550 } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
551 // Emit the disp8 encoding.
552 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
553 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
554 ImmOffset = CDisp8 - Disp.getImm();
556 // Emit the normal disp32 encoding.
557 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
560 // Calculate what the SS field value should be...
561 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
562 unsigned SS = SSTable[Scale.getImm()];
565 // Handle the SIB byte for the case where there is no base, see Intel
566 // Manual 2A, table 2-7. The displacement has already been output.
568 if (IndexReg.getReg())
569 IndexRegNo = GetX86RegNum(IndexReg);
570 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
572 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
575 if (IndexReg.getReg())
576 IndexRegNo = GetX86RegNum(IndexReg);
578 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
579 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
582 // Do we need to output a displacement?
584 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset);
585 else if (ForceDisp32 || Disp.getImm() != 0)
586 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
587 CurByte, OS, Fixups);
590 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
592 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
593 int MemOperand, const MCInst &MI,
594 const MCInstrDesc &Desc,
595 raw_ostream &OS) const {
596 unsigned char Encoding = (TSFlags & X86II::EncodingMask) >>
597 X86II::EncodingShift;
598 bool HasEVEX_K = ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
599 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
600 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
601 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
602 bool HasEVEX_RC = (TSFlags >> X86II::VEXShift) & X86II::EVEX_RC;
604 // VEX_R: opcode externsion equivalent to REX.R in
605 // 1's complement (inverted) form
607 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
608 // 0: Same as REX_R=1 (64 bit mode only)
610 unsigned char VEX_R = 0x1;
611 unsigned char EVEX_R2 = 0x1;
613 // VEX_X: equivalent to REX.X, only used when a
614 // register is used for index in SIB Byte.
616 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
617 // 0: Same as REX.X=1 (64-bit mode only)
618 unsigned char VEX_X = 0x1;
622 // 1: Same as REX_B=0 (ignored in 32-bit mode)
623 // 0: Same as REX_B=1 (64 bit mode only)
625 unsigned char VEX_B = 0x1;
627 // VEX_W: opcode specific (use like REX.W, or used for
628 // opcode extension, or ignored, depending on the opcode byte)
629 unsigned char VEX_W = 0;
631 // VEX_5M (VEX m-mmmmm field):
633 // 0b00000: Reserved for future use
634 // 0b00001: implied 0F leading opcode
635 // 0b00010: implied 0F 38 leading opcode bytes
636 // 0b00011: implied 0F 3A leading opcode bytes
637 // 0b00100-0b11111: Reserved for future use
638 // 0b01000: XOP map select - 08h instructions with imm byte
639 // 0b01001: XOP map select - 09h instructions with no imm byte
640 // 0b01010: XOP map select - 0Ah instructions with imm dword
641 unsigned char VEX_5M = 0;
643 // VEX_4V (VEX vvvv field): a register specifier
644 // (in 1's complement form) or 1111 if unused.
645 unsigned char VEX_4V = 0xf;
646 unsigned char EVEX_V2 = 0x1;
648 // VEX_L (Vector Length):
650 // 0: scalar or 128-bit vector
653 unsigned char VEX_L = 0;
654 unsigned char EVEX_L2 = 0;
656 // VEX_PP: opcode extension providing equivalent
657 // functionality of a SIMD prefix
664 unsigned char VEX_PP = 0;
667 unsigned char EVEX_U = 1; // Always '1' so far
670 unsigned char EVEX_z = 0;
673 unsigned char EVEX_b = 0;
676 unsigned char EVEX_rc = 0;
679 unsigned char EVEX_aaa = 0;
681 bool EncodeRC = false;
683 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
686 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
688 if (((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2))
691 if (HasEVEX_K && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_Z))
694 if (((TSFlags >> X86II::VEXShift) & X86II::EVEX_B))
697 switch (TSFlags & X86II::OpPrefixMask) {
698 default: break; // VEX_PP already correct
699 case X86II::PD: VEX_PP = 0x1; break; // 66
700 case X86II::XS: VEX_PP = 0x2; break; // F3
701 case X86II::XD: VEX_PP = 0x3; break; // F2
704 switch (TSFlags & X86II::OpMapMask) {
705 default: llvm_unreachable("Invalid prefix!");
706 case X86II::TB: VEX_5M = 0x1; break; // 0F
707 case X86II::T8: VEX_5M = 0x2; break; // 0F 38
708 case X86II::TA: VEX_5M = 0x3; break; // 0F 3A
709 case X86II::XOP8: VEX_5M = 0x8; break;
710 case X86II::XOP9: VEX_5M = 0x9; break;
711 case X86II::XOPA: VEX_5M = 0xA; break;
714 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
715 unsigned NumOps = Desc.getNumOperands();
716 unsigned CurOp = X86II::getOperandBias(Desc);
718 switch (TSFlags & X86II::FormMask) {
719 default: llvm_unreachable("Unexpected form in EmitVEXOpcodePrefix!");
722 case X86II::MRMDestMem: {
723 // MRMDestMem instructions forms:
724 // MemAddr, src1(ModR/M)
725 // MemAddr, src1(VEX_4V), src2(ModR/M)
726 // MemAddr, src1(ModR/M), imm8
728 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
729 X86::AddrBaseReg).getReg()))
731 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
732 X86::AddrIndexReg).getReg()))
734 if (X86II::is32ExtendedReg(MI.getOperand(MemOperand +
735 X86::AddrIndexReg).getReg()))
738 CurOp += X86::AddrNumOperands;
741 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
744 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
745 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
750 const MCOperand &MO = MI.getOperand(CurOp);
752 if (X86II::isX86_64ExtendedReg(MO.getReg()))
754 if (X86II::is32ExtendedReg(MO.getReg()))
759 case X86II::MRMSrcMem:
760 // MRMSrcMem instructions forms:
761 // src1(ModR/M), MemAddr
762 // src1(ModR/M), src2(VEX_4V), MemAddr
763 // src1(ModR/M), MemAddr, imm8
764 // src1(ModR/M), MemAddr, src2(VEX_I8IMM)
767 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
768 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
769 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
771 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
776 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
779 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
780 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
785 if (X86II::isX86_64ExtendedReg(
786 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
788 if (X86II::isX86_64ExtendedReg(
789 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
791 if (X86II::is32ExtendedReg(MI.getOperand(MemOperand +
792 X86::AddrIndexReg).getReg()))
796 // Instruction format for 4VOp3:
797 // src1(ModR/M), MemAddr, src3(VEX_4V)
798 // CurOp points to start of the MemoryOperand,
799 // it skips TIED_TO operands if exist, then increments past src1.
800 // CurOp + X86::AddrNumOperands will point to src3.
801 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands);
803 case X86II::MRM0m: case X86II::MRM1m:
804 case X86II::MRM2m: case X86II::MRM3m:
805 case X86II::MRM4m: case X86II::MRM5m:
806 case X86II::MRM6m: case X86II::MRM7m: {
807 // MRM[0-9]m instructions forms:
809 // src1(VEX_4V), MemAddr
811 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
812 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
818 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
820 if (X86II::isX86_64ExtendedReg(
821 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
823 if (X86II::isX86_64ExtendedReg(
824 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
828 case X86II::MRMSrcReg:
829 // MRMSrcReg instructions forms:
830 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
831 // dst(ModR/M), src1(ModR/M)
832 // dst(ModR/M), src1(ModR/M), imm8
835 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
836 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
837 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
839 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
844 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
847 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
848 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
853 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
856 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
858 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
862 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
865 unsigned RcOperand = NumOps-1;
866 assert(RcOperand >= CurOp);
867 EVEX_rc = MI.getOperand(RcOperand).getImm() & 0x3;
872 case X86II::MRMDestReg:
873 // MRMDestReg instructions forms:
874 // dst(ModR/M), src(ModR/M)
875 // dst(ModR/M), src(ModR/M), imm8
876 // dst(ModR/M), src1(VEX_4V), src2(ModR/M)
877 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
879 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
884 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
887 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
888 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
893 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
895 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
900 case X86II::MRM0r: case X86II::MRM1r:
901 case X86II::MRM2r: case X86II::MRM3r:
902 case X86II::MRM4r: case X86II::MRM5r:
903 case X86II::MRM6r: case X86II::MRM7r:
904 // MRM0r-MRM7r instructions forms:
905 // dst(VEX_4V), src(ModR/M), imm8
907 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
908 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
913 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
915 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
917 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
922 if (Encoding == X86II::VEX || Encoding == X86II::XOP) {
923 // VEX opcode prefix can have 2 or 3 bytes
926 // +-----+ +--------------+ +-------------------+
927 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
928 // +-----+ +--------------+ +-------------------+
930 // +-----+ +-------------------+
931 // | C5h | | R | vvvv | L | pp |
932 // +-----+ +-------------------+
934 // XOP uses a similar prefix:
935 // +-----+ +--------------+ +-------------------+
936 // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp |
937 // +-----+ +--------------+ +-------------------+
938 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
940 // Can we use the 2 byte VEX prefix?
941 if (Encoding == X86II::VEX && VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) {
942 EmitByte(0xC5, CurByte, OS);
943 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
948 EmitByte(Encoding == X86II::XOP ? 0x8F : 0xC4, CurByte, OS);
949 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
950 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
952 assert(Encoding == X86II::EVEX && "unknown encoding!");
953 // EVEX opcode prefix can have 4 bytes
955 // +-----+ +--------------+ +-------------------+ +------------------------+
956 // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
957 // +-----+ +--------------+ +-------------------+ +------------------------+
958 assert((VEX_5M & 0x3) == VEX_5M
959 && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!");
963 EmitByte(0x62, CurByte, OS);
964 EmitByte((VEX_R << 7) |
968 VEX_5M, CurByte, OS);
969 EmitByte((VEX_W << 7) |
972 VEX_PP, CurByte, OS);
974 EmitByte((EVEX_z << 7) |
978 EVEX_aaa, CurByte, OS);
980 EmitByte((EVEX_z << 7) |
985 EVEX_aaa, CurByte, OS);
989 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
990 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
991 /// size, and 3) use of X86-64 extended registers.
992 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
993 const MCInstrDesc &Desc) {
995 if (TSFlags & X86II::REX_W)
996 REX |= 1 << 3; // set REX.W
998 if (MI.getNumOperands() == 0) return REX;
1000 unsigned NumOps = MI.getNumOperands();
1001 // FIXME: MCInst should explicitize the two-addrness.
1002 bool isTwoAddr = NumOps > 1 &&
1003 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
1005 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
1006 unsigned i = isTwoAddr ? 1 : 0;
1007 for (; i != NumOps; ++i) {
1008 const MCOperand &MO = MI.getOperand(i);
1009 if (!MO.isReg()) continue;
1010 unsigned Reg = MO.getReg();
1011 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
1012 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
1013 // that returns non-zero.
1014 REX |= 0x40; // REX fixed encoding prefix
1018 switch (TSFlags & X86II::FormMask) {
1019 case X86II::MRMSrcReg:
1020 if (MI.getOperand(0).isReg() &&
1021 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1022 REX |= 1 << 2; // set REX.R
1023 i = isTwoAddr ? 2 : 1;
1024 for (; i != NumOps; ++i) {
1025 const MCOperand &MO = MI.getOperand(i);
1026 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
1027 REX |= 1 << 0; // set REX.B
1030 case X86II::MRMSrcMem: {
1031 if (MI.getOperand(0).isReg() &&
1032 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1033 REX |= 1 << 2; // set REX.R
1035 i = isTwoAddr ? 2 : 1;
1036 for (; i != NumOps; ++i) {
1037 const MCOperand &MO = MI.getOperand(i);
1039 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1040 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
1047 case X86II::MRM0m: case X86II::MRM1m:
1048 case X86II::MRM2m: case X86II::MRM3m:
1049 case X86II::MRM4m: case X86II::MRM5m:
1050 case X86II::MRM6m: case X86II::MRM7m:
1051 case X86II::MRMDestMem: {
1052 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
1053 i = isTwoAddr ? 1 : 0;
1054 if (NumOps > e && MI.getOperand(e).isReg() &&
1055 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
1056 REX |= 1 << 2; // set REX.R
1058 for (; i != e; ++i) {
1059 const MCOperand &MO = MI.getOperand(i);
1061 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1062 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
1069 if (MI.getOperand(0).isReg() &&
1070 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1071 REX |= 1 << 0; // set REX.B
1072 i = isTwoAddr ? 2 : 1;
1073 for (unsigned e = NumOps; i != e; ++i) {
1074 const MCOperand &MO = MI.getOperand(i);
1075 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
1076 REX |= 1 << 2; // set REX.R
1083 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
1084 void X86MCCodeEmitter::EmitSegmentOverridePrefix(unsigned &CurByte,
1085 unsigned SegOperand,
1087 raw_ostream &OS) const {
1088 // Check for explicit segment override on memory operand.
1089 switch (MI.getOperand(SegOperand).getReg()) {
1090 default: llvm_unreachable("Unknown segment register!");
1092 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
1093 case X86::SS: EmitByte(0x36, CurByte, OS); break;
1094 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
1095 case X86::ES: EmitByte(0x26, CurByte, OS); break;
1096 case X86::FS: EmitByte(0x64, CurByte, OS); break;
1097 case X86::GS: EmitByte(0x65, CurByte, OS); break;
1101 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
1103 /// MemOperand is the operand # of the start of a memory operand if present. If
1104 /// Not present, it is -1.
1105 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
1106 int MemOperand, const MCInst &MI,
1107 const MCInstrDesc &Desc,
1108 const MCSubtargetInfo &STI,
1109 raw_ostream &OS) const {
1111 // Emit the operand size opcode prefix as needed.
1112 unsigned char OpSize = (TSFlags & X86II::OpSizeMask) >> X86II::OpSizeShift;
1113 if (OpSize == (is16BitMode(STI) ? X86II::OpSize32 : X86II::OpSize16))
1114 EmitByte(0x66, CurByte, OS);
1116 switch (TSFlags & X86II::OpPrefixMask) {
1117 case X86II::PD: // 66
1118 EmitByte(0x66, CurByte, OS);
1120 case X86II::XS: // F3
1121 EmitByte(0xF3, CurByte, OS);
1123 case X86II::XD: // F2
1124 EmitByte(0xF2, CurByte, OS);
1128 // Handle REX prefix.
1129 // FIXME: Can this come before F2 etc to simplify emission?
1130 if (is64BitMode(STI)) {
1131 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
1132 EmitByte(0x40 | REX, CurByte, OS);
1135 // 0x0F escape code must be emitted just before the opcode.
1136 switch (TSFlags & X86II::OpMapMask) {
1137 case X86II::TB: // Two-byte opcode map
1138 case X86II::T8: // 0F 38
1139 case X86II::TA: // 0F 3A
1140 EmitByte(0x0F, CurByte, OS);
1144 switch (TSFlags & X86II::OpMapMask) {
1145 case X86II::T8: // 0F 38
1146 EmitByte(0x38, CurByte, OS);
1148 case X86II::TA: // 0F 3A
1149 EmitByte(0x3A, CurByte, OS);
1154 void X86MCCodeEmitter::
1155 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1156 SmallVectorImpl<MCFixup> &Fixups,
1157 const MCSubtargetInfo &STI) const {
1158 unsigned Opcode = MI.getOpcode();
1159 const MCInstrDesc &Desc = MCII.get(Opcode);
1160 uint64_t TSFlags = Desc.TSFlags;
1162 // Pseudo instructions don't get encoded.
1163 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
1166 unsigned NumOps = Desc.getNumOperands();
1167 unsigned CurOp = X86II::getOperandBias(Desc);
1169 // Keep track of the current byte being emitted.
1170 unsigned CurByte = 0;
1172 // Encoding type for this instruction.
1173 unsigned char Encoding = (TSFlags & X86II::EncodingMask) >>
1174 X86II::EncodingShift;
1176 // It uses the VEX.VVVV field?
1177 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
1178 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
1179 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
1180 const unsigned MemOp4_I8IMMOperand = 2;
1182 // It uses the EVEX.aaa field?
1183 bool HasEVEX_K = ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
1184 bool HasEVEX_RC = ((TSFlags >> X86II::VEXShift) & X86II::EVEX_RC);
1186 // Determine where the memory operand starts, if present.
1187 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
1188 if (MemoryOperand != -1) MemoryOperand += CurOp;
1190 // Emit the lock opcode prefix as needed.
1191 if (TSFlags & X86II::LOCK)
1192 EmitByte(0xF0, CurByte, OS);
1194 // Emit segment override opcode prefix as needed.
1195 if (MemoryOperand >= 0)
1196 EmitSegmentOverridePrefix(CurByte, MemoryOperand+X86::AddrSegmentReg,
1199 // Emit the repeat opcode prefix as needed.
1200 if (TSFlags & X86II::REP)
1201 EmitByte(0xF3, CurByte, OS);
1203 // Emit the address size opcode prefix as needed.
1204 bool need_address_override;
1205 // The AdSize prefix is only for 32-bit and 64-bit modes. Hm, perhaps we
1206 // should introduce an AdSize16 bit instead of having seven special cases?
1207 if ((!is16BitMode(STI) && TSFlags & X86II::AdSize) ||
1208 (is16BitMode(STI) && (MI.getOpcode() == X86::JECXZ_32 ||
1209 MI.getOpcode() == X86::MOV8o8a ||
1210 MI.getOpcode() == X86::MOV16o16a ||
1211 MI.getOpcode() == X86::MOV32o32a ||
1212 MI.getOpcode() == X86::MOV8ao8 ||
1213 MI.getOpcode() == X86::MOV16ao16 ||
1214 MI.getOpcode() == X86::MOV32ao32))) {
1215 need_address_override = true;
1216 } else if (MemoryOperand < 0) {
1217 need_address_override = false;
1218 } else if (is64BitMode(STI)) {
1219 assert(!Is16BitMemOperand(MI, MemoryOperand, STI));
1220 need_address_override = Is32BitMemOperand(MI, MemoryOperand);
1221 } else if (is32BitMode(STI)) {
1222 assert(!Is64BitMemOperand(MI, MemoryOperand));
1223 need_address_override = Is16BitMemOperand(MI, MemoryOperand, STI);
1225 assert(is16BitMode(STI));
1226 assert(!Is64BitMemOperand(MI, MemoryOperand));
1227 need_address_override = !Is16BitMemOperand(MI, MemoryOperand, STI);
1230 if (need_address_override)
1231 EmitByte(0x67, CurByte, OS);
1234 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS);
1236 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1238 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1240 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1241 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1243 unsigned SrcRegNum = 0;
1244 switch (TSFlags & X86II::FormMask) {
1245 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
1246 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1248 llvm_unreachable("Pseudo instruction shouldn't be emitted");
1249 case X86II::RawFrmDstSrc: {
1250 unsigned siReg = MI.getOperand(1).getReg();
1251 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) ||
1252 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) ||
1253 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&
1254 "SI and DI register sizes do not match");
1255 // Emit segment override opcode prefix as needed (not for %ds).
1256 if (MI.getOperand(2).getReg() != X86::DS)
1257 EmitSegmentOverridePrefix(CurByte, 2, MI, OS);
1258 // Emit AdSize prefix as needed.
1259 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1260 (is32BitMode(STI) && siReg == X86::SI))
1261 EmitByte(0x67, CurByte, OS);
1262 CurOp += 3; // Consume operands.
1263 EmitByte(BaseOpcode, CurByte, OS);
1266 case X86II::RawFrmSrc: {
1267 unsigned siReg = MI.getOperand(0).getReg();
1268 // Emit segment override opcode prefix as needed (not for %ds).
1269 if (MI.getOperand(1).getReg() != X86::DS)
1270 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1271 // Emit AdSize prefix as needed.
1272 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1273 (is32BitMode(STI) && siReg == X86::SI))
1274 EmitByte(0x67, CurByte, OS);
1275 CurOp += 2; // Consume operands.
1276 EmitByte(BaseOpcode, CurByte, OS);
1279 case X86II::RawFrmDst: {
1280 unsigned siReg = MI.getOperand(0).getReg();
1281 // Emit AdSize prefix as needed.
1282 if ((!is32BitMode(STI) && siReg == X86::EDI) ||
1283 (is32BitMode(STI) && siReg == X86::DI))
1284 EmitByte(0x67, CurByte, OS);
1285 ++CurOp; // Consume operand.
1286 EmitByte(BaseOpcode, CurByte, OS);
1290 EmitByte(BaseOpcode, CurByte, OS);
1292 case X86II::RawFrmMemOffs:
1293 // Emit segment override opcode prefix as needed.
1294 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1295 EmitByte(BaseOpcode, CurByte, OS);
1296 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1297 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1298 CurByte, OS, Fixups);
1299 ++CurOp; // skip segment operand
1301 case X86II::RawFrmImm8:
1302 EmitByte(BaseOpcode, CurByte, OS);
1303 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1304 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1305 CurByte, OS, Fixups);
1306 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte,
1309 case X86II::RawFrmImm16:
1310 EmitByte(BaseOpcode, CurByte, OS);
1311 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1312 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1313 CurByte, OS, Fixups);
1314 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte,
1318 case X86II::AddRegFrm:
1319 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
1322 case X86II::MRMDestReg:
1323 EmitByte(BaseOpcode, CurByte, OS);
1324 SrcRegNum = CurOp + 1;
1326 if (HasEVEX_K) // Skip writemask
1329 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1332 EmitRegModRMByte(MI.getOperand(CurOp),
1333 GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS);
1334 CurOp = SrcRegNum + 1;
1337 case X86II::MRMDestMem:
1338 EmitByte(BaseOpcode, CurByte, OS);
1339 SrcRegNum = CurOp + X86::AddrNumOperands;
1341 if (HasEVEX_K) // Skip writemask
1344 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1347 EmitMemModRMByte(MI, CurOp,
1348 GetX86RegNum(MI.getOperand(SrcRegNum)),
1349 TSFlags, CurByte, OS, Fixups, STI);
1350 CurOp = SrcRegNum + 1;
1353 case X86II::MRMSrcReg:
1354 EmitByte(BaseOpcode, CurByte, OS);
1355 SrcRegNum = CurOp + 1;
1357 if (HasEVEX_K) // Skip writemask
1360 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1363 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
1366 EmitRegModRMByte(MI.getOperand(SrcRegNum),
1367 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1369 // 2 operands skipped with HasMemOp4, compensate accordingly
1370 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
1373 // do not count the rounding control operand
1378 case X86II::MRMSrcMem: {
1379 int AddrOperands = X86::AddrNumOperands;
1380 unsigned FirstMemOp = CurOp+1;
1382 if (HasEVEX_K) { // Skip writemask
1389 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1391 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
1394 EmitByte(BaseOpcode, CurByte, OS);
1396 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1397 TSFlags, CurByte, OS, Fixups, STI);
1398 CurOp += AddrOperands + 1;
1405 case X86II::MRM0r: case X86II::MRM1r:
1406 case X86II::MRM2r: case X86II::MRM3r:
1407 case X86II::MRM4r: case X86II::MRM5r:
1408 case X86II::MRM6r: case X86II::MRM7r: {
1409 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1411 if (HasEVEX_K) // Skip writemask
1413 EmitByte(BaseOpcode, CurByte, OS);
1414 uint64_t Form = TSFlags & X86II::FormMask;
1415 EmitRegModRMByte(MI.getOperand(CurOp++),
1416 (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r,
1422 case X86II::MRM0m: case X86II::MRM1m:
1423 case X86II::MRM2m: case X86II::MRM3m:
1424 case X86II::MRM4m: case X86II::MRM5m:
1425 case X86II::MRM6m: case X86II::MRM7m: {
1426 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1428 if (HasEVEX_K) // Skip writemask
1430 EmitByte(BaseOpcode, CurByte, OS);
1431 uint64_t Form = TSFlags & X86II::FormMask;
1432 EmitMemModRMByte(MI, CurOp, (Form == X86II::MRMXm) ? 0 : Form-X86II::MRM0m,
1433 TSFlags, CurByte, OS, Fixups, STI);
1434 CurOp += X86::AddrNumOperands;
1437 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
1438 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8:
1439 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
1440 case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
1441 case X86II::MRM_D4: case X86II::MRM_D5: case X86II::MRM_D6:
1442 case X86II::MRM_D7: case X86II::MRM_D8: case X86II::MRM_D9:
1443 case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC:
1444 case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF:
1445 case X86II::MRM_E0: case X86II::MRM_E1: case X86II::MRM_E2:
1446 case X86II::MRM_E3: case X86II::MRM_E4: case X86II::MRM_E5:
1447 case X86II::MRM_E8: case X86II::MRM_E9: case X86II::MRM_EA:
1448 case X86II::MRM_EB: case X86II::MRM_EC: case X86II::MRM_ED:
1449 case X86II::MRM_EE: case X86II::MRM_F0: case X86II::MRM_F1:
1450 case X86II::MRM_F2: case X86II::MRM_F3: case X86II::MRM_F4:
1451 case X86II::MRM_F5: case X86II::MRM_F6: case X86II::MRM_F7:
1452 case X86II::MRM_F8: case X86II::MRM_F9: case X86II::MRM_FA:
1453 case X86II::MRM_FB: case X86II::MRM_FC: case X86II::MRM_FD:
1454 case X86II::MRM_FE: case X86II::MRM_FF:
1455 EmitByte(BaseOpcode, CurByte, OS);
1458 switch (TSFlags & X86II::FormMask) {
1459 default: llvm_unreachable("Invalid Form");
1460 case X86II::MRM_C0: MRM = 0xC0; break;
1461 case X86II::MRM_C1: MRM = 0xC1; break;
1462 case X86II::MRM_C2: MRM = 0xC2; break;
1463 case X86II::MRM_C3: MRM = 0xC3; break;
1464 case X86II::MRM_C4: MRM = 0xC4; break;
1465 case X86II::MRM_C8: MRM = 0xC8; break;
1466 case X86II::MRM_C9: MRM = 0xC9; break;
1467 case X86II::MRM_CA: MRM = 0xCA; break;
1468 case X86II::MRM_CB: MRM = 0xCB; break;
1469 case X86II::MRM_CF: MRM = 0xCF; break;
1470 case X86II::MRM_D0: MRM = 0xD0; break;
1471 case X86II::MRM_D1: MRM = 0xD1; break;
1472 case X86II::MRM_D4: MRM = 0xD4; break;
1473 case X86II::MRM_D5: MRM = 0xD5; break;
1474 case X86II::MRM_D6: MRM = 0xD6; break;
1475 case X86II::MRM_D7: MRM = 0xD7; break;
1476 case X86II::MRM_D8: MRM = 0xD8; break;
1477 case X86II::MRM_D9: MRM = 0xD9; break;
1478 case X86II::MRM_DA: MRM = 0xDA; break;
1479 case X86II::MRM_DB: MRM = 0xDB; break;
1480 case X86II::MRM_DC: MRM = 0xDC; break;
1481 case X86II::MRM_DD: MRM = 0xDD; break;
1482 case X86II::MRM_DE: MRM = 0xDE; break;
1483 case X86II::MRM_DF: MRM = 0xDF; break;
1484 case X86II::MRM_E0: MRM = 0xE0; break;
1485 case X86II::MRM_E1: MRM = 0xE1; break;
1486 case X86II::MRM_E2: MRM = 0xE2; break;
1487 case X86II::MRM_E3: MRM = 0xE3; break;
1488 case X86II::MRM_E4: MRM = 0xE4; break;
1489 case X86II::MRM_E5: MRM = 0xE5; break;
1490 case X86II::MRM_E8: MRM = 0xE8; break;
1491 case X86II::MRM_E9: MRM = 0xE9; break;
1492 case X86II::MRM_EA: MRM = 0xEA; break;
1493 case X86II::MRM_EB: MRM = 0xEB; break;
1494 case X86II::MRM_EC: MRM = 0xEC; break;
1495 case X86II::MRM_ED: MRM = 0xED; break;
1496 case X86II::MRM_EE: MRM = 0xEE; break;
1497 case X86II::MRM_F0: MRM = 0xF0; break;
1498 case X86II::MRM_F1: MRM = 0xF1; break;
1499 case X86II::MRM_F2: MRM = 0xF2; break;
1500 case X86II::MRM_F3: MRM = 0xF3; break;
1501 case X86II::MRM_F4: MRM = 0xF4; break;
1502 case X86II::MRM_F5: MRM = 0xF5; break;
1503 case X86II::MRM_F6: MRM = 0xF6; break;
1504 case X86II::MRM_F7: MRM = 0xF7; break;
1505 case X86II::MRM_F8: MRM = 0xF8; break;
1506 case X86II::MRM_F9: MRM = 0xF9; break;
1507 case X86II::MRM_FA: MRM = 0xFA; break;
1508 case X86II::MRM_FB: MRM = 0xFB; break;
1509 case X86II::MRM_FC: MRM = 0xFC; break;
1510 case X86II::MRM_FD: MRM = 0xFD; break;
1511 case X86II::MRM_FE: MRM = 0xFE; break;
1512 case X86II::MRM_FF: MRM = 0xFF; break;
1514 EmitByte(MRM, CurByte, OS);
1518 // If there is a remaining operand, it must be a trailing immediate. Emit it
1519 // according to the right size for the instruction. Some instructions
1520 // (SSE4a extrq and insertq) have two trailing immediates.
1521 while (CurOp != NumOps && NumOps - CurOp <= 2) {
1522 // The last source register of a 4 operand instruction in AVX is encoded
1523 // in bits[7:4] of a immediate byte.
1524 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
1525 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
1528 unsigned RegNum = GetX86RegNum(MO) << 4;
1529 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1531 // If there is an additional 5th operand it must be an immediate, which
1532 // is encoded in bits[3:0]
1533 if (CurOp != NumOps) {
1534 const MCOperand &MIMM = MI.getOperand(CurOp++);
1536 unsigned Val = MIMM.getImm();
1537 assert(Val < 16 && "Immediate operand value out of range");
1541 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1,
1542 CurByte, OS, Fixups);
1544 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1545 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1546 CurByte, OS, Fixups);
1550 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1551 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1555 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1556 errs() << "Cannot encode all operands of: ";