1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/X86MCTargetDesc.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "MCTargetDesc/X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCSymbol.h"
26 #include "llvm/Support/raw_ostream.h"
31 class X86MCCodeEmitter : public MCCodeEmitter {
32 X86MCCodeEmitter(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION;
33 void operator=(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION;
34 const MCInstrInfo &MCII;
37 X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
38 : MCII(mcii), Ctx(ctx) {
41 ~X86MCCodeEmitter() {}
43 bool is64BitMode(const MCSubtargetInfo &STI) const {
44 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
47 bool is32BitMode(const MCSubtargetInfo &STI) const {
48 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
51 bool is16BitMode(const MCSubtargetInfo &STI) const {
52 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
55 /// Is16BitMemOperand - Return true if the specified instruction has
56 /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
57 bool Is16BitMemOperand(const MCInst &MI, unsigned Op,
58 const MCSubtargetInfo &STI) const {
59 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
60 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
61 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
63 if (is16BitMode(STI) && BaseReg.getReg() == 0 &&
64 Disp.isImm() && Disp.getImm() < 0x10000)
66 if ((BaseReg.getReg() != 0 &&
67 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
68 (IndexReg.getReg() != 0 &&
69 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
74 unsigned GetX86RegNum(const MCOperand &MO) const {
75 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
78 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
79 // 0-7 and the difference between the 2 groups is given by the REX prefix.
80 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
81 // in 1's complement form, example:
83 // ModRM field => XMM9 => 1
84 // VEX.VVVV => XMM9 => ~9
86 // See table 4-35 of Intel AVX Programming Reference for details.
87 unsigned char getVEXRegisterEncoding(const MCInst &MI,
88 unsigned OpNum) const {
89 unsigned SrcReg = MI.getOperand(OpNum).getReg();
90 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
91 if (X86II::isX86_64ExtendedReg(SrcReg))
94 // The registers represented through VEX_VVVV should
95 // be encoded in 1's complement form.
96 return (~SrcRegNum) & 0xf;
99 unsigned char getWriteMaskRegisterEncoding(const MCInst &MI,
100 unsigned OpNum) const {
101 assert(X86::K0 != MI.getOperand(OpNum).getReg() &&
102 "Invalid mask register as write-mask!");
103 unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum));
107 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
112 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
113 raw_ostream &OS) const {
114 // Output the constant in little endian byte order.
115 for (unsigned i = 0; i != Size; ++i) {
116 EmitByte(Val & 255, CurByte, OS);
121 void EmitImmediate(const MCOperand &Disp, SMLoc Loc,
122 unsigned ImmSize, MCFixupKind FixupKind,
123 unsigned &CurByte, raw_ostream &OS,
124 SmallVectorImpl<MCFixup> &Fixups,
125 int ImmOffset = 0) const;
127 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
129 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
130 return RM | (RegOpcode << 3) | (Mod << 6);
133 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
134 unsigned &CurByte, raw_ostream &OS) const {
135 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
138 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
139 unsigned &CurByte, raw_ostream &OS) const {
140 // SIB byte is in the same format as the ModRMByte.
141 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
145 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
146 unsigned RegOpcodeField,
147 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
148 SmallVectorImpl<MCFixup> &Fixups,
149 const MCSubtargetInfo &STI) const;
151 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
152 SmallVectorImpl<MCFixup> &Fixups,
153 const MCSubtargetInfo &STI) const;
155 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
156 const MCInst &MI, const MCInstrDesc &Desc,
157 raw_ostream &OS) const;
159 void EmitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand,
160 const MCInst &MI, raw_ostream &OS) const;
162 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
163 const MCInst &MI, const MCInstrDesc &Desc,
164 const MCSubtargetInfo &STI,
165 raw_ostream &OS) const;
168 } // end anonymous namespace
171 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
172 const MCRegisterInfo &MRI,
173 const MCSubtargetInfo &STI,
175 return new X86MCCodeEmitter(MCII, Ctx);
178 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
179 /// sign-extended field.
180 static bool isDisp8(int Value) {
181 return Value == (signed char)Value;
184 /// isCDisp8 - Return true if this signed displacement fits in a 8-bit
185 /// compressed dispacement field.
186 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
187 assert(((TSFlags >> X86II::VEXShift) & X86II::EVEX) &&
188 "Compressed 8-bit displacement is only valid for EVEX inst.");
190 unsigned CD8E = (TSFlags >> X86II::EVEX_CD8EShift) & X86II::EVEX_CD8EMask;
191 unsigned CD8V = (TSFlags >> X86II::EVEX_CD8VShift) & X86II::EVEX_CD8VMask;
193 if (CD8V == 0 && CD8E == 0) {
195 return isDisp8(Value);
198 unsigned MemObjSize = 1U << CD8E;
200 // Fixed vector length
201 MemObjSize *= 1U << (CD8V & 0x3);
203 // Modified vector length
204 bool EVEX_b = (TSFlags >> X86II::VEXShift) & X86II::EVEX_B;
206 unsigned EVEX_LL = ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) ? 1 : 0;
207 EVEX_LL += ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2) ? 2 : 0;
208 assert(EVEX_LL < 3 && "");
210 unsigned NumElems = (1U << (EVEX_LL + 4)) / MemObjSize;
211 NumElems /= 1U << (CD8V & 0x3);
213 MemObjSize *= NumElems;
217 unsigned MemObjMask = MemObjSize - 1;
218 assert((MemObjSize & MemObjMask) == 0 && "Invalid memory object size.");
220 if (Value & MemObjMask) // Unaligned offset
223 bool Ret = (Value == (signed char)Value);
230 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
231 /// in an instruction with the specified TSFlags.
232 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
233 unsigned Size = X86II::getSizeOfImm(TSFlags);
234 bool isPCRel = X86II::isImmPCRel(TSFlags);
236 if (X86II::isImmSigned(TSFlags)) {
238 default: llvm_unreachable("Unsupported signed fixup size!");
239 case 4: return MCFixupKind(X86::reloc_signed_4byte);
242 return MCFixup::getKindForSize(Size, isPCRel);
245 /// Is32BitMemOperand - Return true if the specified instruction has
246 /// a 32-bit memory operand. Op specifies the operand # of the memoperand.
247 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
248 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
249 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
251 if ((BaseReg.getReg() != 0 &&
252 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
253 (IndexReg.getReg() != 0 &&
254 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
259 /// Is64BitMemOperand - Return true if the specified instruction has
260 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
262 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
263 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
264 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
266 if ((BaseReg.getReg() != 0 &&
267 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
268 (IndexReg.getReg() != 0 &&
269 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
275 /// StartsWithGlobalOffsetTable - Check if this expression starts with
276 /// _GLOBAL_OFFSET_TABLE_ and if it is of the form
277 /// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF
278 /// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
279 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
280 /// of a binary expression.
281 enum GlobalOffsetTableExprKind {
286 static GlobalOffsetTableExprKind
287 StartsWithGlobalOffsetTable(const MCExpr *Expr) {
288 const MCExpr *RHS = 0;
289 if (Expr->getKind() == MCExpr::Binary) {
290 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
295 if (Expr->getKind() != MCExpr::SymbolRef)
298 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
299 const MCSymbol &S = Ref->getSymbol();
300 if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
302 if (RHS && RHS->getKind() == MCExpr::SymbolRef)
307 static bool HasSecRelSymbolRef(const MCExpr *Expr) {
308 if (Expr->getKind() == MCExpr::SymbolRef) {
309 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
310 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL;
315 void X86MCCodeEmitter::
316 EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size,
317 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS,
318 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
319 const MCExpr *Expr = NULL;
320 if (DispOp.isImm()) {
321 // If this is a simple integer displacement that doesn't require a
322 // relocation, emit it now.
323 if (FixupKind != FK_PCRel_1 &&
324 FixupKind != FK_PCRel_2 &&
325 FixupKind != FK_PCRel_4) {
326 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
329 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx);
331 Expr = DispOp.getExpr();
334 // If we have an immoffset, add it to the expression.
335 if ((FixupKind == FK_Data_4 ||
336 FixupKind == FK_Data_8 ||
337 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
338 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr);
339 if (Kind != GOT_None) {
340 assert(ImmOffset == 0);
342 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
343 if (Kind == GOT_Normal)
345 } else if (Expr->getKind() == MCExpr::SymbolRef) {
346 if (HasSecRelSymbolRef(Expr)) {
347 FixupKind = MCFixupKind(FK_SecRel_4);
349 } else if (Expr->getKind() == MCExpr::Binary) {
350 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr);
351 if (HasSecRelSymbolRef(Bin->getLHS())
352 || HasSecRelSymbolRef(Bin->getRHS())) {
353 FixupKind = MCFixupKind(FK_SecRel_4);
358 // If the fixup is pc-relative, we need to bias the value to be relative to
359 // the start of the field, not the end of the field.
360 if (FixupKind == FK_PCRel_4 ||
361 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
362 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
364 if (FixupKind == FK_PCRel_2)
366 if (FixupKind == FK_PCRel_1)
370 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
373 // Emit a symbolic constant as a fixup and 4 zeros.
374 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc));
375 EmitConstant(0, Size, CurByte, OS);
378 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
379 unsigned RegOpcodeField,
380 uint64_t TSFlags, unsigned &CurByte,
382 SmallVectorImpl<MCFixup> &Fixups,
383 const MCSubtargetInfo &STI) const{
384 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
385 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
386 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
387 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
388 unsigned BaseReg = Base.getReg();
389 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
391 // Handle %rip relative addressing.
392 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
393 assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode");
394 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
395 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
397 unsigned FixupKind = X86::reloc_riprel_4byte;
399 // movq loads are handled with a special relocation form which allows the
400 // linker to eliminate some loads for GOT references which end up in the
401 // same linkage unit.
402 if (MI.getOpcode() == X86::MOV64rm)
403 FixupKind = X86::reloc_riprel_4byte_movq_load;
405 // rip-relative addressing is actually relative to the *next* instruction.
406 // Since an immediate can follow the mod/rm byte for an instruction, this
407 // means that we need to bias the immediate field of the instruction with
408 // the size of the immediate field. If we have this case, add it into the
409 // expression to emit.
410 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
412 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind),
413 CurByte, OS, Fixups, -ImmSize);
417 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
419 // 16-bit addressing forms of the ModR/M byte have a different encoding for
420 // the R/M field and are far more limited in which registers can be used.
421 if (Is16BitMemOperand(MI, Op, STI)) {
423 // For 32-bit addressing, the row and column values in Table 2-2 are
424 // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
425 // some special cases. And GetX86RegNum reflects that numbering.
426 // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
427 // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
428 // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
429 // while values 0-3 indicate the allowed combinations (base+index) of
430 // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
432 // R16Table[] is a lookup from the normal RegNo, to the row values from
433 // Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
434 static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 };
435 unsigned RMfield = R16Table[BaseRegNo];
437 assert(RMfield && "invalid 16-bit base register");
439 if (IndexReg.getReg()) {
440 unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)];
442 assert(IndexReg16 && "invalid 16-bit index register");
443 // We must have one of SI/DI (4,5), and one of BP/BX (6,7).
444 assert(((IndexReg16 ^ RMfield) & 2) &&
445 "invalid 16-bit base/index register combination");
446 assert(Scale.getImm() == 1 &&
447 "invalid scale for 16-bit memory reference");
449 // Allow base/index to appear in either order (although GAS doesn't).
451 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
453 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
456 if (Disp.isImm() && isDisp8(Disp.getImm())) {
457 if (Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
458 // There is no displacement; just the register.
459 EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS);
462 // Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
463 EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS);
464 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
467 // This is the [REG]+disp16 case.
468 EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS);
470 // There is no BaseReg; this is the plain [disp16] case.
471 EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS);
474 // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
475 EmitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups);
479 // Determine whether a SIB byte is needed.
480 // If no BaseReg, issue a RIP relative instruction only if the MCE can
481 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
482 // 2-7) and absolute references.
484 if (// The SIB byte must be used if there is an index register.
485 IndexReg.getReg() == 0 &&
486 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
487 // encode to an R/M value of 4, which indicates that a SIB byte is
489 BaseRegNo != N86::ESP &&
490 // If there is no base register and we're in 64-bit mode, we need a SIB
491 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
492 (!is64BitMode(STI) || BaseReg != 0)) {
494 if (BaseReg == 0) { // [disp32] in X86-32 mode
495 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
496 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups);
500 // If the base is not EBP/ESP and there is no displacement, use simple
501 // indirect register encoding, this handles addresses like [EAX]. The
502 // encoding for [EBP] with no displacement means [disp32] so we handle it
503 // by emitting a displacement of 0 below.
504 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
505 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
509 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
511 if (!HasEVEX && isDisp8(Disp.getImm())) {
512 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
513 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
516 // Try EVEX compressed 8-bit displacement first; if failed, fall back to
517 // 32-bit displacement.
519 if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
520 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
521 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups,
522 CDisp8 - Disp.getImm());
527 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
528 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
529 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
534 // We need a SIB byte, so start by outputting the ModR/M byte first
535 assert(IndexReg.getReg() != X86::ESP &&
536 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
538 bool ForceDisp32 = false;
539 bool ForceDisp8 = false;
543 // If there is no base register, we emit the special case SIB byte with
544 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
545 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
547 } else if (!Disp.isImm()) {
548 // Emit the normal disp32 encoding.
549 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
551 } else if (Disp.getImm() == 0 &&
552 // Base reg can't be anything that ends up with '5' as the base
553 // reg, it is the magic [*] nomenclature that indicates no base.
554 BaseRegNo != N86::EBP) {
555 // Emit no displacement ModR/M byte
556 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
557 } else if (!HasEVEX && isDisp8(Disp.getImm())) {
558 // Emit the disp8 encoding.
559 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
560 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
561 } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
562 // Emit the disp8 encoding.
563 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
564 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
565 ImmOffset = CDisp8 - Disp.getImm();
567 // Emit the normal disp32 encoding.
568 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
571 // Calculate what the SS field value should be...
572 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
573 unsigned SS = SSTable[Scale.getImm()];
576 // Handle the SIB byte for the case where there is no base, see Intel
577 // Manual 2A, table 2-7. The displacement has already been output.
579 if (IndexReg.getReg())
580 IndexRegNo = GetX86RegNum(IndexReg);
581 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
583 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
586 if (IndexReg.getReg())
587 IndexRegNo = GetX86RegNum(IndexReg);
589 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
590 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
593 // Do we need to output a displacement?
595 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset);
596 else if (ForceDisp32 || Disp.getImm() != 0)
597 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
598 CurByte, OS, Fixups);
601 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
603 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
604 int MemOperand, const MCInst &MI,
605 const MCInstrDesc &Desc,
606 raw_ostream &OS) const {
607 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
608 bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
609 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
610 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
611 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
612 bool HasEVEX_RC = (TSFlags >> X86II::VEXShift) & X86II::EVEX_RC;
614 // VEX_R: opcode externsion equivalent to REX.R in
615 // 1's complement (inverted) form
617 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
618 // 0: Same as REX_R=1 (64 bit mode only)
620 unsigned char VEX_R = 0x1;
621 unsigned char EVEX_R2 = 0x1;
623 // VEX_X: equivalent to REX.X, only used when a
624 // register is used for index in SIB Byte.
626 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
627 // 0: Same as REX.X=1 (64-bit mode only)
628 unsigned char VEX_X = 0x1;
632 // 1: Same as REX_B=0 (ignored in 32-bit mode)
633 // 0: Same as REX_B=1 (64 bit mode only)
635 unsigned char VEX_B = 0x1;
637 // VEX_W: opcode specific (use like REX.W, or used for
638 // opcode extension, or ignored, depending on the opcode byte)
639 unsigned char VEX_W = 0;
641 // XOP: Use XOP prefix byte 0x8f instead of VEX.
642 bool XOP = (TSFlags >> X86II::VEXShift) & X86II::XOP;
644 // VEX_5M (VEX m-mmmmm field):
646 // 0b00000: Reserved for future use
647 // 0b00001: implied 0F leading opcode
648 // 0b00010: implied 0F 38 leading opcode bytes
649 // 0b00011: implied 0F 3A leading opcode bytes
650 // 0b00100-0b11111: Reserved for future use
651 // 0b01000: XOP map select - 08h instructions with imm byte
652 // 0b01001: XOP map select - 09h instructions with no imm byte
653 // 0b01010: XOP map select - 0Ah instructions with imm dword
654 unsigned char VEX_5M = 0x1;
656 // VEX_4V (VEX vvvv field): a register specifier
657 // (in 1's complement form) or 1111 if unused.
658 unsigned char VEX_4V = 0xf;
659 unsigned char EVEX_V2 = 0x1;
661 // VEX_L (Vector Length):
663 // 0: scalar or 128-bit vector
666 unsigned char VEX_L = 0;
667 unsigned char EVEX_L2 = 0;
669 // VEX_PP: opcode extension providing equivalent
670 // functionality of a SIMD prefix
677 unsigned char VEX_PP = 0;
680 unsigned char EVEX_U = 1; // Always '1' so far
683 unsigned char EVEX_z = 0;
686 unsigned char EVEX_b = 0;
689 unsigned char EVEX_rc = 0;
692 unsigned char EVEX_aaa = 0;
694 bool EncodeRC = false;
696 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
699 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
701 if (HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2))
704 if (HasEVEX_K && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_Z))
707 if (HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_B))
710 switch (TSFlags & X86II::Op0Mask) {
711 default: llvm_unreachable("Invalid prefix!");
712 case X86II::T8: // 0F 38
715 case X86II::TA: // 0F 3A
718 case X86II::T8PD: // 66 0F 38
722 case X86II::T8XS: // F3 0F 38
726 case X86II::T8XD: // F2 0F 38
730 case X86II::TAPD: // 66 0F 3A
734 case X86II::TAXD: // F2 0F 3A
738 case X86II::PD: // 66 0F
741 case X86II::XS: // F3 0F
744 case X86II::XD: // F2 0F
756 case X86II::TB: // VEX_5M/VEX_PP already correct
761 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
762 unsigned NumOps = Desc.getNumOperands();
763 unsigned CurOp = X86II::getOperandBias(Desc);
765 switch (TSFlags & X86II::FormMask) {
766 default: llvm_unreachable("Unexpected form in EmitVEXOpcodePrefix!");
769 case X86II::MRMDestMem: {
770 // MRMDestMem instructions forms:
771 // MemAddr, src1(ModR/M)
772 // MemAddr, src1(VEX_4V), src2(ModR/M)
773 // MemAddr, src1(ModR/M), imm8
775 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
776 X86::AddrBaseReg).getReg()))
778 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
779 X86::AddrIndexReg).getReg()))
781 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(MemOperand +
782 X86::AddrIndexReg).getReg()))
785 CurOp += X86::AddrNumOperands;
788 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
791 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
792 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
797 const MCOperand &MO = MI.getOperand(CurOp);
799 if (X86II::isX86_64ExtendedReg(MO.getReg()))
801 if (HasEVEX && X86II::is32ExtendedReg(MO.getReg()))
806 case X86II::MRMSrcMem:
807 // MRMSrcMem instructions forms:
808 // src1(ModR/M), MemAddr
809 // src1(ModR/M), src2(VEX_4V), MemAddr
810 // src1(ModR/M), MemAddr, imm8
811 // src1(ModR/M), MemAddr, src2(VEX_I8IMM)
814 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
815 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
816 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
818 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
823 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
826 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
827 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
832 if (X86II::isX86_64ExtendedReg(
833 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
835 if (X86II::isX86_64ExtendedReg(
836 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
838 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(MemOperand +
839 X86::AddrIndexReg).getReg()))
843 // Instruction format for 4VOp3:
844 // src1(ModR/M), MemAddr, src3(VEX_4V)
845 // CurOp points to start of the MemoryOperand,
846 // it skips TIED_TO operands if exist, then increments past src1.
847 // CurOp + X86::AddrNumOperands will point to src3.
848 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands);
850 case X86II::MRM0m: case X86II::MRM1m:
851 case X86II::MRM2m: case X86II::MRM3m:
852 case X86II::MRM4m: case X86II::MRM5m:
853 case X86II::MRM6m: case X86II::MRM7m: {
854 // MRM[0-9]m instructions forms:
856 // src1(VEX_4V), MemAddr
858 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
859 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
865 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
867 if (X86II::isX86_64ExtendedReg(
868 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
870 if (X86II::isX86_64ExtendedReg(
871 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
875 case X86II::MRMSrcReg:
876 // MRMSrcReg instructions forms:
877 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
878 // dst(ModR/M), src1(ModR/M)
879 // dst(ModR/M), src1(ModR/M), imm8
882 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
883 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
884 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
886 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
891 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
894 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
895 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
900 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
903 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
905 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
909 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
912 unsigned RcOperand = NumOps-1;
913 assert(RcOperand >= CurOp);
914 EVEX_rc = MI.getOperand(RcOperand).getImm() & 0x3;
919 case X86II::MRMDestReg:
920 // MRMDestReg instructions forms:
921 // dst(ModR/M), src(ModR/M)
922 // dst(ModR/M), src(ModR/M), imm8
923 // dst(ModR/M), src1(VEX_4V), src2(ModR/M)
924 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
926 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
931 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
934 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
935 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
940 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
942 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
947 case X86II::MRM0r: case X86II::MRM1r:
948 case X86II::MRM2r: case X86II::MRM3r:
949 case X86II::MRM4r: case X86II::MRM5r:
950 case X86II::MRM6r: case X86II::MRM7r:
951 // MRM0r-MRM7r instructions forms:
952 // dst(VEX_4V), src(ModR/M), imm8
954 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
955 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
960 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
962 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
964 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
970 // VEX opcode prefix can have 2 or 3 bytes
973 // +-----+ +--------------+ +-------------------+
974 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
975 // +-----+ +--------------+ +-------------------+
977 // +-----+ +-------------------+
978 // | C5h | | R | vvvv | L | pp |
979 // +-----+ +-------------------+
981 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
983 if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix
984 EmitByte(0xC5, CurByte, OS);
985 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
990 EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS);
991 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
992 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
994 // EVEX opcode prefix can have 4 bytes
996 // +-----+ +--------------+ +-------------------+ +------------------------+
997 // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
998 // +-----+ +--------------+ +-------------------+ +------------------------+
999 assert((VEX_5M & 0x3) == VEX_5M
1000 && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!");
1004 EmitByte(0x62, CurByte, OS);
1005 EmitByte((VEX_R << 7) |
1009 VEX_5M, CurByte, OS);
1010 EmitByte((VEX_W << 7) |
1013 VEX_PP, CurByte, OS);
1015 EmitByte((EVEX_z << 7) |
1019 EVEX_aaa, CurByte, OS);
1021 EmitByte((EVEX_z << 7) |
1026 EVEX_aaa, CurByte, OS);
1030 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
1031 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
1032 /// size, and 3) use of X86-64 extended registers.
1033 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
1034 const MCInstrDesc &Desc) {
1036 if (TSFlags & X86II::REX_W)
1037 REX |= 1 << 3; // set REX.W
1039 if (MI.getNumOperands() == 0) return REX;
1041 unsigned NumOps = MI.getNumOperands();
1042 // FIXME: MCInst should explicitize the two-addrness.
1043 bool isTwoAddr = NumOps > 1 &&
1044 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
1046 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
1047 unsigned i = isTwoAddr ? 1 : 0;
1048 for (; i != NumOps; ++i) {
1049 const MCOperand &MO = MI.getOperand(i);
1050 if (!MO.isReg()) continue;
1051 unsigned Reg = MO.getReg();
1052 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
1053 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
1054 // that returns non-zero.
1055 REX |= 0x40; // REX fixed encoding prefix
1059 switch (TSFlags & X86II::FormMask) {
1060 case X86II::MRMSrcReg:
1061 if (MI.getOperand(0).isReg() &&
1062 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1063 REX |= 1 << 2; // set REX.R
1064 i = isTwoAddr ? 2 : 1;
1065 for (; i != NumOps; ++i) {
1066 const MCOperand &MO = MI.getOperand(i);
1067 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
1068 REX |= 1 << 0; // set REX.B
1071 case X86II::MRMSrcMem: {
1072 if (MI.getOperand(0).isReg() &&
1073 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1074 REX |= 1 << 2; // set REX.R
1076 i = isTwoAddr ? 2 : 1;
1077 for (; i != NumOps; ++i) {
1078 const MCOperand &MO = MI.getOperand(i);
1080 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1081 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
1087 case X86II::MRM0m: case X86II::MRM1m:
1088 case X86II::MRM2m: case X86II::MRM3m:
1089 case X86II::MRM4m: case X86II::MRM5m:
1090 case X86II::MRM6m: case X86II::MRM7m:
1091 case X86II::MRMDestMem: {
1092 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
1093 i = isTwoAddr ? 1 : 0;
1094 if (NumOps > e && MI.getOperand(e).isReg() &&
1095 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
1096 REX |= 1 << 2; // set REX.R
1098 for (; i != e; ++i) {
1099 const MCOperand &MO = MI.getOperand(i);
1101 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1102 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
1109 if (MI.getOperand(0).isReg() &&
1110 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1111 REX |= 1 << 0; // set REX.B
1112 i = isTwoAddr ? 2 : 1;
1113 for (unsigned e = NumOps; i != e; ++i) {
1114 const MCOperand &MO = MI.getOperand(i);
1115 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
1116 REX |= 1 << 2; // set REX.R
1123 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
1124 void X86MCCodeEmitter::EmitSegmentOverridePrefix(unsigned &CurByte,
1125 unsigned SegOperand,
1127 raw_ostream &OS) const {
1128 // Check for explicit segment override on memory operand.
1129 switch (MI.getOperand(SegOperand).getReg()) {
1130 default: llvm_unreachable("Unknown segment register!");
1132 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
1133 case X86::SS: EmitByte(0x36, CurByte, OS); break;
1134 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
1135 case X86::ES: EmitByte(0x26, CurByte, OS); break;
1136 case X86::FS: EmitByte(0x64, CurByte, OS); break;
1137 case X86::GS: EmitByte(0x65, CurByte, OS); break;
1141 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
1143 /// MemOperand is the operand # of the start of a memory operand if present. If
1144 /// Not present, it is -1.
1145 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
1146 int MemOperand, const MCInst &MI,
1147 const MCInstrDesc &Desc,
1148 const MCSubtargetInfo &STI,
1149 raw_ostream &OS) const {
1151 // Emit the operand size opcode prefix as needed.
1152 if (TSFlags & (is16BitMode(STI) ? X86II::OpSize16 : X86II::OpSize))
1153 EmitByte(0x66, CurByte, OS);
1155 bool Need0FPrefix = false;
1156 switch (TSFlags & X86II::Op0Mask) {
1157 default: llvm_unreachable("Invalid prefix!");
1158 case 0: break; // No prefix!
1159 case X86II::REP: break; // already handled.
1160 case X86II::TB: // Two-byte opcode prefix
1161 case X86II::T8: // 0F 38
1162 case X86II::TA: // 0F 3A
1163 case X86II::A6: // 0F A6
1164 case X86II::A7: // 0F A7
1165 Need0FPrefix = true;
1167 case X86II::PD: // 66 0F
1168 case X86II::T8PD: // 66 0F 38
1169 case X86II::TAPD: // 66 0F 3A
1170 EmitByte(0x66, CurByte, OS);
1171 Need0FPrefix = true;
1173 case X86II::XS: // F3 0F
1174 case X86II::T8XS: // F3 0F 38
1175 EmitByte(0xF3, CurByte, OS);
1176 Need0FPrefix = true;
1178 case X86II::XD: // F2 0F
1179 case X86II::T8XD: // F2 0F 38
1180 case X86II::TAXD: // F2 0F 3A
1181 EmitByte(0xF2, CurByte, OS);
1182 Need0FPrefix = true;
1192 EmitByte(0xD8+(((TSFlags & X86II::Op0Mask) - X86II::D8) >> X86II::Op0Shift),
1197 // Handle REX prefix.
1198 // FIXME: Can this come before F2 etc to simplify emission?
1199 if (is64BitMode(STI)) {
1200 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
1201 EmitByte(0x40 | REX, CurByte, OS);
1204 // 0x0F escape code must be emitted just before the opcode.
1206 EmitByte(0x0F, CurByte, OS);
1208 // FIXME: Pull this up into previous switch if REX can be moved earlier.
1209 switch (TSFlags & X86II::Op0Mask) {
1210 case X86II::T8PD: // 66 0F 38
1211 case X86II::T8XS: // F3 0F 38
1212 case X86II::T8XD: // F2 0F 38
1213 case X86II::T8: // 0F 38
1214 EmitByte(0x38, CurByte, OS);
1216 case X86II::TAPD: // 66 0F 3A
1217 case X86II::TAXD: // F2 0F 3A
1218 case X86II::TA: // 0F 3A
1219 EmitByte(0x3A, CurByte, OS);
1221 case X86II::A6: // 0F A6
1222 EmitByte(0xA6, CurByte, OS);
1224 case X86II::A7: // 0F A7
1225 EmitByte(0xA7, CurByte, OS);
1230 void X86MCCodeEmitter::
1231 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1232 SmallVectorImpl<MCFixup> &Fixups,
1233 const MCSubtargetInfo &STI) const {
1234 unsigned Opcode = MI.getOpcode();
1235 const MCInstrDesc &Desc = MCII.get(Opcode);
1236 uint64_t TSFlags = Desc.TSFlags;
1238 // Pseudo instructions don't get encoded.
1239 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
1242 unsigned NumOps = Desc.getNumOperands();
1243 unsigned CurOp = X86II::getOperandBias(Desc);
1245 // Keep track of the current byte being emitted.
1246 unsigned CurByte = 0;
1248 // Is this instruction encoded using the AVX VEX prefix?
1249 bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX;
1251 // It uses the VEX.VVVV field?
1252 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
1253 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
1254 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
1255 const unsigned MemOp4_I8IMMOperand = 2;
1257 // It uses the EVEX.aaa field?
1258 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
1259 bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
1260 bool HasEVEX_RC = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_RC);
1262 // Determine where the memory operand starts, if present.
1263 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
1264 if (MemoryOperand != -1) MemoryOperand += CurOp;
1266 // Emit the lock opcode prefix as needed.
1267 if (TSFlags & X86II::LOCK)
1268 EmitByte(0xF0, CurByte, OS);
1270 // Emit segment override opcode prefix as needed.
1271 if (MemoryOperand >= 0)
1272 EmitSegmentOverridePrefix(CurByte, MemoryOperand+X86::AddrSegmentReg,
1275 // Emit the repeat opcode prefix as needed.
1276 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
1277 EmitByte(0xF3, CurByte, OS);
1279 // Emit the address size opcode prefix as needed.
1280 bool need_address_override;
1281 // The AdSize prefix is only for 32-bit and 64-bit modes. Hm, perhaps we
1282 // should introduce an AdSize16 bit instead of having seven special cases?
1283 if ((!is16BitMode(STI) && TSFlags & X86II::AdSize) ||
1284 (is16BitMode(STI) && (MI.getOpcode() == X86::JECXZ_32 ||
1285 MI.getOpcode() == X86::MOV8o8a ||
1286 MI.getOpcode() == X86::MOV16o16a ||
1287 MI.getOpcode() == X86::MOV32o32a ||
1288 MI.getOpcode() == X86::MOV8ao8 ||
1289 MI.getOpcode() == X86::MOV16ao16 ||
1290 MI.getOpcode() == X86::MOV32ao32))) {
1291 need_address_override = true;
1292 } else if (MemoryOperand < 0) {
1293 need_address_override = false;
1294 } else if (is64BitMode(STI)) {
1295 assert(!Is16BitMemOperand(MI, MemoryOperand, STI));
1296 need_address_override = Is32BitMemOperand(MI, MemoryOperand);
1297 } else if (is32BitMode(STI)) {
1298 assert(!Is64BitMemOperand(MI, MemoryOperand));
1299 need_address_override = Is16BitMemOperand(MI, MemoryOperand, STI);
1301 assert(is16BitMode(STI));
1302 assert(!Is64BitMemOperand(MI, MemoryOperand));
1303 need_address_override = !Is16BitMemOperand(MI, MemoryOperand, STI);
1306 if (need_address_override)
1307 EmitByte(0x67, CurByte, OS);
1310 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS);
1312 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1314 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1316 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1317 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1319 unsigned SrcRegNum = 0;
1320 switch (TSFlags & X86II::FormMask) {
1321 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
1322 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1324 llvm_unreachable("Pseudo instruction shouldn't be emitted");
1325 case X86II::RawFrmDstSrc: {
1326 unsigned siReg = MI.getOperand(1).getReg();
1327 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) ||
1328 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) ||
1329 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&
1330 "SI and DI register sizes do not match");
1331 // Emit segment override opcode prefix as needed (not for %ds).
1332 if (MI.getOperand(2).getReg() != X86::DS)
1333 EmitSegmentOverridePrefix(CurByte, 2, MI, OS);
1334 // Emit OpSize prefix as needed.
1335 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1336 (is32BitMode(STI) && siReg == X86::SI))
1337 EmitByte(0x67, CurByte, OS);
1338 CurOp += 3; // Consume operands.
1339 EmitByte(BaseOpcode, CurByte, OS);
1342 case X86II::RawFrmSrc: {
1343 unsigned siReg = MI.getOperand(0).getReg();
1344 // Emit segment override opcode prefix as needed (not for %ds).
1345 if (MI.getOperand(1).getReg() != X86::DS)
1346 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1347 // Emit OpSize prefix as needed.
1348 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1349 (is32BitMode(STI) && siReg == X86::SI))
1350 EmitByte(0x67, CurByte, OS);
1351 CurOp += 2; // Consume operands.
1352 EmitByte(BaseOpcode, CurByte, OS);
1355 case X86II::RawFrmDst: {
1356 unsigned siReg = MI.getOperand(0).getReg();
1357 // Emit OpSize prefix as needed.
1358 if ((!is32BitMode(STI) && siReg == X86::EDI) ||
1359 (is32BitMode(STI) && siReg == X86::DI))
1360 EmitByte(0x67, CurByte, OS);
1361 ++CurOp; // Consume operand.
1362 EmitByte(BaseOpcode, CurByte, OS);
1366 EmitByte(BaseOpcode, CurByte, OS);
1368 case X86II::RawFrmMemOffs:
1369 // Emit segment override opcode prefix as needed.
1370 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1371 EmitByte(BaseOpcode, CurByte, OS);
1372 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1373 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1374 CurByte, OS, Fixups);
1375 ++CurOp; // skip segment operand
1377 case X86II::RawFrmImm8:
1378 EmitByte(BaseOpcode, CurByte, OS);
1379 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1380 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1381 CurByte, OS, Fixups);
1382 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte,
1385 case X86II::RawFrmImm16:
1386 EmitByte(BaseOpcode, CurByte, OS);
1387 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1388 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1389 CurByte, OS, Fixups);
1390 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte,
1394 case X86II::AddRegFrm:
1395 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
1398 case X86II::MRMDestReg:
1399 EmitByte(BaseOpcode, CurByte, OS);
1400 SrcRegNum = CurOp + 1;
1402 if (HasEVEX_K) // Skip writemask
1405 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1408 EmitRegModRMByte(MI.getOperand(CurOp),
1409 GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS);
1410 CurOp = SrcRegNum + 1;
1413 case X86II::MRMDestMem:
1414 EmitByte(BaseOpcode, CurByte, OS);
1415 SrcRegNum = CurOp + X86::AddrNumOperands;
1417 if (HasEVEX_K) // Skip writemask
1420 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1423 EmitMemModRMByte(MI, CurOp,
1424 GetX86RegNum(MI.getOperand(SrcRegNum)),
1425 TSFlags, CurByte, OS, Fixups, STI);
1426 CurOp = SrcRegNum + 1;
1429 case X86II::MRMSrcReg:
1430 EmitByte(BaseOpcode, CurByte, OS);
1431 SrcRegNum = CurOp + 1;
1433 if (HasEVEX_K) // Skip writemask
1436 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1439 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
1442 EmitRegModRMByte(MI.getOperand(SrcRegNum),
1443 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1445 // 2 operands skipped with HasMemOp4, compensate accordingly
1446 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
1449 // do not count the rounding control operand
1454 case X86II::MRMSrcMem: {
1455 int AddrOperands = X86::AddrNumOperands;
1456 unsigned FirstMemOp = CurOp+1;
1458 if (HasEVEX_K) { // Skip writemask
1465 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1467 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
1470 EmitByte(BaseOpcode, CurByte, OS);
1472 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1473 TSFlags, CurByte, OS, Fixups, STI);
1474 CurOp += AddrOperands + 1;
1480 case X86II::MRM0r: case X86II::MRM1r:
1481 case X86II::MRM2r: case X86II::MRM3r:
1482 case X86II::MRM4r: case X86II::MRM5r:
1483 case X86II::MRM6r: case X86II::MRM7r:
1484 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1486 EmitByte(BaseOpcode, CurByte, OS);
1487 EmitRegModRMByte(MI.getOperand(CurOp++),
1488 (TSFlags & X86II::FormMask)-X86II::MRM0r,
1491 case X86II::MRM0m: case X86II::MRM1m:
1492 case X86II::MRM2m: case X86II::MRM3m:
1493 case X86II::MRM4m: case X86II::MRM5m:
1494 case X86II::MRM6m: case X86II::MRM7m:
1495 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1497 EmitByte(BaseOpcode, CurByte, OS);
1498 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
1499 TSFlags, CurByte, OS, Fixups, STI);
1500 CurOp += X86::AddrNumOperands;
1502 case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3:
1503 case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9:
1504 case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_D0:
1505 case X86II::MRM_D1: case X86II::MRM_D4: case X86II::MRM_D5:
1506 case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D9:
1507 case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC:
1508 case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF:
1509 case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8:
1511 EmitByte(BaseOpcode, CurByte, OS);
1514 switch (TSFlags & X86II::FormMask) {
1515 default: llvm_unreachable("Invalid Form");
1516 case X86II::MRM_C1: MRM = 0xC1; break;
1517 case X86II::MRM_C2: MRM = 0xC2; break;
1518 case X86II::MRM_C3: MRM = 0xC3; break;
1519 case X86II::MRM_C4: MRM = 0xC4; break;
1520 case X86II::MRM_C8: MRM = 0xC8; break;
1521 case X86II::MRM_C9: MRM = 0xC9; break;
1522 case X86II::MRM_CA: MRM = 0xCA; break;
1523 case X86II::MRM_CB: MRM = 0xCB; break;
1524 case X86II::MRM_D0: MRM = 0xD0; break;
1525 case X86II::MRM_D1: MRM = 0xD1; break;
1526 case X86II::MRM_D4: MRM = 0xD4; break;
1527 case X86II::MRM_D5: MRM = 0xD5; break;
1528 case X86II::MRM_D6: MRM = 0xD6; break;
1529 case X86II::MRM_D8: MRM = 0xD8; break;
1530 case X86II::MRM_D9: MRM = 0xD9; break;
1531 case X86II::MRM_DA: MRM = 0xDA; break;
1532 case X86II::MRM_DB: MRM = 0xDB; break;
1533 case X86II::MRM_DC: MRM = 0xDC; break;
1534 case X86II::MRM_DD: MRM = 0xDD; break;
1535 case X86II::MRM_DE: MRM = 0xDE; break;
1536 case X86II::MRM_DF: MRM = 0xDF; break;
1537 case X86II::MRM_E8: MRM = 0xE8; break;
1538 case X86II::MRM_F0: MRM = 0xF0; break;
1539 case X86II::MRM_F8: MRM = 0xF8; break;
1540 case X86II::MRM_F9: MRM = 0xF9; break;
1542 EmitByte(MRM, CurByte, OS);
1546 // If there is a remaining operand, it must be a trailing immediate. Emit it
1547 // according to the right size for the instruction. Some instructions
1548 // (SSE4a extrq and insertq) have two trailing immediates.
1549 while (CurOp != NumOps && NumOps - CurOp <= 2) {
1550 // The last source register of a 4 operand instruction in AVX is encoded
1551 // in bits[7:4] of a immediate byte.
1552 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
1553 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
1556 unsigned RegNum = GetX86RegNum(MO) << 4;
1557 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1559 // If there is an additional 5th operand it must be an immediate, which
1560 // is encoded in bits[3:0]
1561 if (CurOp != NumOps) {
1562 const MCOperand &MIMM = MI.getOperand(CurOp++);
1564 unsigned Val = MIMM.getImm();
1565 assert(Val < 16 && "Immediate operand value out of range");
1569 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1,
1570 CurByte, OS, Fixups);
1572 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1573 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1574 CurByte, OS, Fixups);
1578 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1579 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1583 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1584 errs() << "Cannot encode all operands of: ";