1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/X86MCTargetDesc.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "MCTargetDesc/X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCSymbol.h"
26 #include "llvm/Support/raw_ostream.h"
31 class X86MCCodeEmitter : public MCCodeEmitter {
32 X86MCCodeEmitter(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION;
33 void operator=(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION;
34 const MCInstrInfo &MCII;
35 const MCSubtargetInfo &STI;
38 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
40 : MCII(mcii), STI(sti), Ctx(ctx) {
43 ~X86MCCodeEmitter() {}
45 bool is64BitMode() const {
46 // FIXME: Can tablegen auto-generate this?
47 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
50 bool is32BitMode() const {
51 // FIXME: Can tablegen auto-generate this?
52 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
55 bool is16BitMode() const {
56 // FIXME: Can tablegen auto-generate this?
57 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
60 /// Is16BitMemOperand - Return true if the specified instruction has
61 /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
62 bool Is16BitMemOperand(const MCInst &MI, unsigned Op) const {
63 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
64 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
65 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
67 if (is16BitMode() && BaseReg.getReg() == 0 &&
68 Disp.isImm() && Disp.getImm() < 0x10000)
70 if ((BaseReg.getReg() != 0 &&
71 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
72 (IndexReg.getReg() != 0 &&
73 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
78 unsigned GetX86RegNum(const MCOperand &MO) const {
79 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
82 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
83 // 0-7 and the difference between the 2 groups is given by the REX prefix.
84 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
85 // in 1's complement form, example:
87 // ModRM field => XMM9 => 1
88 // VEX.VVVV => XMM9 => ~9
90 // See table 4-35 of Intel AVX Programming Reference for details.
91 unsigned char getVEXRegisterEncoding(const MCInst &MI,
92 unsigned OpNum) const {
93 unsigned SrcReg = MI.getOperand(OpNum).getReg();
94 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
95 if (X86II::isX86_64ExtendedReg(SrcReg))
98 // The registers represented through VEX_VVVV should
99 // be encoded in 1's complement form.
100 return (~SrcRegNum) & 0xf;
103 unsigned char getWriteMaskRegisterEncoding(const MCInst &MI,
104 unsigned OpNum) const {
105 assert(X86::K0 != MI.getOperand(OpNum).getReg() &&
106 "Invalid mask register as write-mask!");
107 unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum));
111 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
116 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
117 raw_ostream &OS) const {
118 // Output the constant in little endian byte order.
119 for (unsigned i = 0; i != Size; ++i) {
120 EmitByte(Val & 255, CurByte, OS);
125 void EmitImmediate(const MCOperand &Disp, SMLoc Loc,
126 unsigned ImmSize, MCFixupKind FixupKind,
127 unsigned &CurByte, raw_ostream &OS,
128 SmallVectorImpl<MCFixup> &Fixups,
129 int ImmOffset = 0) const;
131 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
133 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
134 return RM | (RegOpcode << 3) | (Mod << 6);
137 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
138 unsigned &CurByte, raw_ostream &OS) const {
139 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
142 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
143 unsigned &CurByte, raw_ostream &OS) const {
144 // SIB byte is in the same format as the ModRMByte.
145 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
149 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
150 unsigned RegOpcodeField,
151 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
152 SmallVectorImpl<MCFixup> &Fixups) const;
154 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
155 SmallVectorImpl<MCFixup> &Fixups) const;
157 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
158 const MCInst &MI, const MCInstrDesc &Desc,
159 raw_ostream &OS) const;
161 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
162 int MemOperand, const MCInst &MI,
163 raw_ostream &OS) const;
165 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
166 const MCInst &MI, const MCInstrDesc &Desc,
167 raw_ostream &OS) const;
170 } // end anonymous namespace
173 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
174 const MCRegisterInfo &MRI,
175 const MCSubtargetInfo &STI,
177 return new X86MCCodeEmitter(MCII, STI, Ctx);
180 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
181 /// sign-extended field.
182 static bool isDisp8(int Value) {
183 return Value == (signed char)Value;
186 /// isCDisp8 - Return true if this signed displacement fits in a 8-bit
187 /// compressed dispacement field.
188 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
189 assert(((TSFlags >> X86II::VEXShift) & X86II::EVEX) &&
190 "Compressed 8-bit displacement is only valid for EVEX inst.");
192 unsigned CD8E = (TSFlags >> X86II::EVEX_CD8EShift) & X86II::EVEX_CD8EMask;
193 unsigned CD8V = (TSFlags >> X86II::EVEX_CD8VShift) & X86II::EVEX_CD8VMask;
195 if (CD8V == 0 && CD8E == 0) {
197 return isDisp8(Value);
200 unsigned MemObjSize = 1U << CD8E;
202 // Fixed vector length
203 MemObjSize *= 1U << (CD8V & 0x3);
205 // Modified vector length
206 bool EVEX_b = (TSFlags >> X86II::VEXShift) & X86II::EVEX_B;
208 unsigned EVEX_LL = ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) ? 1 : 0;
209 EVEX_LL += ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2) ? 2 : 0;
210 assert(EVEX_LL < 3 && "");
212 unsigned NumElems = (1U << (EVEX_LL + 4)) / MemObjSize;
213 NumElems /= 1U << (CD8V & 0x3);
215 MemObjSize *= NumElems;
219 unsigned MemObjMask = MemObjSize - 1;
220 assert((MemObjSize & MemObjMask) == 0 && "Invalid memory object size.");
222 if (Value & MemObjMask) // Unaligned offset
225 bool Ret = (Value == (signed char)Value);
232 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
233 /// in an instruction with the specified TSFlags.
234 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
235 unsigned Size = X86II::getSizeOfImm(TSFlags);
236 bool isPCRel = X86II::isImmPCRel(TSFlags);
238 return MCFixup::getKindForSize(Size, isPCRel);
241 /// Is32BitMemOperand - Return true if the specified instruction has
242 /// a 32-bit memory operand. Op specifies the operand # of the memoperand.
243 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
244 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
245 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
247 if ((BaseReg.getReg() != 0 &&
248 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
249 (IndexReg.getReg() != 0 &&
250 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
255 /// Is64BitMemOperand - Return true if the specified instruction has
256 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
258 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
259 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
260 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
262 if ((BaseReg.getReg() != 0 &&
263 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
264 (IndexReg.getReg() != 0 &&
265 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
271 /// StartsWithGlobalOffsetTable - Check if this expression starts with
272 /// _GLOBAL_OFFSET_TABLE_ and if it is of the form
273 /// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF
274 /// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
275 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
276 /// of a binary expression.
277 enum GlobalOffsetTableExprKind {
282 static GlobalOffsetTableExprKind
283 StartsWithGlobalOffsetTable(const MCExpr *Expr) {
284 const MCExpr *RHS = 0;
285 if (Expr->getKind() == MCExpr::Binary) {
286 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
291 if (Expr->getKind() != MCExpr::SymbolRef)
294 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
295 const MCSymbol &S = Ref->getSymbol();
296 if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
298 if (RHS && RHS->getKind() == MCExpr::SymbolRef)
303 static bool HasSecRelSymbolRef(const MCExpr *Expr) {
304 if (Expr->getKind() == MCExpr::SymbolRef) {
305 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
306 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL;
311 void X86MCCodeEmitter::
312 EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size,
313 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS,
314 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
315 const MCExpr *Expr = NULL;
316 if (DispOp.isImm()) {
317 // If this is a simple integer displacement that doesn't require a
318 // relocation, emit it now.
319 if (FixupKind != FK_PCRel_1 &&
320 FixupKind != FK_PCRel_2 &&
321 FixupKind != FK_PCRel_4) {
322 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
325 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx);
327 Expr = DispOp.getExpr();
330 // If we have an immoffset, add it to the expression.
331 if ((FixupKind == FK_Data_4 ||
332 FixupKind == FK_Data_8 ||
333 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
334 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr);
335 if (Kind != GOT_None) {
336 assert(ImmOffset == 0);
338 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
339 if (Kind == GOT_Normal)
341 } else if (Expr->getKind() == MCExpr::SymbolRef) {
342 if (HasSecRelSymbolRef(Expr)) {
343 FixupKind = MCFixupKind(FK_SecRel_4);
345 } else if (Expr->getKind() == MCExpr::Binary) {
346 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr);
347 if (HasSecRelSymbolRef(Bin->getLHS())
348 || HasSecRelSymbolRef(Bin->getRHS())) {
349 FixupKind = MCFixupKind(FK_SecRel_4);
354 // If the fixup is pc-relative, we need to bias the value to be relative to
355 // the start of the field, not the end of the field.
356 if (FixupKind == FK_PCRel_4 ||
357 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
358 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
360 if (FixupKind == FK_PCRel_2)
362 if (FixupKind == FK_PCRel_1)
366 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
369 // Emit a symbolic constant as a fixup and 4 zeros.
370 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc));
371 EmitConstant(0, Size, CurByte, OS);
374 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
375 unsigned RegOpcodeField,
376 uint64_t TSFlags, unsigned &CurByte,
378 SmallVectorImpl<MCFixup> &Fixups) const{
379 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
380 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
381 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
382 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
383 unsigned BaseReg = Base.getReg();
384 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
386 // Handle %rip relative addressing.
387 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
388 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode");
389 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
390 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
392 unsigned FixupKind = X86::reloc_riprel_4byte;
394 // movq loads are handled with a special relocation form which allows the
395 // linker to eliminate some loads for GOT references which end up in the
396 // same linkage unit.
397 if (MI.getOpcode() == X86::MOV64rm)
398 FixupKind = X86::reloc_riprel_4byte_movq_load;
400 // rip-relative addressing is actually relative to the *next* instruction.
401 // Since an immediate can follow the mod/rm byte for an instruction, this
402 // means that we need to bias the immediate field of the instruction with
403 // the size of the immediate field. If we have this case, add it into the
404 // expression to emit.
405 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
407 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind),
408 CurByte, OS, Fixups, -ImmSize);
412 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
414 // 16-bit addressing forms of the ModR/M byte have a different encoding for
415 // the R/M field and are far more limited in which registers can be used.
416 if (Is16BitMemOperand(MI, Op)) {
418 // For 32-bit addressing, the row and column values in Table 2-2 are
419 // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
420 // some special cases. And GetX86RegNum reflects that numbering.
421 // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
422 // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
423 // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
424 // while values 0-3 indicate the allowed combinations (base+index) of
425 // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
427 // R16Table[] is a lookup from the normal RegNo, to the row values from
428 // Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
429 static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 };
430 unsigned RMfield = R16Table[BaseRegNo];
432 assert(RMfield && "invalid 16-bit base register");
434 if (IndexReg.getReg()) {
435 unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)];
437 assert(IndexReg16 && "invalid 16-bit index register");
438 // We must have one of SI/DI (4,5), and one of BP/BX (6,7).
439 assert(((IndexReg16 ^ RMfield) & 2) &&
440 "invalid 16-bit base/index register combination");
441 assert(Scale.getImm() == 1 &&
442 "invalid scale for 16-bit memory reference");
444 // Allow base/index to appear in either order (although GAS doesn't).
446 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
448 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
451 if (Disp.isImm() && isDisp8(Disp.getImm())) {
452 if (Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
453 // There is no displacement; just the register.
454 EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS);
457 // Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
458 EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS);
459 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
462 // This is the [REG]+disp16 case.
463 EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS);
465 // There is no BaseReg; this is the plain [disp16] case.
466 EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS);
469 // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
470 EmitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups);
474 // Determine whether a SIB byte is needed.
475 // If no BaseReg, issue a RIP relative instruction only if the MCE can
476 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
477 // 2-7) and absolute references.
479 if (// The SIB byte must be used if there is an index register.
480 IndexReg.getReg() == 0 &&
481 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
482 // encode to an R/M value of 4, which indicates that a SIB byte is
484 BaseRegNo != N86::ESP &&
485 // If there is no base register and we're in 64-bit mode, we need a SIB
486 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
487 (!is64BitMode() || BaseReg != 0)) {
489 if (BaseReg == 0) { // [disp32] in X86-32 mode
490 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
491 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups);
495 // If the base is not EBP/ESP and there is no displacement, use simple
496 // indirect register encoding, this handles addresses like [EAX]. The
497 // encoding for [EBP] with no displacement means [disp32] so we handle it
498 // by emitting a displacement of 0 below.
499 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
500 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
504 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
506 if (!HasEVEX && isDisp8(Disp.getImm())) {
507 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
508 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
511 // Try EVEX compressed 8-bit displacement first; if failed, fall back to
512 // 32-bit displacement.
514 if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
515 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
516 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups,
517 CDisp8 - Disp.getImm());
522 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
523 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
524 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
529 // We need a SIB byte, so start by outputting the ModR/M byte first
530 assert(IndexReg.getReg() != X86::ESP &&
531 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
533 bool ForceDisp32 = false;
534 bool ForceDisp8 = false;
538 // If there is no base register, we emit the special case SIB byte with
539 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
540 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
542 } else if (!Disp.isImm()) {
543 // Emit the normal disp32 encoding.
544 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
546 } else if (Disp.getImm() == 0 &&
547 // Base reg can't be anything that ends up with '5' as the base
548 // reg, it is the magic [*] nomenclature that indicates no base.
549 BaseRegNo != N86::EBP) {
550 // Emit no displacement ModR/M byte
551 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
552 } else if (!HasEVEX && isDisp8(Disp.getImm())) {
553 // Emit the disp8 encoding.
554 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
555 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
556 } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
557 // Emit the disp8 encoding.
558 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
559 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
560 ImmOffset = CDisp8 - Disp.getImm();
562 // Emit the normal disp32 encoding.
563 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
566 // Calculate what the SS field value should be...
567 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
568 unsigned SS = SSTable[Scale.getImm()];
571 // Handle the SIB byte for the case where there is no base, see Intel
572 // Manual 2A, table 2-7. The displacement has already been output.
574 if (IndexReg.getReg())
575 IndexRegNo = GetX86RegNum(IndexReg);
576 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
578 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
581 if (IndexReg.getReg())
582 IndexRegNo = GetX86RegNum(IndexReg);
584 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
585 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
588 // Do we need to output a displacement?
590 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset);
591 else if (ForceDisp32 || Disp.getImm() != 0)
592 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
593 CurByte, OS, Fixups);
596 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
598 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
599 int MemOperand, const MCInst &MI,
600 const MCInstrDesc &Desc,
601 raw_ostream &OS) const {
602 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
603 bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
604 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
605 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
606 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
607 bool HasEVEX_RC = (TSFlags >> X86II::VEXShift) & X86II::EVEX_RC;
609 // VEX_R: opcode externsion equivalent to REX.R in
610 // 1's complement (inverted) form
612 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
613 // 0: Same as REX_R=1 (64 bit mode only)
615 unsigned char VEX_R = 0x1;
616 unsigned char EVEX_R2 = 0x1;
618 // VEX_X: equivalent to REX.X, only used when a
619 // register is used for index in SIB Byte.
621 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
622 // 0: Same as REX.X=1 (64-bit mode only)
623 unsigned char VEX_X = 0x1;
627 // 1: Same as REX_B=0 (ignored in 32-bit mode)
628 // 0: Same as REX_B=1 (64 bit mode only)
630 unsigned char VEX_B = 0x1;
632 // VEX_W: opcode specific (use like REX.W, or used for
633 // opcode extension, or ignored, depending on the opcode byte)
634 unsigned char VEX_W = 0;
636 // XOP: Use XOP prefix byte 0x8f instead of VEX.
639 // VEX_5M (VEX m-mmmmm field):
641 // 0b00000: Reserved for future use
642 // 0b00001: implied 0F leading opcode
643 // 0b00010: implied 0F 38 leading opcode bytes
644 // 0b00011: implied 0F 3A leading opcode bytes
645 // 0b00100-0b11111: Reserved for future use
646 // 0b01000: XOP map select - 08h instructions with imm byte
647 // 0b01001: XOP map select - 09h instructions with no imm byte
648 // 0b01010: XOP map select - 0Ah instructions with imm dword
649 unsigned char VEX_5M = 0x1;
651 // VEX_4V (VEX vvvv field): a register specifier
652 // (in 1's complement form) or 1111 if unused.
653 unsigned char VEX_4V = 0xf;
654 unsigned char EVEX_V2 = 0x1;
656 // VEX_L (Vector Length):
658 // 0: scalar or 128-bit vector
661 unsigned char VEX_L = 0;
662 unsigned char EVEX_L2 = 0;
664 // VEX_PP: opcode extension providing equivalent
665 // functionality of a SIMD prefix
672 unsigned char VEX_PP = 0;
675 unsigned char EVEX_U = 1; // Always '1' so far
678 unsigned char EVEX_z = 0;
681 unsigned char EVEX_b = 0;
684 unsigned char EVEX_rc = 0;
687 unsigned char EVEX_aaa = 0;
689 bool EncodeRC = false;
691 // Encode the operand size opcode prefix as needed.
692 if (TSFlags & X86II::OpSize)
695 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
698 if ((TSFlags >> X86II::VEXShift) & X86II::XOP)
701 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
703 if (HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2))
706 if (HasEVEX_K && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_Z))
709 if (HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_B))
712 switch (TSFlags & X86II::Op0Mask) {
713 default: llvm_unreachable("Invalid prefix!");
714 case X86II::T8: // 0F 38
717 case X86II::TA: // 0F 3A
720 case X86II::T8PD: // 66 0F 38
724 case X86II::T8XS: // F3 0F 38
728 case X86II::T8XD: // F2 0F 38
732 case X86II::TAPD: // 66 0F 3A
736 case X86II::TAXD: // F2 0F 3A
740 case X86II::PD: // 66 0F
743 case X86II::XS: // F3 0F
746 case X86II::XD: // F2 0F
758 case X86II::TB: // VEX_5M/VEX_PP already correct
763 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
764 unsigned NumOps = Desc.getNumOperands();
766 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
768 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
769 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
770 // Special case for AVX-512 GATHER with 2 TIED_TO operands
771 // Skip the first 2 operands: dst, mask_wb
773 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
774 Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1)
775 // Special case for GATHER with 2 TIED_TO operands
776 // Skip the first 2 operands: dst, mask_wb
778 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0)
782 switch (TSFlags & X86II::FormMask) {
783 case X86II::MRMDestMem: {
784 // MRMDestMem instructions forms:
785 // MemAddr, src1(ModR/M)
786 // MemAddr, src1(VEX_4V), src2(ModR/M)
787 // MemAddr, src1(ModR/M), imm8
789 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
790 X86::AddrBaseReg).getReg()))
792 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
793 X86::AddrIndexReg).getReg()))
795 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(MemOperand +
796 X86::AddrIndexReg).getReg()))
799 CurOp += X86::AddrNumOperands;
802 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
805 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
806 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
811 const MCOperand &MO = MI.getOperand(CurOp);
813 if (X86II::isX86_64ExtendedReg(MO.getReg()))
815 if (HasEVEX && X86II::is32ExtendedReg(MO.getReg()))
820 case X86II::MRMSrcMem:
821 // MRMSrcMem instructions forms:
822 // src1(ModR/M), MemAddr
823 // src1(ModR/M), src2(VEX_4V), MemAddr
824 // src1(ModR/M), MemAddr, imm8
825 // src1(ModR/M), MemAddr, src2(VEX_I8IMM)
828 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
829 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
830 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
832 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
837 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
840 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
841 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
846 if (X86II::isX86_64ExtendedReg(
847 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
849 if (X86II::isX86_64ExtendedReg(
850 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
852 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(MemOperand +
853 X86::AddrIndexReg).getReg()))
857 // Instruction format for 4VOp3:
858 // src1(ModR/M), MemAddr, src3(VEX_4V)
859 // CurOp points to start of the MemoryOperand,
860 // it skips TIED_TO operands if exist, then increments past src1.
861 // CurOp + X86::AddrNumOperands will point to src3.
862 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands);
864 case X86II::MRM0m: case X86II::MRM1m:
865 case X86II::MRM2m: case X86II::MRM3m:
866 case X86II::MRM4m: case X86II::MRM5m:
867 case X86II::MRM6m: case X86II::MRM7m: {
868 // MRM[0-9]m instructions forms:
870 // src1(VEX_4V), MemAddr
872 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
873 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
879 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
881 if (X86II::isX86_64ExtendedReg(
882 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
884 if (X86II::isX86_64ExtendedReg(
885 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
889 case X86II::MRMSrcReg:
890 // MRMSrcReg instructions forms:
891 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
892 // dst(ModR/M), src1(ModR/M)
893 // dst(ModR/M), src1(ModR/M), imm8
896 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
897 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
898 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
900 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
905 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
908 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
909 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
914 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
917 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
919 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
923 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
926 unsigned RcOperand = NumOps-1;
927 assert(RcOperand >= CurOp);
928 EVEX_rc = MI.getOperand(RcOperand).getImm() & 0x3;
933 case X86II::MRMDestReg:
934 // MRMDestReg instructions forms:
935 // dst(ModR/M), src(ModR/M)
936 // dst(ModR/M), src(ModR/M), imm8
937 // dst(ModR/M), src1(VEX_4V), src2(ModR/M)
938 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
940 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
945 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
948 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
949 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
954 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
956 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
961 case X86II::MRM0r: case X86II::MRM1r:
962 case X86II::MRM2r: case X86II::MRM3r:
963 case X86II::MRM4r: case X86II::MRM5r:
964 case X86II::MRM6r: case X86II::MRM7r:
965 // MRM0r-MRM7r instructions forms:
966 // dst(VEX_4V), src(ModR/M), imm8
968 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
969 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
974 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
976 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
978 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
985 // Emit segment override opcode prefix as needed.
986 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
989 // VEX opcode prefix can have 2 or 3 bytes
992 // +-----+ +--------------+ +-------------------+
993 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
994 // +-----+ +--------------+ +-------------------+
996 // +-----+ +-------------------+
997 // | C5h | | R | vvvv | L | pp |
998 // +-----+ +-------------------+
1000 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
1002 if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix
1003 EmitByte(0xC5, CurByte, OS);
1004 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
1008 // 3 byte VEX prefix
1009 EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS);
1010 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
1011 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
1013 // EVEX opcode prefix can have 4 bytes
1015 // +-----+ +--------------+ +-------------------+ +------------------------+
1016 // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
1017 // +-----+ +--------------+ +-------------------+ +------------------------+
1018 assert((VEX_5M & 0x3) == VEX_5M
1019 && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!");
1023 EmitByte(0x62, CurByte, OS);
1024 EmitByte((VEX_R << 7) |
1028 VEX_5M, CurByte, OS);
1029 EmitByte((VEX_W << 7) |
1032 VEX_PP, CurByte, OS);
1034 EmitByte((EVEX_z << 7) |
1038 EVEX_aaa, CurByte, OS);
1040 EmitByte((EVEX_z << 7) |
1045 EVEX_aaa, CurByte, OS);
1049 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
1050 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
1051 /// size, and 3) use of X86-64 extended registers.
1052 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
1053 const MCInstrDesc &Desc) {
1055 if (TSFlags & X86II::REX_W)
1056 REX |= 1 << 3; // set REX.W
1058 if (MI.getNumOperands() == 0) return REX;
1060 unsigned NumOps = MI.getNumOperands();
1061 // FIXME: MCInst should explicitize the two-addrness.
1062 bool isTwoAddr = NumOps > 1 &&
1063 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
1065 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
1066 unsigned i = isTwoAddr ? 1 : 0;
1067 for (; i != NumOps; ++i) {
1068 const MCOperand &MO = MI.getOperand(i);
1069 if (!MO.isReg()) continue;
1070 unsigned Reg = MO.getReg();
1071 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
1072 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
1073 // that returns non-zero.
1074 REX |= 0x40; // REX fixed encoding prefix
1078 switch (TSFlags & X86II::FormMask) {
1079 case X86II::MRMSrcReg:
1080 if (MI.getOperand(0).isReg() &&
1081 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1082 REX |= 1 << 2; // set REX.R
1083 i = isTwoAddr ? 2 : 1;
1084 for (; i != NumOps; ++i) {
1085 const MCOperand &MO = MI.getOperand(i);
1086 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
1087 REX |= 1 << 0; // set REX.B
1090 case X86II::MRMSrcMem: {
1091 if (MI.getOperand(0).isReg() &&
1092 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1093 REX |= 1 << 2; // set REX.R
1095 i = isTwoAddr ? 2 : 1;
1096 for (; i != NumOps; ++i) {
1097 const MCOperand &MO = MI.getOperand(i);
1099 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1100 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
1106 case X86II::MRM0m: case X86II::MRM1m:
1107 case X86II::MRM2m: case X86II::MRM3m:
1108 case X86II::MRM4m: case X86II::MRM5m:
1109 case X86II::MRM6m: case X86II::MRM7m:
1110 case X86II::MRMDestMem: {
1111 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
1112 i = isTwoAddr ? 1 : 0;
1113 if (NumOps > e && MI.getOperand(e).isReg() &&
1114 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
1115 REX |= 1 << 2; // set REX.R
1117 for (; i != e; ++i) {
1118 const MCOperand &MO = MI.getOperand(i);
1120 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1121 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
1128 if (MI.getOperand(0).isReg() &&
1129 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1130 REX |= 1 << 0; // set REX.B
1131 i = isTwoAddr ? 2 : 1;
1132 for (unsigned e = NumOps; i != e; ++i) {
1133 const MCOperand &MO = MI.getOperand(i);
1134 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
1135 REX |= 1 << 2; // set REX.R
1142 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
1143 void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags,
1144 unsigned &CurByte, int MemOperand,
1146 raw_ostream &OS) const {
1148 return; // No memory operand
1150 // Check for explicit segment override on memory operand.
1151 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
1152 default: llvm_unreachable("Unknown segment register!");
1154 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
1155 case X86::SS: EmitByte(0x36, CurByte, OS); break;
1156 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
1157 case X86::ES: EmitByte(0x26, CurByte, OS); break;
1158 case X86::FS: EmitByte(0x64, CurByte, OS); break;
1159 case X86::GS: EmitByte(0x65, CurByte, OS); break;
1163 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
1165 /// MemOperand is the operand # of the start of a memory operand if present. If
1166 /// Not present, it is -1.
1167 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
1168 int MemOperand, const MCInst &MI,
1169 const MCInstrDesc &Desc,
1170 raw_ostream &OS) const {
1172 // Emit the lock opcode prefix as needed.
1173 if (TSFlags & X86II::LOCK)
1174 EmitByte(0xF0, CurByte, OS);
1176 // Emit segment override opcode prefix as needed.
1177 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
1179 // Emit the repeat opcode prefix as needed.
1180 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
1181 EmitByte(0xF3, CurByte, OS);
1183 // Emit the address size opcode prefix as needed.
1184 bool need_address_override;
1185 // The AdSize prefix is only for 32-bit and 64-bit modes. Hm, perhaps we
1186 // should introduce an AdSize16 bit instead of having seven special cases?
1187 if ((!is16BitMode() && TSFlags & X86II::AdSize) ||
1188 (is16BitMode() && (MI.getOpcode() == X86::JECXZ_32 ||
1189 MI.getOpcode() == X86::MOV8o8a ||
1190 MI.getOpcode() == X86::MOV16o16a ||
1191 MI.getOpcode() == X86::MOV32o32a ||
1192 MI.getOpcode() == X86::MOV8ao8 ||
1193 MI.getOpcode() == X86::MOV16ao16 ||
1194 MI.getOpcode() == X86::MOV32ao32))) {
1195 need_address_override = true;
1196 } else if (MemOperand == -1) {
1197 need_address_override = false;
1198 } else if (is64BitMode()) {
1199 assert(!Is16BitMemOperand(MI, MemOperand));
1200 need_address_override = Is32BitMemOperand(MI, MemOperand);
1201 } else if (is32BitMode()) {
1202 assert(!Is64BitMemOperand(MI, MemOperand));
1203 need_address_override = Is16BitMemOperand(MI, MemOperand);
1205 assert(is16BitMode());
1206 assert(!Is64BitMemOperand(MI, MemOperand));
1207 need_address_override = !Is16BitMemOperand(MI, MemOperand);
1210 if (need_address_override)
1211 EmitByte(0x67, CurByte, OS);
1213 // Emit the operand size opcode prefix as needed.
1214 if (TSFlags & (is16BitMode() ? X86II::OpSize16 : X86II::OpSize))
1215 EmitByte(0x66, CurByte, OS);
1217 bool Need0FPrefix = false;
1218 switch (TSFlags & X86II::Op0Mask) {
1219 default: llvm_unreachable("Invalid prefix!");
1220 case 0: break; // No prefix!
1221 case X86II::REP: break; // already handled.
1222 case X86II::TB: // Two-byte opcode prefix
1223 case X86II::T8: // 0F 38
1224 case X86II::TA: // 0F 3A
1225 case X86II::A6: // 0F A6
1226 case X86II::A7: // 0F A7
1227 Need0FPrefix = true;
1229 case X86II::PD: // 66 0F
1230 case X86II::T8PD: // 66 0F 38
1231 case X86II::TAPD: // 66 0F 3A
1232 EmitByte(0x66, CurByte, OS);
1233 Need0FPrefix = true;
1235 case X86II::XS: // F3 0F
1236 case X86II::T8XS: // F3 0F 38
1237 EmitByte(0xF3, CurByte, OS);
1238 Need0FPrefix = true;
1240 case X86II::XD: // F2 0F
1241 case X86II::T8XD: // F2 0F 38
1242 case X86II::TAXD: // F2 0F 3A
1243 EmitByte(0xF2, CurByte, OS);
1244 Need0FPrefix = true;
1254 EmitByte(0xD8+(((TSFlags & X86II::Op0Mask) - X86II::D8) >> X86II::Op0Shift),
1259 // Handle REX prefix.
1260 // FIXME: Can this come before F2 etc to simplify emission?
1261 if (is64BitMode()) {
1262 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
1263 EmitByte(0x40 | REX, CurByte, OS);
1266 // 0x0F escape code must be emitted just before the opcode.
1268 EmitByte(0x0F, CurByte, OS);
1270 // FIXME: Pull this up into previous switch if REX can be moved earlier.
1271 switch (TSFlags & X86II::Op0Mask) {
1272 case X86II::T8PD: // 66 0F 38
1273 case X86II::T8XS: // F3 0F 38
1274 case X86II::T8XD: // F2 0F 38
1275 case X86II::T8: // 0F 38
1276 EmitByte(0x38, CurByte, OS);
1278 case X86II::TAPD: // 66 0F 3A
1279 case X86II::TAXD: // F2 0F 3A
1280 case X86II::TA: // 0F 3A
1281 EmitByte(0x3A, CurByte, OS);
1283 case X86II::A6: // 0F A6
1284 EmitByte(0xA6, CurByte, OS);
1286 case X86II::A7: // 0F A7
1287 EmitByte(0xA7, CurByte, OS);
1292 void X86MCCodeEmitter::
1293 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1294 SmallVectorImpl<MCFixup> &Fixups) const {
1295 unsigned Opcode = MI.getOpcode();
1296 const MCInstrDesc &Desc = MCII.get(Opcode);
1297 uint64_t TSFlags = Desc.TSFlags;
1299 // Pseudo instructions don't get encoded.
1300 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
1303 unsigned NumOps = Desc.getNumOperands();
1304 unsigned CurOp = X86II::getOperandBias(Desc);
1306 // Keep track of the current byte being emitted.
1307 unsigned CurByte = 0;
1309 // Is this instruction encoded using the AVX VEX prefix?
1310 bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX;
1312 // It uses the VEX.VVVV field?
1313 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
1314 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
1315 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
1316 const unsigned MemOp4_I8IMMOperand = 2;
1318 // It uses the EVEX.aaa field?
1319 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
1320 bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
1321 bool HasEVEX_RC = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_RC);
1323 // Determine where the memory operand starts, if present.
1324 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
1325 if (MemoryOperand != -1) MemoryOperand += CurOp;
1328 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1330 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1332 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1334 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1335 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1337 unsigned SrcRegNum = 0;
1338 switch (TSFlags & X86II::FormMask) {
1339 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
1340 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1342 llvm_unreachable("Pseudo instruction shouldn't be emitted");
1344 EmitByte(BaseOpcode, CurByte, OS);
1346 case X86II::RawFrmImm8:
1347 EmitByte(BaseOpcode, CurByte, OS);
1348 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1349 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1350 CurByte, OS, Fixups);
1351 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte,
1354 case X86II::RawFrmImm16:
1355 EmitByte(BaseOpcode, CurByte, OS);
1356 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1357 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1358 CurByte, OS, Fixups);
1359 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte,
1363 case X86II::AddRegFrm:
1364 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
1367 case X86II::MRMDestReg:
1368 EmitByte(BaseOpcode, CurByte, OS);
1369 SrcRegNum = CurOp + 1;
1371 if (HasEVEX_K) // Skip writemask
1374 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1377 EmitRegModRMByte(MI.getOperand(CurOp),
1378 GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS);
1379 CurOp = SrcRegNum + 1;
1382 case X86II::MRMDestMem:
1383 EmitByte(BaseOpcode, CurByte, OS);
1384 SrcRegNum = CurOp + X86::AddrNumOperands;
1386 if (HasEVEX_K) // Skip writemask
1389 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1392 EmitMemModRMByte(MI, CurOp,
1393 GetX86RegNum(MI.getOperand(SrcRegNum)),
1394 TSFlags, CurByte, OS, Fixups);
1395 CurOp = SrcRegNum + 1;
1398 case X86II::MRMSrcReg:
1399 EmitByte(BaseOpcode, CurByte, OS);
1400 SrcRegNum = CurOp + 1;
1402 if (HasEVEX_K) // Skip writemask
1405 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1408 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
1411 EmitRegModRMByte(MI.getOperand(SrcRegNum),
1412 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1414 // 2 operands skipped with HasMemOp4, compensate accordingly
1415 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
1418 // do not count the rounding control operand
1423 case X86II::MRMSrcMem: {
1424 int AddrOperands = X86::AddrNumOperands;
1425 unsigned FirstMemOp = CurOp+1;
1427 if (HasEVEX_K) { // Skip writemask
1434 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1436 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
1439 EmitByte(BaseOpcode, CurByte, OS);
1441 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1442 TSFlags, CurByte, OS, Fixups);
1443 CurOp += AddrOperands + 1;
1449 case X86II::MRM0r: case X86II::MRM1r:
1450 case X86II::MRM2r: case X86II::MRM3r:
1451 case X86II::MRM4r: case X86II::MRM5r:
1452 case X86II::MRM6r: case X86II::MRM7r:
1453 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1455 EmitByte(BaseOpcode, CurByte, OS);
1456 EmitRegModRMByte(MI.getOperand(CurOp++),
1457 (TSFlags & X86II::FormMask)-X86II::MRM0r,
1460 case X86II::MRM0m: case X86II::MRM1m:
1461 case X86II::MRM2m: case X86II::MRM3m:
1462 case X86II::MRM4m: case X86II::MRM5m:
1463 case X86II::MRM6m: case X86II::MRM7m:
1464 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1466 EmitByte(BaseOpcode, CurByte, OS);
1467 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
1468 TSFlags, CurByte, OS, Fixups);
1469 CurOp += X86::AddrNumOperands;
1471 case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3:
1472 case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9:
1473 case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_D0:
1474 case X86II::MRM_D1: case X86II::MRM_D4: case X86II::MRM_D5:
1475 case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D9:
1476 case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC:
1477 case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF:
1478 case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8:
1480 EmitByte(BaseOpcode, CurByte, OS);
1483 switch (TSFlags & X86II::FormMask) {
1484 default: llvm_unreachable("Invalid Form");
1485 case X86II::MRM_C1: MRM = 0xC1; break;
1486 case X86II::MRM_C2: MRM = 0xC2; break;
1487 case X86II::MRM_C3: MRM = 0xC3; break;
1488 case X86II::MRM_C4: MRM = 0xC4; break;
1489 case X86II::MRM_C8: MRM = 0xC8; break;
1490 case X86II::MRM_C9: MRM = 0xC9; break;
1491 case X86II::MRM_CA: MRM = 0xCA; break;
1492 case X86II::MRM_CB: MRM = 0xCB; break;
1493 case X86II::MRM_D0: MRM = 0xD0; break;
1494 case X86II::MRM_D1: MRM = 0xD1; break;
1495 case X86II::MRM_D4: MRM = 0xD4; break;
1496 case X86II::MRM_D5: MRM = 0xD5; break;
1497 case X86II::MRM_D6: MRM = 0xD6; break;
1498 case X86II::MRM_D8: MRM = 0xD8; break;
1499 case X86II::MRM_D9: MRM = 0xD9; break;
1500 case X86II::MRM_DA: MRM = 0xDA; break;
1501 case X86II::MRM_DB: MRM = 0xDB; break;
1502 case X86II::MRM_DC: MRM = 0xDC; break;
1503 case X86II::MRM_DD: MRM = 0xDD; break;
1504 case X86II::MRM_DE: MRM = 0xDE; break;
1505 case X86II::MRM_DF: MRM = 0xDF; break;
1506 case X86II::MRM_E8: MRM = 0xE8; break;
1507 case X86II::MRM_F0: MRM = 0xF0; break;
1508 case X86II::MRM_F8: MRM = 0xF8; break;
1509 case X86II::MRM_F9: MRM = 0xF9; break;
1511 EmitByte(MRM, CurByte, OS);
1515 // If there is a remaining operand, it must be a trailing immediate. Emit it
1516 // according to the right size for the instruction. Some instructions
1517 // (SSE4a extrq and insertq) have two trailing immediates.
1518 while (CurOp != NumOps && NumOps - CurOp <= 2) {
1519 // The last source register of a 4 operand instruction in AVX is encoded
1520 // in bits[7:4] of a immediate byte.
1521 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
1522 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
1525 unsigned RegNum = GetX86RegNum(MO) << 4;
1526 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1528 // If there is an additional 5th operand it must be an immediate, which
1529 // is encoded in bits[3:0]
1530 if (CurOp != NumOps) {
1531 const MCOperand &MIMM = MI.getOperand(CurOp++);
1533 unsigned Val = MIMM.getImm();
1534 assert(Val < 16 && "Immediate operand value out of range");
1538 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1,
1539 CurByte, OS, Fixups);
1542 // FIXME: Is there a better way to know that we need a signed relocation?
1543 if (MI.getOpcode() == X86::ADD64ri32 ||
1544 MI.getOpcode() == X86::MOV64ri32 ||
1545 MI.getOpcode() == X86::MOV64mi32 ||
1546 MI.getOpcode() == X86::PUSH64i32)
1547 FixupKind = X86::reloc_signed_4byte;
1549 FixupKind = getImmFixupKind(TSFlags);
1550 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1551 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind),
1552 CurByte, OS, Fixups);
1556 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1557 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1561 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1562 errs() << "Cannot encode all operands of: ";