1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "MCTargetDesc/X86BaseInfo.h"
16 #include "MCTargetDesc/X86FixupKinds.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "mccodeemitter"
32 class X86MCCodeEmitter : public MCCodeEmitter {
33 X86MCCodeEmitter(const X86MCCodeEmitter &) = delete;
34 void operator=(const X86MCCodeEmitter &) = delete;
35 const MCInstrInfo &MCII;
38 X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
39 : MCII(mcii), Ctx(ctx) {
42 ~X86MCCodeEmitter() {}
44 bool is64BitMode(const MCSubtargetInfo &STI) const {
45 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
48 bool is32BitMode(const MCSubtargetInfo &STI) const {
49 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
52 bool is16BitMode(const MCSubtargetInfo &STI) const {
53 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
56 /// Is16BitMemOperand - Return true if the specified instruction has
57 /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
58 bool Is16BitMemOperand(const MCInst &MI, unsigned Op,
59 const MCSubtargetInfo &STI) const {
60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
62 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
64 if (is16BitMode(STI) && BaseReg.getReg() == 0 &&
65 Disp.isImm() && Disp.getImm() < 0x10000)
67 if ((BaseReg.getReg() != 0 &&
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
69 (IndexReg.getReg() != 0 &&
70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
75 unsigned GetX86RegNum(const MCOperand &MO) const {
76 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
79 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
80 // 0-7 and the difference between the 2 groups is given by the REX prefix.
81 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
82 // in 1's complement form, example:
84 // ModRM field => XMM9 => 1
85 // VEX.VVVV => XMM9 => ~9
87 // See table 4-35 of Intel AVX Programming Reference for details.
88 unsigned char getVEXRegisterEncoding(const MCInst &MI,
89 unsigned OpNum) const {
90 unsigned SrcReg = MI.getOperand(OpNum).getReg();
91 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
92 if (X86II::isX86_64ExtendedReg(SrcReg))
95 // The registers represented through VEX_VVVV should
96 // be encoded in 1's complement form.
97 return (~SrcRegNum) & 0xf;
100 unsigned char getWriteMaskRegisterEncoding(const MCInst &MI,
101 unsigned OpNum) const {
102 assert(X86::K0 != MI.getOperand(OpNum).getReg() &&
103 "Invalid mask register as write-mask!");
104 unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum));
108 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
113 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
114 raw_ostream &OS) const {
115 // Output the constant in little endian byte order.
116 for (unsigned i = 0; i != Size; ++i) {
117 EmitByte(Val & 255, CurByte, OS);
122 void EmitImmediate(const MCOperand &Disp, SMLoc Loc,
123 unsigned ImmSize, MCFixupKind FixupKind,
124 unsigned &CurByte, raw_ostream &OS,
125 SmallVectorImpl<MCFixup> &Fixups,
126 int ImmOffset = 0) const;
128 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
130 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
131 return RM | (RegOpcode << 3) | (Mod << 6);
134 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
135 unsigned &CurByte, raw_ostream &OS) const {
136 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
139 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
140 unsigned &CurByte, raw_ostream &OS) const {
141 // SIB byte is in the same format as the ModRMByte.
142 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
146 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
147 unsigned RegOpcodeField,
148 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
149 SmallVectorImpl<MCFixup> &Fixups,
150 const MCSubtargetInfo &STI) const;
152 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
153 SmallVectorImpl<MCFixup> &Fixups,
154 const MCSubtargetInfo &STI) const override;
156 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
157 const MCInst &MI, const MCInstrDesc &Desc,
158 raw_ostream &OS) const;
160 void EmitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand,
161 const MCInst &MI, raw_ostream &OS) const;
163 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
164 const MCInst &MI, const MCInstrDesc &Desc,
165 const MCSubtargetInfo &STI,
166 raw_ostream &OS) const;
169 } // end anonymous namespace
171 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
172 const MCRegisterInfo &MRI,
174 return new X86MCCodeEmitter(MCII, Ctx);
177 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
178 /// sign-extended field.
179 static bool isDisp8(int Value) {
180 return Value == (signed char)Value;
183 /// isCDisp8 - Return true if this signed displacement fits in a 8-bit
184 /// compressed dispacement field.
185 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
186 assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) &&
187 "Compressed 8-bit displacement is only valid for EVEX inst.");
190 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift;
191 if (CD8_Scale == 0) {
193 return isDisp8(Value);
196 unsigned Mask = CD8_Scale - 1;
197 assert((CD8_Scale & Mask) == 0 && "Invalid memory object size.");
198 if (Value & Mask) // Unaligned offset
200 Value /= (int)CD8_Scale;
201 bool Ret = (Value == (signed char)Value);
208 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
209 /// in an instruction with the specified TSFlags.
210 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
211 unsigned Size = X86II::getSizeOfImm(TSFlags);
212 bool isPCRel = X86II::isImmPCRel(TSFlags);
214 if (X86II::isImmSigned(TSFlags)) {
216 default: llvm_unreachable("Unsupported signed fixup size!");
217 case 4: return MCFixupKind(X86::reloc_signed_4byte);
220 return MCFixup::getKindForSize(Size, isPCRel);
223 /// Is32BitMemOperand - Return true if the specified instruction has
224 /// a 32-bit memory operand. Op specifies the operand # of the memoperand.
225 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
226 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
227 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
229 if ((BaseReg.getReg() != 0 &&
230 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
231 (IndexReg.getReg() != 0 &&
232 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
237 /// Is64BitMemOperand - Return true if the specified instruction has
238 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
240 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
241 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
242 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
244 if ((BaseReg.getReg() != 0 &&
245 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
246 (IndexReg.getReg() != 0 &&
247 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
253 /// StartsWithGlobalOffsetTable - Check if this expression starts with
254 /// _GLOBAL_OFFSET_TABLE_ and if it is of the form
255 /// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF
256 /// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
257 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
258 /// of a binary expression.
259 enum GlobalOffsetTableExprKind {
264 static GlobalOffsetTableExprKind
265 StartsWithGlobalOffsetTable(const MCExpr *Expr) {
266 const MCExpr *RHS = nullptr;
267 if (Expr->getKind() == MCExpr::Binary) {
268 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
273 if (Expr->getKind() != MCExpr::SymbolRef)
276 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
277 const MCSymbol &S = Ref->getSymbol();
278 if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
280 if (RHS && RHS->getKind() == MCExpr::SymbolRef)
285 static bool HasSecRelSymbolRef(const MCExpr *Expr) {
286 if (Expr->getKind() == MCExpr::SymbolRef) {
287 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
288 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL;
293 void X86MCCodeEmitter::
294 EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size,
295 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS,
296 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
297 const MCExpr *Expr = nullptr;
298 if (DispOp.isImm()) {
299 // If this is a simple integer displacement that doesn't require a
300 // relocation, emit it now.
301 if (FixupKind != FK_PCRel_1 &&
302 FixupKind != FK_PCRel_2 &&
303 FixupKind != FK_PCRel_4) {
304 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
307 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx);
309 Expr = DispOp.getExpr();
312 // If we have an immoffset, add it to the expression.
313 if ((FixupKind == FK_Data_4 ||
314 FixupKind == FK_Data_8 ||
315 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
316 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr);
317 if (Kind != GOT_None) {
318 assert(ImmOffset == 0);
321 FixupKind = MCFixupKind(X86::reloc_global_offset_table8);
324 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
327 if (Kind == GOT_Normal)
329 } else if (Expr->getKind() == MCExpr::SymbolRef) {
330 if (HasSecRelSymbolRef(Expr)) {
331 FixupKind = MCFixupKind(FK_SecRel_4);
333 } else if (Expr->getKind() == MCExpr::Binary) {
334 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr);
335 if (HasSecRelSymbolRef(Bin->getLHS())
336 || HasSecRelSymbolRef(Bin->getRHS())) {
337 FixupKind = MCFixupKind(FK_SecRel_4);
342 // If the fixup is pc-relative, we need to bias the value to be relative to
343 // the start of the field, not the end of the field.
344 if (FixupKind == FK_PCRel_4 ||
345 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
346 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
348 if (FixupKind == FK_PCRel_2)
350 if (FixupKind == FK_PCRel_1)
354 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
357 // Emit a symbolic constant as a fixup and 4 zeros.
358 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc));
359 EmitConstant(0, Size, CurByte, OS);
362 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
363 unsigned RegOpcodeField,
364 uint64_t TSFlags, unsigned &CurByte,
366 SmallVectorImpl<MCFixup> &Fixups,
367 const MCSubtargetInfo &STI) const{
368 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
369 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
370 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
371 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
372 unsigned BaseReg = Base.getReg();
373 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
375 // Handle %rip relative addressing.
376 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
377 assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode");
378 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
379 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
381 unsigned FixupKind = X86::reloc_riprel_4byte;
383 // movq loads are handled with a special relocation form which allows the
384 // linker to eliminate some loads for GOT references which end up in the
385 // same linkage unit.
386 if (MI.getOpcode() == X86::MOV64rm)
387 FixupKind = X86::reloc_riprel_4byte_movq_load;
389 // rip-relative addressing is actually relative to the *next* instruction.
390 // Since an immediate can follow the mod/rm byte for an instruction, this
391 // means that we need to bias the immediate field of the instruction with
392 // the size of the immediate field. If we have this case, add it into the
393 // expression to emit.
394 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
396 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind),
397 CurByte, OS, Fixups, -ImmSize);
401 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
403 // 16-bit addressing forms of the ModR/M byte have a different encoding for
404 // the R/M field and are far more limited in which registers can be used.
405 if (Is16BitMemOperand(MI, Op, STI)) {
407 // For 32-bit addressing, the row and column values in Table 2-2 are
408 // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
409 // some special cases. And GetX86RegNum reflects that numbering.
410 // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
411 // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
412 // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
413 // while values 0-3 indicate the allowed combinations (base+index) of
414 // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
416 // R16Table[] is a lookup from the normal RegNo, to the row values from
417 // Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
418 static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 };
419 unsigned RMfield = R16Table[BaseRegNo];
421 assert(RMfield && "invalid 16-bit base register");
423 if (IndexReg.getReg()) {
424 unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)];
426 assert(IndexReg16 && "invalid 16-bit index register");
427 // We must have one of SI/DI (4,5), and one of BP/BX (6,7).
428 assert(((IndexReg16 ^ RMfield) & 2) &&
429 "invalid 16-bit base/index register combination");
430 assert(Scale.getImm() == 1 &&
431 "invalid scale for 16-bit memory reference");
433 // Allow base/index to appear in either order (although GAS doesn't).
435 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
437 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
440 if (Disp.isImm() && isDisp8(Disp.getImm())) {
441 if (Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
442 // There is no displacement; just the register.
443 EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS);
446 // Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
447 EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS);
448 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
451 // This is the [REG]+disp16 case.
452 EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS);
454 // There is no BaseReg; this is the plain [disp16] case.
455 EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS);
458 // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
459 EmitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups);
463 // Determine whether a SIB byte is needed.
464 // If no BaseReg, issue a RIP relative instruction only if the MCE can
465 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
466 // 2-7) and absolute references.
468 if (// The SIB byte must be used if there is an index register.
469 IndexReg.getReg() == 0 &&
470 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
471 // encode to an R/M value of 4, which indicates that a SIB byte is
473 BaseRegNo != N86::ESP &&
474 // If there is no base register and we're in 64-bit mode, we need a SIB
475 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
476 (!is64BitMode(STI) || BaseReg != 0)) {
478 if (BaseReg == 0) { // [disp32] in X86-32 mode
479 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
480 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups);
484 // If the base is not EBP/ESP and there is no displacement, use simple
485 // indirect register encoding, this handles addresses like [EAX]. The
486 // encoding for [EBP] with no displacement means [disp32] so we handle it
487 // by emitting a displacement of 0 below.
488 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
489 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
493 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
495 if (!HasEVEX && isDisp8(Disp.getImm())) {
496 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
497 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
500 // Try EVEX compressed 8-bit displacement first; if failed, fall back to
501 // 32-bit displacement.
503 if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
504 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
505 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups,
506 CDisp8 - Disp.getImm());
511 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
512 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
513 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
518 // We need a SIB byte, so start by outputting the ModR/M byte first
519 assert(IndexReg.getReg() != X86::ESP &&
520 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
522 bool ForceDisp32 = false;
523 bool ForceDisp8 = false;
527 // If there is no base register, we emit the special case SIB byte with
528 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
529 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
531 } else if (!Disp.isImm()) {
532 // Emit the normal disp32 encoding.
533 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
535 } else if (Disp.getImm() == 0 &&
536 // Base reg can't be anything that ends up with '5' as the base
537 // reg, it is the magic [*] nomenclature that indicates no base.
538 BaseRegNo != N86::EBP) {
539 // Emit no displacement ModR/M byte
540 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
541 } else if (!HasEVEX && isDisp8(Disp.getImm())) {
542 // Emit the disp8 encoding.
543 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
544 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
545 } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
546 // Emit the disp8 encoding.
547 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
548 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
549 ImmOffset = CDisp8 - Disp.getImm();
551 // Emit the normal disp32 encoding.
552 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
555 // Calculate what the SS field value should be...
556 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
557 unsigned SS = SSTable[Scale.getImm()];
560 // Handle the SIB byte for the case where there is no base, see Intel
561 // Manual 2A, table 2-7. The displacement has already been output.
563 if (IndexReg.getReg())
564 IndexRegNo = GetX86RegNum(IndexReg);
565 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
567 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
570 if (IndexReg.getReg())
571 IndexRegNo = GetX86RegNum(IndexReg);
573 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
574 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
577 // Do we need to output a displacement?
579 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset);
580 else if (ForceDisp32 || Disp.getImm() != 0)
581 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
582 CurByte, OS, Fixups);
585 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
587 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
588 int MemOperand, const MCInst &MI,
589 const MCInstrDesc &Desc,
590 raw_ostream &OS) const {
591 assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
593 uint64_t Encoding = TSFlags & X86II::EncodingMask;
594 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
595 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
596 bool HasVEX_4VOp3 = TSFlags & X86II::VEX_4VOp3;
597 bool HasMemOp4 = TSFlags & X86II::MemOp4;
598 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
600 // VEX_R: opcode externsion equivalent to REX.R in
601 // 1's complement (inverted) form
603 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
604 // 0: Same as REX_R=1 (64 bit mode only)
606 unsigned char VEX_R = 0x1;
607 unsigned char EVEX_R2 = 0x1;
609 // VEX_X: equivalent to REX.X, only used when a
610 // register is used for index in SIB Byte.
612 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
613 // 0: Same as REX.X=1 (64-bit mode only)
614 unsigned char VEX_X = 0x1;
618 // 1: Same as REX_B=0 (ignored in 32-bit mode)
619 // 0: Same as REX_B=1 (64 bit mode only)
621 unsigned char VEX_B = 0x1;
623 // VEX_W: opcode specific (use like REX.W, or used for
624 // opcode extension, or ignored, depending on the opcode byte)
625 unsigned char VEX_W = 0;
627 // VEX_5M (VEX m-mmmmm field):
629 // 0b00000: Reserved for future use
630 // 0b00001: implied 0F leading opcode
631 // 0b00010: implied 0F 38 leading opcode bytes
632 // 0b00011: implied 0F 3A leading opcode bytes
633 // 0b00100-0b11111: Reserved for future use
634 // 0b01000: XOP map select - 08h instructions with imm byte
635 // 0b01001: XOP map select - 09h instructions with no imm byte
636 // 0b01010: XOP map select - 0Ah instructions with imm dword
637 unsigned char VEX_5M = 0;
639 // VEX_4V (VEX vvvv field): a register specifier
640 // (in 1's complement form) or 1111 if unused.
641 unsigned char VEX_4V = 0xf;
642 unsigned char EVEX_V2 = 0x1;
644 // VEX_L (Vector Length):
646 // 0: scalar or 128-bit vector
649 unsigned char VEX_L = 0;
650 unsigned char EVEX_L2 = 0;
652 // VEX_PP: opcode extension providing equivalent
653 // functionality of a SIMD prefix
660 unsigned char VEX_PP = 0;
663 unsigned char EVEX_U = 1; // Always '1' so far
666 unsigned char EVEX_z = 0;
669 unsigned char EVEX_b = 0;
672 unsigned char EVEX_rc = 0;
675 unsigned char EVEX_aaa = 0;
677 bool EncodeRC = false;
679 if (TSFlags & X86II::VEX_W)
682 if (TSFlags & X86II::VEX_L)
684 if (TSFlags & X86II::EVEX_L2)
687 if (HasEVEX_K && (TSFlags & X86II::EVEX_Z))
690 if ((TSFlags & X86II::EVEX_B))
693 switch (TSFlags & X86II::OpPrefixMask) {
694 default: break; // VEX_PP already correct
695 case X86II::PD: VEX_PP = 0x1; break; // 66
696 case X86II::XS: VEX_PP = 0x2; break; // F3
697 case X86II::XD: VEX_PP = 0x3; break; // F2
700 switch (TSFlags & X86II::OpMapMask) {
701 default: llvm_unreachable("Invalid prefix!");
702 case X86II::TB: VEX_5M = 0x1; break; // 0F
703 case X86II::T8: VEX_5M = 0x2; break; // 0F 38
704 case X86II::TA: VEX_5M = 0x3; break; // 0F 3A
705 case X86II::XOP8: VEX_5M = 0x8; break;
706 case X86II::XOP9: VEX_5M = 0x9; break;
707 case X86II::XOPA: VEX_5M = 0xA; break;
710 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
711 unsigned NumOps = Desc.getNumOperands();
712 unsigned CurOp = X86II::getOperandBias(Desc);
714 switch (TSFlags & X86II::FormMask) {
715 default: llvm_unreachable("Unexpected form in EmitVEXOpcodePrefix!");
718 case X86II::MRMDestMem: {
719 // MRMDestMem instructions forms:
720 // MemAddr, src1(ModR/M)
721 // MemAddr, src1(VEX_4V), src2(ModR/M)
722 // MemAddr, src1(ModR/M), imm8
724 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
725 X86::AddrBaseReg).getReg()))
727 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
728 X86::AddrIndexReg).getReg()))
730 if (X86II::is32ExtendedReg(MI.getOperand(MemOperand +
731 X86::AddrIndexReg).getReg()))
734 CurOp += X86::AddrNumOperands;
737 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
740 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
741 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
746 const MCOperand &MO = MI.getOperand(CurOp);
748 if (X86II::isX86_64ExtendedReg(MO.getReg()))
750 if (X86II::is32ExtendedReg(MO.getReg()))
755 case X86II::MRMSrcMem:
756 // MRMSrcMem instructions forms:
757 // src1(ModR/M), MemAddr
758 // src1(ModR/M), src2(VEX_4V), MemAddr
759 // src1(ModR/M), MemAddr, imm8
760 // src1(ModR/M), MemAddr, src2(VEX_I8IMM)
763 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
764 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
765 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
767 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
772 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
775 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
776 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
781 if (X86II::isX86_64ExtendedReg(
782 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
784 if (X86II::isX86_64ExtendedReg(
785 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
787 if (X86II::is32ExtendedReg(MI.getOperand(MemOperand +
788 X86::AddrIndexReg).getReg()))
792 // Instruction format for 4VOp3:
793 // src1(ModR/M), MemAddr, src3(VEX_4V)
794 // CurOp points to start of the MemoryOperand,
795 // it skips TIED_TO operands if exist, then increments past src1.
796 // CurOp + X86::AddrNumOperands will point to src3.
797 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands);
799 case X86II::MRM0m: case X86II::MRM1m:
800 case X86II::MRM2m: case X86II::MRM3m:
801 case X86II::MRM4m: case X86II::MRM5m:
802 case X86II::MRM6m: case X86II::MRM7m: {
803 // MRM[0-9]m instructions forms:
805 // src1(VEX_4V), MemAddr
807 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
808 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
814 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
816 if (X86II::isX86_64ExtendedReg(
817 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
819 if (X86II::isX86_64ExtendedReg(
820 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
824 case X86II::MRMSrcReg:
825 // MRMSrcReg instructions forms:
826 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
827 // dst(ModR/M), src1(ModR/M)
828 // dst(ModR/M), src1(ModR/M), imm8
831 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
832 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
833 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
835 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
840 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
843 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
844 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
849 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
852 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
854 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
858 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
861 unsigned RcOperand = NumOps-1;
862 assert(RcOperand >= CurOp);
863 EVEX_rc = MI.getOperand(RcOperand).getImm() & 0x3;
868 case X86II::MRMDestReg:
869 // MRMDestReg instructions forms:
870 // dst(ModR/M), src(ModR/M)
871 // dst(ModR/M), src(ModR/M), imm8
872 // dst(ModR/M), src1(VEX_4V), src2(ModR/M)
873 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
875 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
880 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
883 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
884 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
889 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
891 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
896 case X86II::MRM0r: case X86II::MRM1r:
897 case X86II::MRM2r: case X86II::MRM3r:
898 case X86II::MRM4r: case X86II::MRM5r:
899 case X86II::MRM6r: case X86II::MRM7r:
900 // MRM0r-MRM7r instructions forms:
901 // dst(VEX_4V), src(ModR/M), imm8
903 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
904 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
909 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
911 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
913 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
918 if (Encoding == X86II::VEX || Encoding == X86II::XOP) {
919 // VEX opcode prefix can have 2 or 3 bytes
922 // +-----+ +--------------+ +-------------------+
923 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
924 // +-----+ +--------------+ +-------------------+
926 // +-----+ +-------------------+
927 // | C5h | | R | vvvv | L | pp |
928 // +-----+ +-------------------+
930 // XOP uses a similar prefix:
931 // +-----+ +--------------+ +-------------------+
932 // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp |
933 // +-----+ +--------------+ +-------------------+
934 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
936 // Can we use the 2 byte VEX prefix?
937 if (Encoding == X86II::VEX && VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) {
938 EmitByte(0xC5, CurByte, OS);
939 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
944 EmitByte(Encoding == X86II::XOP ? 0x8F : 0xC4, CurByte, OS);
945 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
946 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
948 assert(Encoding == X86II::EVEX && "unknown encoding!");
949 // EVEX opcode prefix can have 4 bytes
951 // +-----+ +--------------+ +-------------------+ +------------------------+
952 // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
953 // +-----+ +--------------+ +-------------------+ +------------------------+
954 assert((VEX_5M & 0x3) == VEX_5M
955 && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!");
959 EmitByte(0x62, CurByte, OS);
960 EmitByte((VEX_R << 7) |
964 VEX_5M, CurByte, OS);
965 EmitByte((VEX_W << 7) |
968 VEX_PP, CurByte, OS);
970 EmitByte((EVEX_z << 7) |
974 EVEX_aaa, CurByte, OS);
976 EmitByte((EVEX_z << 7) |
981 EVEX_aaa, CurByte, OS);
985 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
986 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
987 /// size, and 3) use of X86-64 extended registers.
988 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
989 const MCInstrDesc &Desc) {
991 if (TSFlags & X86II::REX_W)
992 REX |= 1 << 3; // set REX.W
994 if (MI.getNumOperands() == 0) return REX;
996 unsigned NumOps = MI.getNumOperands();
997 // FIXME: MCInst should explicitize the two-addrness.
998 bool isTwoAddr = NumOps > 1 &&
999 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
1001 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
1002 unsigned i = isTwoAddr ? 1 : 0;
1003 for (; i != NumOps; ++i) {
1004 const MCOperand &MO = MI.getOperand(i);
1005 if (!MO.isReg()) continue;
1006 unsigned Reg = MO.getReg();
1007 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue;
1008 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
1009 // that returns non-zero.
1010 REX |= 0x40; // REX fixed encoding prefix
1014 switch (TSFlags & X86II::FormMask) {
1015 case X86II::MRMSrcReg:
1016 if (MI.getOperand(0).isReg() &&
1017 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1018 REX |= 1 << 2; // set REX.R
1019 i = isTwoAddr ? 2 : 1;
1020 for (; i != NumOps; ++i) {
1021 const MCOperand &MO = MI.getOperand(i);
1022 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
1023 REX |= 1 << 0; // set REX.B
1026 case X86II::MRMSrcMem: {
1027 if (MI.getOperand(0).isReg() &&
1028 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1029 REX |= 1 << 2; // set REX.R
1031 i = isTwoAddr ? 2 : 1;
1032 for (; i != NumOps; ++i) {
1033 const MCOperand &MO = MI.getOperand(i);
1035 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1036 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
1043 case X86II::MRM0m: case X86II::MRM1m:
1044 case X86II::MRM2m: case X86II::MRM3m:
1045 case X86II::MRM4m: case X86II::MRM5m:
1046 case X86II::MRM6m: case X86II::MRM7m:
1047 case X86II::MRMDestMem: {
1048 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
1049 i = isTwoAddr ? 1 : 0;
1050 if (NumOps > e && MI.getOperand(e).isReg() &&
1051 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
1052 REX |= 1 << 2; // set REX.R
1054 for (; i != e; ++i) {
1055 const MCOperand &MO = MI.getOperand(i);
1057 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1058 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
1065 if (MI.getOperand(0).isReg() &&
1066 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
1067 REX |= 1 << 0; // set REX.B
1068 i = isTwoAddr ? 2 : 1;
1069 for (unsigned e = NumOps; i != e; ++i) {
1070 const MCOperand &MO = MI.getOperand(i);
1071 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
1072 REX |= 1 << 2; // set REX.R
1079 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
1080 void X86MCCodeEmitter::EmitSegmentOverridePrefix(unsigned &CurByte,
1081 unsigned SegOperand,
1083 raw_ostream &OS) const {
1084 // Check for explicit segment override on memory operand.
1085 switch (MI.getOperand(SegOperand).getReg()) {
1086 default: llvm_unreachable("Unknown segment register!");
1088 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
1089 case X86::SS: EmitByte(0x36, CurByte, OS); break;
1090 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
1091 case X86::ES: EmitByte(0x26, CurByte, OS); break;
1092 case X86::FS: EmitByte(0x64, CurByte, OS); break;
1093 case X86::GS: EmitByte(0x65, CurByte, OS); break;
1097 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
1099 /// MemOperand is the operand # of the start of a memory operand if present. If
1100 /// Not present, it is -1.
1101 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
1102 int MemOperand, const MCInst &MI,
1103 const MCInstrDesc &Desc,
1104 const MCSubtargetInfo &STI,
1105 raw_ostream &OS) const {
1107 // Emit the operand size opcode prefix as needed.
1108 if ((TSFlags & X86II::OpSizeMask) == (is16BitMode(STI) ? X86II::OpSize32
1110 EmitByte(0x66, CurByte, OS);
1112 // Emit the LOCK opcode prefix.
1113 if (TSFlags & X86II::LOCK)
1114 EmitByte(0xF0, CurByte, OS);
1116 switch (TSFlags & X86II::OpPrefixMask) {
1117 case X86II::PD: // 66
1118 EmitByte(0x66, CurByte, OS);
1120 case X86II::XS: // F3
1121 EmitByte(0xF3, CurByte, OS);
1123 case X86II::XD: // F2
1124 EmitByte(0xF2, CurByte, OS);
1128 // Handle REX prefix.
1129 // FIXME: Can this come before F2 etc to simplify emission?
1130 if (is64BitMode(STI)) {
1131 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
1132 EmitByte(0x40 | REX, CurByte, OS);
1135 // 0x0F escape code must be emitted just before the opcode.
1136 switch (TSFlags & X86II::OpMapMask) {
1137 case X86II::TB: // Two-byte opcode map
1138 case X86II::T8: // 0F 38
1139 case X86II::TA: // 0F 3A
1140 EmitByte(0x0F, CurByte, OS);
1144 switch (TSFlags & X86II::OpMapMask) {
1145 case X86II::T8: // 0F 38
1146 EmitByte(0x38, CurByte, OS);
1148 case X86II::TA: // 0F 3A
1149 EmitByte(0x3A, CurByte, OS);
1154 void X86MCCodeEmitter::
1155 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1156 SmallVectorImpl<MCFixup> &Fixups,
1157 const MCSubtargetInfo &STI) const {
1158 unsigned Opcode = MI.getOpcode();
1159 const MCInstrDesc &Desc = MCII.get(Opcode);
1160 uint64_t TSFlags = Desc.TSFlags;
1162 // Pseudo instructions don't get encoded.
1163 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
1166 unsigned NumOps = Desc.getNumOperands();
1167 unsigned CurOp = X86II::getOperandBias(Desc);
1169 // Keep track of the current byte being emitted.
1170 unsigned CurByte = 0;
1172 // Encoding type for this instruction.
1173 uint64_t Encoding = TSFlags & X86II::EncodingMask;
1175 // It uses the VEX.VVVV field?
1176 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1177 bool HasVEX_4VOp3 = TSFlags & X86II::VEX_4VOp3;
1178 bool HasMemOp4 = TSFlags & X86II::MemOp4;
1179 const unsigned MemOp4_I8IMMOperand = 2;
1181 // It uses the EVEX.aaa field?
1182 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1183 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
1185 // Determine where the memory operand starts, if present.
1186 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
1187 if (MemoryOperand != -1) MemoryOperand += CurOp;
1189 // Emit segment override opcode prefix as needed.
1190 if (MemoryOperand >= 0)
1191 EmitSegmentOverridePrefix(CurByte, MemoryOperand+X86::AddrSegmentReg,
1194 // Emit the repeat opcode prefix as needed.
1195 if (TSFlags & X86II::REP)
1196 EmitByte(0xF3, CurByte, OS);
1198 // Emit the address size opcode prefix as needed.
1199 bool need_address_override;
1200 uint64_t AdSize = TSFlags & X86II::AdSizeMask;
1201 if ((is16BitMode(STI) && AdSize == X86II::AdSize32) ||
1202 (is32BitMode(STI) && AdSize == X86II::AdSize16) ||
1203 (is64BitMode(STI) && AdSize == X86II::AdSize32)) {
1204 need_address_override = true;
1205 } else if (MemoryOperand < 0) {
1206 need_address_override = false;
1207 } else if (is64BitMode(STI)) {
1208 assert(!Is16BitMemOperand(MI, MemoryOperand, STI));
1209 need_address_override = Is32BitMemOperand(MI, MemoryOperand);
1210 } else if (is32BitMode(STI)) {
1211 assert(!Is64BitMemOperand(MI, MemoryOperand));
1212 need_address_override = Is16BitMemOperand(MI, MemoryOperand, STI);
1214 assert(is16BitMode(STI));
1215 assert(!Is64BitMemOperand(MI, MemoryOperand));
1216 need_address_override = !Is16BitMemOperand(MI, MemoryOperand, STI);
1219 if (need_address_override)
1220 EmitByte(0x67, CurByte, OS);
1223 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS);
1225 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1227 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1229 if (TSFlags & X86II::Has3DNow0F0FOpcode)
1230 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1232 unsigned SrcRegNum = 0;
1233 switch (TSFlags & X86II::FormMask) {
1234 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
1235 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1237 llvm_unreachable("Pseudo instruction shouldn't be emitted");
1238 case X86II::RawFrmDstSrc: {
1239 unsigned siReg = MI.getOperand(1).getReg();
1240 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) ||
1241 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) ||
1242 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) &&
1243 "SI and DI register sizes do not match");
1244 // Emit segment override opcode prefix as needed (not for %ds).
1245 if (MI.getOperand(2).getReg() != X86::DS)
1246 EmitSegmentOverridePrefix(CurByte, 2, MI, OS);
1247 // Emit AdSize prefix as needed.
1248 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1249 (is32BitMode(STI) && siReg == X86::SI))
1250 EmitByte(0x67, CurByte, OS);
1251 CurOp += 3; // Consume operands.
1252 EmitByte(BaseOpcode, CurByte, OS);
1255 case X86II::RawFrmSrc: {
1256 unsigned siReg = MI.getOperand(0).getReg();
1257 // Emit segment override opcode prefix as needed (not for %ds).
1258 if (MI.getOperand(1).getReg() != X86::DS)
1259 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1260 // Emit AdSize prefix as needed.
1261 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1262 (is32BitMode(STI) && siReg == X86::SI))
1263 EmitByte(0x67, CurByte, OS);
1264 CurOp += 2; // Consume operands.
1265 EmitByte(BaseOpcode, CurByte, OS);
1268 case X86II::RawFrmDst: {
1269 unsigned siReg = MI.getOperand(0).getReg();
1270 // Emit AdSize prefix as needed.
1271 if ((!is32BitMode(STI) && siReg == X86::EDI) ||
1272 (is32BitMode(STI) && siReg == X86::DI))
1273 EmitByte(0x67, CurByte, OS);
1274 ++CurOp; // Consume operand.
1275 EmitByte(BaseOpcode, CurByte, OS);
1279 EmitByte(BaseOpcode, CurByte, OS);
1281 case X86II::RawFrmMemOffs:
1282 // Emit segment override opcode prefix as needed.
1283 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1284 EmitByte(BaseOpcode, CurByte, OS);
1285 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1286 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1287 CurByte, OS, Fixups);
1288 ++CurOp; // skip segment operand
1290 case X86II::RawFrmImm8:
1291 EmitByte(BaseOpcode, CurByte, OS);
1292 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1293 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1294 CurByte, OS, Fixups);
1295 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte,
1298 case X86II::RawFrmImm16:
1299 EmitByte(BaseOpcode, CurByte, OS);
1300 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1301 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1302 CurByte, OS, Fixups);
1303 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte,
1307 case X86II::AddRegFrm:
1308 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
1311 case X86II::MRMDestReg:
1312 EmitByte(BaseOpcode, CurByte, OS);
1313 SrcRegNum = CurOp + 1;
1315 if (HasEVEX_K) // Skip writemask
1318 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1321 EmitRegModRMByte(MI.getOperand(CurOp),
1322 GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS);
1323 CurOp = SrcRegNum + 1;
1326 case X86II::MRMDestMem:
1327 EmitByte(BaseOpcode, CurByte, OS);
1328 SrcRegNum = CurOp + X86::AddrNumOperands;
1330 if (HasEVEX_K) // Skip writemask
1333 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1336 EmitMemModRMByte(MI, CurOp,
1337 GetX86RegNum(MI.getOperand(SrcRegNum)),
1338 TSFlags, CurByte, OS, Fixups, STI);
1339 CurOp = SrcRegNum + 1;
1342 case X86II::MRMSrcReg:
1343 EmitByte(BaseOpcode, CurByte, OS);
1344 SrcRegNum = CurOp + 1;
1346 if (HasEVEX_K) // Skip writemask
1349 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1352 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
1355 EmitRegModRMByte(MI.getOperand(SrcRegNum),
1356 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
1358 // 2 operands skipped with HasMemOp4, compensate accordingly
1359 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
1362 // do not count the rounding control operand
1367 case X86II::MRMSrcMem: {
1368 int AddrOperands = X86::AddrNumOperands;
1369 unsigned FirstMemOp = CurOp+1;
1371 if (HasEVEX_K) { // Skip writemask
1378 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1380 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
1383 EmitByte(BaseOpcode, CurByte, OS);
1385 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
1386 TSFlags, CurByte, OS, Fixups, STI);
1387 CurOp += AddrOperands + 1;
1394 case X86II::MRM0r: case X86II::MRM1r:
1395 case X86II::MRM2r: case X86II::MRM3r:
1396 case X86II::MRM4r: case X86II::MRM5r:
1397 case X86II::MRM6r: case X86II::MRM7r: {
1398 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1400 if (HasEVEX_K) // Skip writemask
1402 EmitByte(BaseOpcode, CurByte, OS);
1403 uint64_t Form = TSFlags & X86II::FormMask;
1404 EmitRegModRMByte(MI.getOperand(CurOp++),
1405 (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r,
1411 case X86II::MRM0m: case X86II::MRM1m:
1412 case X86II::MRM2m: case X86II::MRM3m:
1413 case X86II::MRM4m: case X86II::MRM5m:
1414 case X86II::MRM6m: case X86II::MRM7m: {
1415 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1417 if (HasEVEX_K) // Skip writemask
1419 EmitByte(BaseOpcode, CurByte, OS);
1420 uint64_t Form = TSFlags & X86II::FormMask;
1421 EmitMemModRMByte(MI, CurOp, (Form == X86II::MRMXm) ? 0 : Form-X86II::MRM0m,
1422 TSFlags, CurByte, OS, Fixups, STI);
1423 CurOp += X86::AddrNumOperands;
1426 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
1427 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
1428 case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
1429 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
1430 case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
1431 case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
1432 case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
1433 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
1434 case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
1435 case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
1436 case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
1437 case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
1438 case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
1439 case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
1440 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
1441 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
1442 case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
1443 case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
1444 case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
1445 case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
1446 case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
1448 EmitByte(BaseOpcode, CurByte, OS);
1450 uint64_t Form = TSFlags & X86II::FormMask;
1451 EmitByte(0xC0 + Form - X86II::MRM_C0, CurByte, OS);
1455 // If there is a remaining operand, it must be a trailing immediate. Emit it
1456 // according to the right size for the instruction. Some instructions
1457 // (SSE4a extrq and insertq) have two trailing immediates.
1458 while (CurOp != NumOps && NumOps - CurOp <= 2) {
1459 // The last source register of a 4 operand instruction in AVX is encoded
1460 // in bits[7:4] of a immediate byte.
1461 if (TSFlags & X86II::VEX_I8IMM) {
1462 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
1465 unsigned RegNum = GetX86RegNum(MO) << 4;
1466 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1468 // If there is an additional 5th operand it must be an immediate, which
1469 // is encoded in bits[3:0]
1470 if (CurOp != NumOps) {
1471 const MCOperand &MIMM = MI.getOperand(CurOp++);
1473 unsigned Val = MIMM.getImm();
1474 assert(Val < 16 && "Immediate operand value out of range");
1478 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1,
1479 CurByte, OS, Fixups);
1481 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(),
1482 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
1483 CurByte, OS, Fixups);
1487 if (TSFlags & X86II::Has3DNow0F0FOpcode)
1488 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1492 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1493 errs() << "Cannot encode all operands of: ";