1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "X86MCTargetDesc.h"
15 #include "X86MCAsmInfo.h"
16 #include "InstPrinter/X86ATTInstPrinter.h"
17 #include "InstPrinter/X86IntelInstPrinter.h"
18 #include "llvm/MC/MachineLocation.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCInstrAnalysis.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/Support/Host.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/TargetRegistry.h"
30 #define GET_REGINFO_MC_DESC
31 #include "X86GenRegisterInfo.inc"
33 #define GET_INSTRINFO_MC_DESC
34 #include "X86GenInstrInfo.inc"
36 #define GET_SUBTARGETINFO_MC_DESC
37 #include "X86GenSubtargetInfo.inc"
46 std::string X86_MC::ParseX86Triple(StringRef TT) {
49 if (TheTriple.getArch() == Triple::x86_64)
56 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
57 /// specified arguments. If we can't run cpuid on the host, return true.
58 bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
59 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
60 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
62 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
63 asm ("movq\t%%rbx, %%rsi\n\t"
65 "xchgq\t%%rbx, %%rsi\n\t"
72 #elif defined(_MSC_VER)
74 __cpuid(registers, value);
83 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
85 asm ("movl\t%%ebx, %%esi\n\t"
87 "xchgl\t%%ebx, %%esi\n\t"
94 #elif defined(_MSC_VER)
99 mov dword ptr [esi],eax
101 mov dword ptr [esi],ebx
103 mov dword ptr [esi],ecx
105 mov dword ptr [esi],edx
116 /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
117 /// 4 values in the specified arguments. If we can't run cpuid on the host,
119 bool X86_MC::GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX,
120 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
121 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
122 #if defined(__GNUC__)
123 // gcc desn't know cpuid would clobber ebx/rbx. Preseve it manually.
124 asm ("movq\t%%rbx, %%rsi\n\t"
126 "xchgq\t%%rbx, %%rsi\n\t"
134 #elif defined(_MSC_VER)
135 // __cpuidex was added in MSVC++ 9.0 SP1
136 #if (_MSC_VER > 1500) || (_MSC_VER == 1500 && _MSC_FULL_VER >= 150030729)
138 __cpuidex(registers, value, subleaf);
139 *rEAX = registers[0];
140 *rEBX = registers[1];
141 *rECX = registers[2];
142 *rEDX = registers[3];
150 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
151 #if defined(__GNUC__)
152 asm ("movl\t%%ebx, %%esi\n\t"
154 "xchgl\t%%ebx, %%esi\n\t"
162 #elif defined(_MSC_VER)
168 mov dword ptr [esi],eax
170 mov dword ptr [esi],ebx
172 mov dword ptr [esi],ecx
174 mov dword ptr [esi],edx
185 void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
187 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
188 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
189 if (Family == 6 || Family == 0xf) {
191 // Examine extended family ID if family ID is F.
192 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
193 // Examine extended model ID if family ID is 6 or F.
194 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
198 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
199 Triple TheTriple(TT);
200 if (TheTriple.getArch() == Triple::x86_64)
201 return DWARFFlavour::X86_64;
203 if (TheTriple.isOSDarwin())
204 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
205 if (TheTriple.getOS() == Triple::MinGW32 ||
206 TheTriple.getOS() == Triple::Cygwin)
207 // Unsupported by now, just quick fallback
208 return DWARFFlavour::X86_32_Generic;
209 return DWARFFlavour::X86_32_Generic;
212 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
213 // FIXME: TableGen these.
214 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
215 unsigned SEH = MRI->getEncodingValue(Reg);
216 MRI->mapLLVMRegToSEHReg(Reg, SEH);
220 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
222 std::string ArchFS = X86_MC::ParseX86Triple(TT);
225 ArchFS = ArchFS + "," + FS.str();
230 std::string CPUName = CPU;
231 if (CPUName.empty()) {
232 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
233 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
234 CPUName = sys::getHostCPUName();
240 MCSubtargetInfo *X = new MCSubtargetInfo();
241 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
245 static MCInstrInfo *createX86MCInstrInfo() {
246 MCInstrInfo *X = new MCInstrInfo();
247 InitX86MCInstrInfo(X);
251 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
252 Triple TheTriple(TT);
253 unsigned RA = (TheTriple.getArch() == Triple::x86_64)
254 ? X86::RIP // Should have dwarf #16.
255 : X86::EIP; // Should have dwarf #8.
257 MCRegisterInfo *X = new MCRegisterInfo();
258 InitX86MCRegisterInfo(X, RA,
259 X86_MC::getDwarfRegFlavour(TT, false),
260 X86_MC::getDwarfRegFlavour(TT, true));
261 X86_MC::InitLLVM2SEHRegisterMapping(X);
265 static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) {
266 Triple TheTriple(TT);
267 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
270 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
272 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
274 MAI = new X86MCAsmInfoDarwin(TheTriple);
275 } else if (TheTriple.getEnvironment() == Triple::ELF) {
276 // Force the use of an ELF container.
277 MAI = new X86ELFMCAsmInfo(TheTriple);
278 } else if (TheTriple.getOS() == Triple::Win32) {
279 MAI = new X86MCAsmInfoMicrosoft(TheTriple);
280 } else if (TheTriple.getOS() == Triple::MinGW32 || TheTriple.getOS() == Triple::Cygwin) {
281 MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
283 // The default is ELF.
284 MAI = new X86ELFMCAsmInfo(TheTriple);
287 // Initialize initial frame state.
288 // Calculate amount of bytes used for return address storing
289 int stackGrowth = is64Bit ? -8 : -4;
291 // Initial state of the frame pointer is esp+stackGrowth.
292 MachineLocation Dst(MachineLocation::VirtualFP);
293 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
294 MAI->addInitialFrameState(0, Dst, Src);
296 // Add return address to move list
297 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
298 MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP);
299 MAI->addInitialFrameState(0, CSDst, CSSrc);
304 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
306 CodeGenOpt::Level OL) {
307 MCCodeGenInfo *X = new MCCodeGenInfo();
310 bool is64Bit = T.getArch() == Triple::x86_64;
312 if (RM == Reloc::Default) {
313 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
314 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
315 // use static relocation model by default.
316 if (T.isOSDarwin()) {
320 RM = Reloc::DynamicNoPIC;
321 } else if (T.isOSWindows() && is64Bit)
327 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
328 // is defined as a model for code which may be used in static or dynamic
329 // executables but not necessarily a shared library. On X86-32 we just
330 // compile in -static mode, in x86-64 we use PIC.
331 if (RM == Reloc::DynamicNoPIC) {
334 else if (!T.isOSDarwin())
338 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
339 // the Mach-O file format doesn't support it.
340 if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
343 // For static codegen, if we're not already set, use Small codegen.
344 if (CM == CodeModel::Default)
345 CM = CodeModel::Small;
346 else if (CM == CodeModel::JITDefault)
347 // 64-bit JIT places everything in the same buffer except external funcs.
348 CM = is64Bit ? CodeModel::Large : CodeModel::Small;
350 X->InitMCCodeGenInfo(RM, CM, OL);
354 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
355 MCContext &Ctx, MCAsmBackend &MAB,
357 MCCodeEmitter *_Emitter,
360 Triple TheTriple(TT);
362 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
363 return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll);
365 if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
366 return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll);
368 return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
371 static MCInstPrinter *createX86MCInstPrinter(const Target &T,
372 unsigned SyntaxVariant,
373 const MCAsmInfo &MAI,
374 const MCInstrInfo &MII,
375 const MCRegisterInfo &MRI,
376 const MCSubtargetInfo &STI) {
377 if (SyntaxVariant == 0)
378 return new X86ATTInstPrinter(MAI, MII, MRI);
379 if (SyntaxVariant == 1)
380 return new X86IntelInstPrinter(MAI, MII, MRI);
384 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
385 return new MCInstrAnalysis(Info);
388 // Force static initialization.
389 extern "C" void LLVMInitializeX86TargetMC() {
390 // Register the MC asm info.
391 RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
392 RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
394 // Register the MC codegen info.
395 RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo);
396 RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo);
398 // Register the MC instruction info.
399 TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
400 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
402 // Register the MC register info.
403 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
404 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
406 // Register the MC subtarget info.
407 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
408 X86_MC::createX86MCSubtargetInfo);
409 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
410 X86_MC::createX86MCSubtargetInfo);
412 // Register the MC instruction analyzer.
413 TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target,
414 createX86MCInstrAnalysis);
415 TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target,
416 createX86MCInstrAnalysis);
418 // Register the code emitter.
419 TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target,
420 createX86MCCodeEmitter);
421 TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target,
422 createX86MCCodeEmitter);
424 // Register the asm backend.
425 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
426 createX86_32AsmBackend);
427 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
428 createX86_64AsmBackend);
430 // Register the object streamer.
431 TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target,
433 TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target,
436 // Register the MCInstPrinter.
437 TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,
438 createX86MCInstPrinter);
439 TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,
440 createX86MCInstPrinter);