1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "X86MCTargetDesc.h"
15 #include "X86MCAsmInfo.h"
16 #include "InstPrinter/X86ATTInstPrinter.h"
17 #include "InstPrinter/X86IntelInstPrinter.h"
18 #include "llvm/MC/MachineLocation.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCInstrAnalysis.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/Support/Host.h"
27 #include "llvm/Support/TargetRegistry.h"
29 #define GET_REGINFO_MC_DESC
30 #include "X86GenRegisterInfo.inc"
32 #define GET_INSTRINFO_MC_DESC
33 #include "X86GenInstrInfo.inc"
35 #define GET_SUBTARGETINFO_MC_DESC
36 #include "X86GenSubtargetInfo.inc"
41 std::string X86_MC::ParseX86Triple(StringRef TT) {
44 if (TheTriple.getArch() == Triple::x86_64)
51 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
52 /// specified arguments. If we can't run cpuid on the host, return true.
53 bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
54 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
55 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
57 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
58 asm ("movq\t%%rbx, %%rsi\n\t"
60 "xchgq\t%%rbx, %%rsi\n\t"
67 #elif defined(_MSC_VER)
69 __cpuid(registers, value);
76 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
78 asm ("movl\t%%ebx, %%esi\n\t"
80 "xchgl\t%%ebx, %%esi\n\t"
87 #elif defined(_MSC_VER)
92 mov dword ptr [esi],eax
94 mov dword ptr [esi],ebx
96 mov dword ptr [esi],ecx
98 mov dword ptr [esi],edx
106 /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
107 /// 4 values in the specified arguments. If we can't run cpuid on the host,
109 bool X86_MC::GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX,
110 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
111 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
112 #if defined(__GNUC__)
113 // gcc desn't know cpuid would clobber ebx/rbx. Preseve it manually.
114 asm ("movq\t%%rbx, %%rsi\n\t"
116 "xchgq\t%%rbx, %%rsi\n\t"
124 #elif defined(_MSC_VER)
125 // __cpuidex was added in MSVC++ 9.0 SP1
126 #if (_MSC_VER > 1500) || (_MSC_VER == 1500 && _MSC_FULL_VER >= 150030729)
128 __cpuidex(registers, value, subleaf);
129 *rEAX = registers[0];
130 *rEBX = registers[1];
131 *rECX = registers[2];
132 *rEDX = registers[3];
136 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
137 #if defined(__GNUC__)
138 asm ("movl\t%%ebx, %%esi\n\t"
140 "xchgl\t%%ebx, %%esi\n\t"
148 #elif defined(_MSC_VER)
154 mov dword ptr [esi],eax
156 mov dword ptr [esi],ebx
158 mov dword ptr [esi],ecx
160 mov dword ptr [esi],edx
168 void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
170 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
171 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
172 if (Family == 6 || Family == 0xf) {
174 // Examine extended family ID if family ID is F.
175 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
176 // Examine extended model ID if family ID is 6 or F.
177 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
181 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
182 Triple TheTriple(TT);
183 if (TheTriple.getArch() == Triple::x86_64)
184 return DWARFFlavour::X86_64;
186 if (TheTriple.isOSDarwin())
187 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
188 if (TheTriple.getOS() == Triple::MinGW32 ||
189 TheTriple.getOS() == Triple::Cygwin)
190 // Unsupported by now, just quick fallback
191 return DWARFFlavour::X86_32_Generic;
192 return DWARFFlavour::X86_32_Generic;
195 /// getX86RegNum - This function maps LLVM register identifiers to their X86
196 /// specific numbering, which is used in various places encoding instructions.
197 unsigned X86_MC::getX86RegNum(unsigned RegNo) {
199 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
200 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
201 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
202 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
203 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
205 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
207 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
209 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
212 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
214 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
216 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
218 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
220 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
222 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
224 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
226 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
229 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
230 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
231 return RegNo-X86::ST0;
233 case X86::XMM0: case X86::XMM8:
234 case X86::YMM0: case X86::YMM8: case X86::MM0:
236 case X86::XMM1: case X86::XMM9:
237 case X86::YMM1: case X86::YMM9: case X86::MM1:
239 case X86::XMM2: case X86::XMM10:
240 case X86::YMM2: case X86::YMM10: case X86::MM2:
242 case X86::XMM3: case X86::XMM11:
243 case X86::YMM3: case X86::YMM11: case X86::MM3:
245 case X86::XMM4: case X86::XMM12:
246 case X86::YMM4: case X86::YMM12: case X86::MM4:
248 case X86::XMM5: case X86::XMM13:
249 case X86::YMM5: case X86::YMM13: case X86::MM5:
251 case X86::XMM6: case X86::XMM14:
252 case X86::YMM6: case X86::YMM14: case X86::MM6:
254 case X86::XMM7: case X86::XMM15:
255 case X86::YMM7: case X86::YMM15: case X86::MM7:
258 case X86::ES: return 0;
259 case X86::CS: return 1;
260 case X86::SS: return 2;
261 case X86::DS: return 3;
262 case X86::FS: return 4;
263 case X86::GS: return 5;
265 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
266 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
267 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
268 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
269 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
270 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
271 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
272 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
274 // Pseudo index registers are equivalent to a "none"
275 // scaled index (See Intel Manual 2A, table 2-3)
281 assert((int(RegNo) > 0) && "Unknown physical register!");
286 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
287 // FIXME: TableGen these.
288 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
289 int SEH = X86_MC::getX86RegNum(Reg);
291 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
292 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
293 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
294 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
295 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
296 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
297 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
298 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
299 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
300 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
301 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
302 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
306 MRI->mapLLVMRegToSEHReg(Reg, SEH);
310 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
312 std::string ArchFS = X86_MC::ParseX86Triple(TT);
315 ArchFS = ArchFS + "," + FS.str();
320 std::string CPUName = CPU;
321 if (CPUName.empty()) {
322 #if defined (__x86_64__) || defined(__i386__)
323 CPUName = sys::getHostCPUName();
329 MCSubtargetInfo *X = new MCSubtargetInfo();
330 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
334 static MCInstrInfo *createX86MCInstrInfo() {
335 MCInstrInfo *X = new MCInstrInfo();
336 InitX86MCInstrInfo(X);
340 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
341 Triple TheTriple(TT);
342 unsigned RA = (TheTriple.getArch() == Triple::x86_64)
343 ? X86::RIP // Should have dwarf #16.
344 : X86::EIP; // Should have dwarf #8.
346 MCRegisterInfo *X = new MCRegisterInfo();
347 InitX86MCRegisterInfo(X, RA,
348 X86_MC::getDwarfRegFlavour(TT, false),
349 X86_MC::getDwarfRegFlavour(TT, true));
350 X86_MC::InitLLVM2SEHRegisterMapping(X);
354 static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) {
355 Triple TheTriple(TT);
356 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
359 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
361 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
363 MAI = new X86MCAsmInfoDarwin(TheTriple);
364 } else if (TheTriple.getOS() == Triple::Win32) {
365 MAI = new X86MCAsmInfoMicrosoft(TheTriple);
366 } else if (TheTriple.getOS() == Triple::MinGW32 || TheTriple.getOS() == Triple::Cygwin) {
367 MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
369 MAI = new X86ELFMCAsmInfo(TheTriple);
372 // Initialize initial frame state.
373 // Calculate amount of bytes used for return address storing
374 int stackGrowth = is64Bit ? -8 : -4;
376 // Initial state of the frame pointer is esp+stackGrowth.
377 MachineLocation Dst(MachineLocation::VirtualFP);
378 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
379 MAI->addInitialFrameState(0, Dst, Src);
381 // Add return address to move list
382 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
383 MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP);
384 MAI->addInitialFrameState(0, CSDst, CSSrc);
389 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
391 CodeGenOpt::Level OL) {
392 MCCodeGenInfo *X = new MCCodeGenInfo();
395 bool is64Bit = T.getArch() == Triple::x86_64;
397 if (RM == Reloc::Default) {
398 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
399 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
400 // use static relocation model by default.
401 if (T.isOSDarwin()) {
405 RM = Reloc::DynamicNoPIC;
406 } else if (T.isOSWindows() && is64Bit)
412 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
413 // is defined as a model for code which may be used in static or dynamic
414 // executables but not necessarily a shared library. On X86-32 we just
415 // compile in -static mode, in x86-64 we use PIC.
416 if (RM == Reloc::DynamicNoPIC) {
419 else if (!T.isOSDarwin())
423 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
424 // the Mach-O file format doesn't support it.
425 if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
428 // For static codegen, if we're not already set, use Small codegen.
429 if (CM == CodeModel::Default)
430 CM = CodeModel::Small;
431 else if (CM == CodeModel::JITDefault)
432 // 64-bit JIT places everything in the same buffer except external funcs.
433 CM = is64Bit ? CodeModel::Large : CodeModel::Small;
435 X->InitMCCodeGenInfo(RM, CM, OL);
439 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
440 MCContext &Ctx, MCAsmBackend &MAB,
442 MCCodeEmitter *_Emitter,
445 Triple TheTriple(TT);
447 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
448 return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll);
450 if (TheTriple.isOSWindows())
451 return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll);
453 return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
456 static MCInstPrinter *createX86MCInstPrinter(const Target &T,
457 unsigned SyntaxVariant,
458 const MCAsmInfo &MAI,
459 const MCSubtargetInfo &STI) {
460 if (SyntaxVariant == 0)
461 return new X86ATTInstPrinter(MAI);
462 if (SyntaxVariant == 1)
463 return new X86IntelInstPrinter(MAI);
467 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
468 return new MCInstrAnalysis(Info);
471 // Force static initialization.
472 extern "C" void LLVMInitializeX86TargetMC() {
473 // Register the MC asm info.
474 RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
475 RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
477 // Register the MC codegen info.
478 RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo);
479 RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo);
481 // Register the MC instruction info.
482 TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
483 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
485 // Register the MC register info.
486 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
487 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
489 // Register the MC subtarget info.
490 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
491 X86_MC::createX86MCSubtargetInfo);
492 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
493 X86_MC::createX86MCSubtargetInfo);
495 // Register the MC instruction analyzer.
496 TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target,
497 createX86MCInstrAnalysis);
498 TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target,
499 createX86MCInstrAnalysis);
501 // Register the code emitter.
502 TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target,
503 createX86MCCodeEmitter);
504 TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target,
505 createX86MCCodeEmitter);
507 // Register the asm backend.
508 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
509 createX86_32AsmBackend);
510 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
511 createX86_64AsmBackend);
513 // Register the object streamer.
514 TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target,
516 TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target,
519 // Register the MCInstPrinter.
520 TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,
521 createX86MCInstPrinter);
522 TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,
523 createX86MCInstPrinter);