1 //===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
15 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
17 #include "llvm/Support/DataTypes.h"
27 class MCSubtargetInfo;
28 class MCRelocationInfo;
34 class raw_pwrite_stream;
36 extern Target TheX86_32Target, TheX86_64Target;
38 /// Flavour of dwarf regnumbers
40 namespace DWARFFlavour {
42 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
46 /// Native X86 register numbers
50 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
55 std::string ParseX86Triple(const Triple &TT);
57 unsigned getDwarfRegFlavour(const Triple &TT, bool isEH);
59 void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
61 /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc.
62 /// do not need to go through TargetRegistry.
63 MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
67 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
68 const MCRegisterInfo &MRI,
71 MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
72 const Triple &TT, StringRef CPU);
73 MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
74 const Triple &TT, StringRef CPU);
76 /// Construct an X86 Windows COFF machine code streamer which will generate
77 /// PE/COFF format object files.
79 /// Takes ownership of \p AB and \p CE.
80 MCStreamer *createX86WinCOFFStreamer(MCContext &C, MCAsmBackend &AB,
81 raw_pwrite_stream &OS, MCCodeEmitter *CE,
84 /// Construct an X86 Mach-O object writer.
85 MCObjectWriter *createX86MachObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
89 /// Construct an X86 ELF object writer.
90 MCObjectWriter *createX86ELFObjectWriter(raw_pwrite_stream &OS, bool IsELF64,
91 uint8_t OSABI, uint16_t EMachine);
92 /// Construct an X86 Win COFF object writer.
93 MCObjectWriter *createX86WinCOFFObjectWriter(raw_pwrite_stream &OS,
96 /// Construct X86-64 Mach-O relocation info.
97 MCRelocationInfo *createX86_64MachORelocationInfo(MCContext &Ctx);
99 /// Construct X86-64 ELF relocation info.
100 MCRelocationInfo *createX86_64ELFRelocationInfo(MCContext &Ctx);
101 } // End llvm namespace
104 // Defines symbolic names for X86 registers. This defines a mapping from
105 // register name to register number.
107 #define GET_REGINFO_ENUM
108 #include "X86GenRegisterInfo.inc"
110 // Defines symbolic names for the X86 instructions.
112 #define GET_INSTRINFO_ENUM
113 #include "X86GenInstrInfo.inc"
115 #define GET_SUBTARGETINFO_ENUM
116 #include "X86GenSubtargetInfo.inc"