1 //===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86MCTARGETDESC_H
15 #define X86MCTARGETDESC_H
17 #include "llvm/Support/DataTypes.h"
27 class MCSubtargetInfo;
28 class MCRelocationInfo;
35 extern Target TheX86_32Target, TheX86_64Target;
37 /// DWARFFlavour - Flavour of dwarf regnumbers
39 namespace DWARFFlavour {
41 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
45 /// N86 namespace - Native X86 register numbers
49 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
54 std::string ParseX86Triple(StringRef TT);
56 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in
57 /// the specified arguments. If we can't run cpuid on the host, return true.
58 bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
59 unsigned *rEBX, unsigned *rECX, unsigned *rEDX);
60 /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
61 /// the 4 values in the specified arguments. If we can't run cpuid on the
62 /// host, return true.
63 bool GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX,
64 unsigned *rEBX, unsigned *rECX, unsigned *rEDX);
66 void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model);
68 unsigned getDwarfRegFlavour(Triple TT, bool isEH);
70 void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
72 /// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance.
73 /// This is exposed so Asm parser, etc. do not need to go through
75 MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
79 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
80 const MCRegisterInfo &MRI,
81 const MCSubtargetInfo &STI,
84 MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
85 StringRef TT, StringRef CPU);
86 MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
87 StringRef TT, StringRef CPU);
89 /// createX86WinCOFFStreamer - Construct an X86 Windows COFF machine code
90 /// streamer which will generate PE/COFF format object files.
92 /// Takes ownership of \p AB and \p CE.
93 MCStreamer *createX86WinCOFFStreamer(MCContext &C, MCAsmBackend &AB,
94 MCCodeEmitter *CE, raw_ostream &OS,
97 /// createX86MachObjectWriter - Construct an X86 Mach-O object writer.
98 MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS,
101 uint32_t CPUSubtype);
103 /// createX86ELFObjectWriter - Construct an X86 ELF object writer.
104 MCObjectWriter *createX86ELFObjectWriter(raw_ostream &OS,
108 /// createX86WinCOFFObjectWriter - Construct an X86 Win COFF object writer.
109 MCObjectWriter *createX86WinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit);
111 /// createX86_64MachORelocationInfo - Construct X86-64 Mach-O relocation info.
112 MCRelocationInfo *createX86_64MachORelocationInfo(MCContext &Ctx);
114 /// createX86_64ELFORelocationInfo - Construct X86-64 ELF relocation info.
115 MCRelocationInfo *createX86_64ELFRelocationInfo(MCContext &Ctx);
116 } // End llvm namespace
119 // Defines symbolic names for X86 registers. This defines a mapping from
120 // register name to register number.
122 #define GET_REGINFO_ENUM
123 #include "X86GenRegisterInfo.inc"
125 // Defines symbolic names for the X86 instructions.
127 #define GET_INSTRINFO_ENUM
128 #include "X86GenInstrInfo.inc"
130 #define GET_SUBTARGETINFO_ENUM
131 #include "X86GenSubtargetInfo.inc"