1 //===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86MCTARGETDESC_H
15 #define X86MCTARGETDESC_H
17 #include "llvm/Support/DataTypes.h"
27 class MCSubtargetInfo;
32 extern Target TheX86_32Target, TheX86_64Target;
34 /// DWARFFlavour - Flavour of dwarf regnumbers
36 namespace DWARFFlavour {
38 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
42 /// N86 namespace - Native X86 register numbers
46 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
51 std::string ParseX86Triple(StringRef TT);
53 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in
54 /// the specified arguments. If we can't run cpuid on the host, return true.
55 bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
56 unsigned *rEBX, unsigned *rECX, unsigned *rEDX);
58 void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model);
60 unsigned getDwarfRegFlavour(StringRef TT, bool isEH);
62 unsigned getX86RegNum(unsigned RegNo);
64 void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
66 /// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance.
67 /// This is exposed so Asm parser, etc. do not need to go through
69 MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
73 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
74 const MCSubtargetInfo &STI,
77 MCAsmBackend *createX86_32AsmBackend(const Target &T, StringRef TT);
78 MCAsmBackend *createX86_64AsmBackend(const Target &T, StringRef TT);
80 /// createX86MachObjectWriter - Construct an X86 Mach-O object writer.
81 MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS,
86 } // End llvm namespace
89 // Defines symbolic names for X86 registers. This defines a mapping from
90 // register name to register number.
92 #define GET_REGINFO_ENUM
93 #include "X86GenRegisterInfo.inc"
95 // Defines symbolic names for the X86 instructions.
97 #define GET_INSTRINFO_ENUM
98 #include "X86GenInstrInfo.inc"
100 #define GET_SUBTARGETINFO_ENUM
101 #include "X86GenSubtargetInfo.inc"