1 //===-- PeepholeOptimizer.cpp - X86 Peephole Optimizer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a peephole optimizer for the X86.
12 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/MachineFunctionPass.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "Support/Statistic.h"
21 Statistic<> NumPHOpts("x86-peephole",
22 "Number of peephole optimization performed");
23 struct PH : public MachineFunctionPass {
24 virtual bool runOnMachineFunction(MachineFunction &MF);
26 bool PeepholeOptimize(MachineBasicBlock &MBB,
27 MachineBasicBlock::iterator &I);
29 virtual const char *getPassName() const { return "X86 Peephole Optimizer"; }
33 FunctionPass *llvm::createX86PeepholeOptimizerPass() { return new PH(); }
35 bool PH::runOnMachineFunction(MachineFunction &MF) {
38 for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
39 for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
40 if (PeepholeOptimize(*BI, I)) {
50 bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator &I) {
52 MachineInstr *MI = *I;
53 MachineInstr *Next = (I+1 != MBB.end()) ? *(I+1) : 0;
55 switch (MI->getOpcode()) {
58 case X86::MOVrr32: // Destroy X = X copies...
59 if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
66 // A large number of X86 instructions have forms which take an 8-bit
67 // immediate despite the fact that the operands are 16 or 32 bits. Because
68 // this can save three bytes of code size (and icache space), we want to
69 // shrink them if possible.
70 case X86::ADDri16: case X86::ADDri32:
71 case X86::SUBri16: case X86::SUBri32:
72 case X86::IMULri16: case X86::IMULri32:
73 case X86::ANDri16: case X86::ANDri32:
74 case X86::ORri16: case X86::ORri32:
75 case X86::XORri16: case X86::XORri32:
76 assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
77 if (MI->getOperand(2).isImmediate()) {
78 int Val = MI->getOperand(2).getImmedValue();
79 // If the value is the same when signed extended from 8 bits...
80 if (Val == (signed int)(signed char)Val) {
82 switch (MI->getOpcode()) {
83 default: assert(0 && "Unknown opcode value!");
84 case X86::ADDri16: Opcode = X86::ADDri16b; break;
85 case X86::ADDri32: Opcode = X86::ADDri32b; break;
86 case X86::SUBri16: Opcode = X86::SUBri16b; break;
87 case X86::SUBri32: Opcode = X86::SUBri32b; break;
88 case X86::IMULri16: Opcode = X86::IMULri16b; break;
89 case X86::IMULri32: Opcode = X86::IMULri32b; break;
90 case X86::ANDri16: Opcode = X86::ANDri16b; break;
91 case X86::ANDri32: Opcode = X86::ANDri32b; break;
92 case X86::ORri16: Opcode = X86::ORri16b; break;
93 case X86::ORri32: Opcode = X86::ORri32b; break;
94 case X86::XORri16: Opcode = X86::XORri16b; break;
95 case X86::XORri32: Opcode = X86::XORri32b; break;
97 unsigned R0 = MI->getOperand(0).getReg();
98 unsigned R1 = MI->getOperand(1).getReg();
99 *I = BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val);
107 case X86::MOVir32: Size++;
108 case X86::MOVir16: Size++;
110 // FIXME: We can only do this transformation if we know that flags are not
111 // used here, because XOR clobbers the flags!
112 if (MI->getOperand(1).isImmediate()) { // avoid mov EAX, <value>
113 int Val = MI->getOperand(1).getImmedValue();
114 if (Val == 0) { // mov EAX, 0 -> xor EAX, EAX
115 static const unsigned Opcode[] ={X86::XORrr8,X86::XORrr16,X86::XORrr32};
116 unsigned Reg = MI->getOperand(0).getReg();
117 *I = BuildMI(Opcode[Size], 2, Reg).addReg(Reg).addReg(Reg);
120 } else if (Val == -1) { // mov EAX, -1 -> or EAX, -1
121 // TODO: 'or Reg, -1' has a smaller encoding than 'mov Reg, -1'
126 case X86::BSWAPr32: // Change bswap EAX, bswap EAX into nothing
127 if (Next->getOpcode() == X86::BSWAPr32 &&
128 MI->getOperand(0).getReg() == Next->getOperand(0).getReg()) {
129 I = MBB.erase(MBB.erase(I));
141 class UseDefChains : public MachineFunctionPass {
142 std::vector<MachineInstr*> DefiningInst;
144 // getDefinition - Return the machine instruction that defines the specified
145 // SSA virtual register.
146 MachineInstr *getDefinition(unsigned Reg) {
147 assert(Reg >= MRegisterInfo::FirstVirtualRegister &&
148 "use-def chains only exist for SSA registers!");
149 assert(Reg - MRegisterInfo::FirstVirtualRegister < DefiningInst.size() &&
150 "Unknown register number!");
151 assert(DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] &&
152 "Unknown register number!");
153 return DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister];
156 // setDefinition - Update the use-def chains to indicate that MI defines
158 void setDefinition(unsigned Reg, MachineInstr *MI) {
159 if (Reg-MRegisterInfo::FirstVirtualRegister >= DefiningInst.size())
160 DefiningInst.resize(Reg-MRegisterInfo::FirstVirtualRegister+1);
161 DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] = MI;
164 // removeDefinition - Update the use-def chains to forget about Reg
166 void removeDefinition(unsigned Reg) {
167 assert(getDefinition(Reg)); // Check validity
168 DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] = 0;
171 virtual bool runOnMachineFunction(MachineFunction &MF) {
172 for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI!=E; ++BI)
173 for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); ++I) {
174 MachineInstr *MI = *I;
175 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
176 MachineOperand &MO = MI->getOperand(i);
177 if (MO.isVirtualRegister() && MO.isDef() && !MO.isUse())
178 setDefinition(MO.getReg(), MI);
184 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
185 AU.setPreservesAll();
186 MachineFunctionPass::getAnalysisUsage(AU);
189 virtual void releaseMemory() {
190 std::vector<MachineInstr*>().swap(DefiningInst);
194 RegisterAnalysis<UseDefChains> X("use-def-chains",
195 "use-def chain construction for machine code");
200 Statistic<> NumSSAPHOpts("x86-ssa-peephole",
201 "Number of SSA peephole optimization performed");
203 /// SSAPH - This pass is an X86-specific, SSA-based, peephole optimizer. This
204 /// pass is really a bad idea: a better instruction selector should completely
205 /// supersume it. However, that will take some time to develop, and the
206 /// simple things this can do are important now.
207 class SSAPH : public MachineFunctionPass {
210 virtual bool runOnMachineFunction(MachineFunction &MF);
212 bool PeepholeOptimize(MachineBasicBlock &MBB,
213 MachineBasicBlock::iterator &I);
215 virtual const char *getPassName() const {
216 return "X86 SSA-based Peephole Optimizer";
219 /// Propagate - Set MI[DestOpNo] = Src[SrcOpNo], optionally change the
220 /// opcode of the instruction, then return true.
221 bool Propagate(MachineInstr *MI, unsigned DestOpNo,
222 MachineInstr *Src, unsigned SrcOpNo, unsigned NewOpcode = 0){
223 MI->getOperand(DestOpNo) = Src->getOperand(SrcOpNo);
224 if (NewOpcode) MI->setOpcode(NewOpcode);
228 /// OptimizeAddress - If we can fold the addressing arithmetic for this
229 /// memory instruction into the instruction itself, do so and return true.
230 bool OptimizeAddress(MachineInstr *MI, unsigned OpNo);
232 /// getDefininingInst - If the specified operand is a read of an SSA
233 /// register, return the machine instruction defining it, otherwise, return
235 MachineInstr *getDefiningInst(MachineOperand &MO) {
236 if (MO.isDef() || !MO.isVirtualRegister()) return 0;
237 return UDC->getDefinition(MO.getReg());
240 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
241 AU.addRequired<UseDefChains>();
242 AU.addPreserved<UseDefChains>();
243 MachineFunctionPass::getAnalysisUsage(AU);
248 FunctionPass *llvm::createX86SSAPeepholeOptimizerPass() { return new SSAPH(); }
250 bool SSAPH::runOnMachineFunction(MachineFunction &MF) {
251 bool Changed = false;
254 UDC = &getAnalysis<UseDefChains>();
257 LocalChanged = false;
259 for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
260 for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
261 if (PeepholeOptimize(*BI, I)) {
266 Changed |= LocalChanged;
267 } while (LocalChanged);
272 static bool isValidScaleAmount(unsigned Scale) {
273 return Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8;
276 /// OptimizeAddress - If we can fold the addressing arithmetic for this
277 /// memory instruction into the instruction itself, do so and return true.
278 bool SSAPH::OptimizeAddress(MachineInstr *MI, unsigned OpNo) {
279 MachineOperand &BaseRegOp = MI->getOperand(OpNo+0);
280 MachineOperand &ScaleOp = MI->getOperand(OpNo+1);
281 MachineOperand &IndexRegOp = MI->getOperand(OpNo+2);
282 MachineOperand &DisplacementOp = MI->getOperand(OpNo+3);
284 unsigned BaseReg = BaseRegOp.hasAllocatedReg() ? BaseRegOp.getReg() : 0;
285 unsigned Scale = ScaleOp.getImmedValue();
286 unsigned IndexReg = IndexRegOp.hasAllocatedReg() ? IndexRegOp.getReg() : 0;
288 bool Changed = false;
290 // If the base register is unset, and the index register is set with a scale
291 // of 1, move it to be the base register.
292 if (BaseRegOp.hasAllocatedReg() && BaseReg == 0 &&
293 Scale == 1 && IndexReg != 0) {
294 BaseRegOp.setReg(IndexReg);
295 IndexRegOp.setReg(0);
299 // Attempt to fold instructions used by the base register into the instruction
300 if (MachineInstr *DefInst = getDefiningInst(BaseRegOp)) {
301 switch (DefInst->getOpcode()) {
303 // If there is no displacement set for this instruction set one now.
304 // FIXME: If we can fold two immediates together, we should do so!
305 if (DisplacementOp.isImmediate() && !DisplacementOp.getImmedValue()) {
306 if (DefInst->getOperand(1).isImmediate()) {
308 return Propagate(MI, OpNo+3, DefInst, 1);
314 // If the source is a register-register add, and we do not yet have an
315 // index register, fold the add into the memory address.
317 BaseRegOp = DefInst->getOperand(1);
318 IndexRegOp = DefInst->getOperand(2);
319 ScaleOp.setImmedValue(1);
325 // If this shift could be folded into the index portion of the address if
326 // it were the index register, move it to the index register operand now,
327 // so it will be folded in below.
328 if ((Scale == 1 || (IndexReg == 0 && IndexRegOp.hasAllocatedReg())) &&
329 DefInst->getOperand(2).getImmedValue() < 4) {
330 std::swap(BaseRegOp, IndexRegOp);
331 ScaleOp.setImmedValue(1); Scale = 1;
332 std::swap(IndexReg, BaseReg);
339 // Attempt to fold instructions used by the index into the instruction
340 if (MachineInstr *DefInst = getDefiningInst(IndexRegOp)) {
341 switch (DefInst->getOpcode()) {
343 // Figure out what the resulting scale would be if we folded this shift.
344 unsigned ResScale = Scale * (1 << DefInst->getOperand(2).getImmedValue());
345 if (isValidScaleAmount(ResScale)) {
346 IndexRegOp = DefInst->getOperand(1);
347 ScaleOp.setImmedValue(ResScale);
358 bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
359 MachineBasicBlock::iterator &I) {
360 MachineInstr *MI = *I;
361 MachineInstr *Next = (I+1 != MBB.end()) ? *(I+1) : 0;
363 bool Changed = false;
365 // Scan the operands of this instruction. If any operands are
366 // register-register copies, replace the operand with the source.
367 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
368 // Is this an SSA register use?
369 if (MachineInstr *DefInst = getDefiningInst(MI->getOperand(i)))
370 // If the operand is a vreg-vreg copy, it is always safe to replace the
371 // source value with the input operand.
372 if (DefInst->getOpcode() == X86::MOVrr8 ||
373 DefInst->getOpcode() == X86::MOVrr16 ||
374 DefInst->getOpcode() == X86::MOVrr32) {
375 // Don't propagate physical registers into PHI nodes...
376 if (MI->getOpcode() != X86::PHI ||
377 DefInst->getOperand(1).isVirtualRegister())
378 Changed = Propagate(MI, i, DefInst, 1);
382 // Perform instruction specific optimizations.
383 switch (MI->getOpcode()) {
385 // Register to memory stores. Format: <base,scale,indexreg,immdisp>, srcreg
386 case X86::MOVrm32: case X86::MOVrm16: case X86::MOVrm8:
387 case X86::MOVim32: case X86::MOVim16: case X86::MOVim8:
388 // Check to see if we can fold the source instruction into this one...
389 if (MachineInstr *SrcInst = getDefiningInst(MI->getOperand(4))) {
390 switch (SrcInst->getOpcode()) {
391 // Fold the immediate value into the store, if possible.
392 case X86::MOVir8: return Propagate(MI, 4, SrcInst, 1, X86::MOVim8);
393 case X86::MOVir16: return Propagate(MI, 4, SrcInst, 1, X86::MOVim16);
394 case X86::MOVir32: return Propagate(MI, 4, SrcInst, 1, X86::MOVim32);
399 // If we can optimize the addressing expression, do so now.
400 if (OptimizeAddress(MI, 0))
407 // If we can optimize the addressing expression, do so now.
408 if (OptimizeAddress(MI, 1))