1 //===-- PeepholeOptimizer.cpp - X86 Peephole Optimizer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a peephole optimizer for the X86.
12 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/MachineFunctionPass.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 struct PH : public MachineFunctionPass {
21 virtual bool runOnMachineFunction(MachineFunction &MF);
23 bool PeepholeOptimize(MachineBasicBlock &MBB,
24 MachineBasicBlock::iterator &I);
26 virtual const char *getPassName() const { return "X86 Peephole Optimizer"; }
30 FunctionPass *llvm::createX86PeepholeOptimizerPass() { return new PH(); }
32 bool PH::runOnMachineFunction(MachineFunction &MF) {
35 for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
36 for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
37 if (PeepholeOptimize(*BI, I))
46 bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator &I) {
48 MachineInstr *MI = *I;
49 MachineInstr *Next = (I+1 != MBB.end()) ? *(I+1) : 0;
51 switch (MI->getOpcode()) {
54 case X86::MOVrr32: // Destroy X = X copies...
55 if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
62 // A large number of X86 instructions have forms which take an 8-bit
63 // immediate despite the fact that the operands are 16 or 32 bits. Because
64 // this can save three bytes of code size (and icache space), we want to
65 // shrink them if possible.
66 case X86::ADDri16: case X86::ADDri32:
67 case X86::SUBri16: case X86::SUBri32:
68 case X86::IMULri16: case X86::IMULri32:
69 case X86::ANDri16: case X86::ANDri32:
70 case X86::ORri16: case X86::ORri32:
71 case X86::XORri16: case X86::XORri32:
72 assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
73 if (MI->getOperand(2).isImmediate()) {
74 int Val = MI->getOperand(2).getImmedValue();
75 // If the value is the same when signed extended from 8 bits...
76 if (Val == (signed int)(signed char)Val) {
78 switch (MI->getOpcode()) {
79 default: assert(0 && "Unknown opcode value!");
80 case X86::ADDri16: Opcode = X86::ADDri16b; break;
81 case X86::ADDri32: Opcode = X86::ADDri32b; break;
82 case X86::SUBri16: Opcode = X86::SUBri16b; break;
83 case X86::SUBri32: Opcode = X86::SUBri32b; break;
84 case X86::IMULri16: Opcode = X86::IMULri16b; break;
85 case X86::IMULri32: Opcode = X86::IMULri32b; break;
86 case X86::ANDri16: Opcode = X86::ANDri16b; break;
87 case X86::ANDri32: Opcode = X86::ANDri32b; break;
88 case X86::ORri16: Opcode = X86::ORri16b; break;
89 case X86::ORri32: Opcode = X86::ORri32b; break;
90 case X86::XORri16: Opcode = X86::XORri16b; break;
91 case X86::XORri32: Opcode = X86::XORri32b; break;
93 unsigned R0 = MI->getOperand(0).getReg();
94 unsigned R1 = MI->getOperand(1).getReg();
95 *I = BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val);
103 case X86::MOVir32: Size++;
104 case X86::MOVir16: Size++;
106 // FIXME: We can only do this transformation if we know that flags are not
107 // used here, because XOR clobbers the flags!
108 if (MI->getOperand(1).isImmediate()) { // avoid mov EAX, <value>
109 int Val = MI->getOperand(1).getImmedValue();
110 if (Val == 0) { // mov EAX, 0 -> xor EAX, EAX
111 static const unsigned Opcode[] ={X86::XORrr8,X86::XORrr16,X86::XORrr32};
112 unsigned Reg = MI->getOperand(0).getReg();
113 *I = BuildMI(Opcode[Size], 2, Reg).addReg(Reg).addReg(Reg);
116 } else if (Val == -1) { // mov EAX, -1 -> or EAX, -1
117 // TODO: 'or Reg, -1' has a smaller encoding than 'mov Reg, -1'
122 case X86::BSWAPr32: // Change bswap EAX, bswap EAX into nothing
123 if (Next->getOpcode() == X86::BSWAPr32 &&
124 MI->getOperand(0).getReg() == Next->getOperand(0).getReg()) {
125 I = MBB.erase(MBB.erase(I));