1 //===-- X86/Printer.cpp - Convert X86 LLVM code to Intel assembly ---------===//
3 // This file contains a printer that converts from our internal
4 // representation of machine-dependent LLVM code to Intel-format
5 // assembly language. This printer is the output mechanism used
6 // by `llc' and `lli -print-machineinstrs' on X86.
8 //===----------------------------------------------------------------------===//
11 #include "X86InstrInfo.h"
12 #include "llvm/Constants.h"
13 #include "llvm/DerivedTypes.h"
14 #include "llvm/Module.h"
15 #include "llvm/Assembly/Writer.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Support/Mangler.h"
21 #include "Support/StringExtras.h"
22 #include "Support/CommandLine.h"
25 // FIXME: This should be automatically picked up by autoconf from the C
27 cl::opt<bool> EmitCygwin("enable-cygwin-compatible-output", cl::Hidden,
28 cl::desc("Emit X86 assembly code suitable for consumption by cygwin"));
30 struct Printer : public MachineFunctionPass {
31 /// Output stream on which we're printing assembly code.
35 /// Target machine description which we query for reg. names, data
40 /// Name-mangler for global names.
44 Printer(std::ostream &o, TargetMachine &tm) : O(o), TM(tm) { }
46 /// We name each basic block in a Function with a unique number, so
47 /// that we can consistently refer to them later. This is cleared
48 /// at the beginning of each call to runOnMachineFunction().
50 typedef std::map<const Value *, unsigned> ValueMapTy;
51 ValueMapTy NumberForBB;
53 /// Cache of mangled name for current function. This is
54 /// recalculated at the beginning of each call to
55 /// runOnMachineFunction().
57 std::string CurrentFnName;
59 virtual const char *getPassName() const {
60 return "X86 Assembly Printer";
63 void checkImplUses (const TargetInstrDescriptor &Desc);
64 void printMachineInstruction(const MachineInstr *MI);
65 void printOp(const MachineOperand &MO,
66 bool elideOffsetKeyword = false);
67 void printMemReference(const MachineInstr *MI, unsigned Op);
68 void printConstantPool(MachineConstantPool *MCP);
69 bool runOnMachineFunction(MachineFunction &F);
70 std::string ConstantExprToString(const ConstantExpr* CE);
71 std::string valToExprString(const Value* V);
72 bool doInitialization(Module &M);
73 bool doFinalization(Module &M);
74 void printConstantValueOnly(const Constant* CV, int numPadBytesAfter = 0);
75 void printSingleConstantValue(const Constant* CV);
77 } // end of anonymous namespace
79 /// createX86CodePrinterPass - Returns a pass that prints the X86
80 /// assembly code for a MachineFunction to the given output stream,
81 /// using the given target machine description. This should work
82 /// regardless of whether the function is in SSA form.
84 FunctionPass *createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){
85 return new Printer(o, tm);
88 /// valToExprString - Helper function for ConstantExprToString().
89 /// Appends result to argument string S.
91 std::string Printer::valToExprString(const Value* V) {
94 if (const Constant* CV = dyn_cast<Constant>(V)) { // symbolic or known
95 if (const ConstantBool *CB = dyn_cast<ConstantBool>(CV))
96 S += std::string(CB == ConstantBool::True ? "1" : "0");
97 else if (const ConstantSInt *CI = dyn_cast<ConstantSInt>(CV))
98 S += itostr(CI->getValue());
99 else if (const ConstantUInt *CI = dyn_cast<ConstantUInt>(CV))
100 S += utostr(CI->getValue());
101 else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV))
102 S += ftostr(CFP->getValue());
103 else if (isa<ConstantPointerNull>(CV))
105 else if (const ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(CV))
106 S += valToExprString(CPR->getValue());
107 else if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV))
108 S += ConstantExprToString(CE);
111 } else if (const GlobalValue* GV = dyn_cast<GlobalValue>(V)) {
112 S += Mang->getValueName(GV);
118 assert(0 && "Cannot convert value to string");
119 S += "<illegal-value>";
124 /// ConstantExprToString - Convert a ConstantExpr to an asm expression
125 /// and return this as a string.
127 std::string Printer::ConstantExprToString(const ConstantExpr* CE) {
128 const TargetData &TD = TM.getTargetData();
129 switch(CE->getOpcode()) {
130 case Instruction::GetElementPtr:
131 { // generate a symbolic expression for the byte address
132 const Value* ptrVal = CE->getOperand(0);
133 std::vector<Value*> idxVec(CE->op_begin()+1, CE->op_end());
134 if (unsigned Offset = TD.getIndexedOffset(ptrVal->getType(), idxVec))
135 return "(" + valToExprString(ptrVal) + ") + " + utostr(Offset);
137 return valToExprString(ptrVal);
140 case Instruction::Cast:
141 // Support only non-converting or widening casts for now, that is,
142 // ones that do not involve a change in value. This assertion is
143 // not a complete check.
145 Constant *Op = CE->getOperand(0);
146 const Type *OpTy = Op->getType(), *Ty = CE->getType();
147 assert(((isa<PointerType>(OpTy)
148 && (Ty == Type::LongTy || Ty == Type::ULongTy))
149 || (isa<PointerType>(Ty)
150 && (OpTy == Type::LongTy || OpTy == Type::ULongTy)))
151 || (((TD.getTypeSize(Ty) >= TD.getTypeSize(OpTy))
152 && (OpTy->isLosslesslyConvertibleTo(Ty))))
153 && "FIXME: Don't yet support this kind of constant cast expr");
154 return "(" + valToExprString(Op) + ")";
157 case Instruction::Add:
158 return "(" + valToExprString(CE->getOperand(0)) + ") + ("
159 + valToExprString(CE->getOperand(1)) + ")";
162 assert(0 && "Unsupported operator in ConstantExprToString()");
167 /// printSingleConstantValue - Print a single constant value.
170 Printer::printSingleConstantValue(const Constant* CV)
172 assert(CV->getType() != Type::VoidTy &&
173 CV->getType() != Type::TypeTy &&
174 CV->getType() != Type::LabelTy &&
175 "Unexpected type for Constant");
177 assert((!isa<ConstantArray>(CV) && ! isa<ConstantStruct>(CV))
178 && "Aggregate types should be handled outside this function");
180 const Type *type = CV->getType();
182 switch(type->getPrimitiveID())
184 case Type::BoolTyID: case Type::UByteTyID: case Type::SByteTyID:
187 case Type::UShortTyID: case Type::ShortTyID:
190 case Type::UIntTyID: case Type::IntTyID: case Type::PointerTyID:
193 case Type::ULongTyID: case Type::LongTyID:
196 case Type::FloatTyID:
199 case Type::DoubleTyID:
202 case Type::ArrayTyID:
203 if ((cast<ArrayType>(type)->getElementType() == Type::UByteTy) ||
204 (cast<ArrayType>(type)->getElementType() == Type::SByteTy))
207 assert (0 && "Can't handle printing this type of array");
210 assert (0 && "Can't handle printing this type of thing");
215 if (const ConstantExpr* CE = dyn_cast<ConstantExpr>(CV))
217 // Constant expression built from operators, constants, and
219 O << ConstantExprToString(CE) << "\n";
221 else if (type->isPrimitiveType())
223 if (type->isFloatingPoint()) {
224 // FP Constants are printed as integer constants to avoid losing
226 double Val = cast<ConstantFP>(CV)->getValue();
227 if (type == Type::FloatTy) {
228 float FVal = (float)Val;
229 char *ProxyPtr = (char*)&FVal; // Abide by C TBAA rules
230 O << *(unsigned int*)ProxyPtr;
231 } else if (type == Type::DoubleTy) {
232 char *ProxyPtr = (char*)&Val; // Abide by C TBAA rules
233 O << *(uint64_t*)ProxyPtr;
235 assert(0 && "Unknown floating point type!");
238 O << "\t# " << type->getDescription() << " value: " << Val << "\n";
240 WriteAsOperand(O, CV, false, false) << "\n";
243 else if (const ConstantPointerRef* CPR = dyn_cast<ConstantPointerRef>(CV))
245 // This is a constant address for a global variable or method.
246 // Use the name of the variable or method as the address value.
247 O << Mang->getValueName(CPR->getValue()) << "\n";
249 else if (isa<ConstantPointerNull>(CV))
251 // Null pointer value
256 assert(0 && "Unknown elementary type for constant");
260 /// isStringCompatible - Can we treat the specified array as a string?
261 /// Only if it is an array of ubytes or non-negative sbytes.
263 static bool isStringCompatible(const ConstantArray *CVA) {
264 const Type *ETy = cast<ArrayType>(CVA->getType())->getElementType();
265 if (ETy == Type::UByteTy) return true;
266 if (ETy != Type::SByteTy) return false;
268 for (unsigned i = 0; i < CVA->getNumOperands(); ++i)
269 if (cast<ConstantSInt>(CVA->getOperand(i))->getValue() < 0)
275 /// toOctal - Convert the low order bits of X into an octal digit.
277 static inline char toOctal(int X) {
281 /// getAsCString - Return the specified array as a C compatible
282 /// string, only if the predicate isStringCompatible is true.
284 static std::string getAsCString(const ConstantArray *CVA) {
285 assert(isStringCompatible(CVA) && "Array is not string compatible!");
288 const Type *ETy = cast<ArrayType>(CVA->getType())->getElementType();
290 for (unsigned i = 0; i < CVA->getNumOperands(); ++i) {
291 unsigned char C = cast<ConstantInt>(CVA->getOperand(i))->getRawValue();
295 } else if (C == '\\') {
297 } else if (isprint(C)) {
301 case '\b': Result += "\\b"; break;
302 case '\f': Result += "\\f"; break;
303 case '\n': Result += "\\n"; break;
304 case '\r': Result += "\\r"; break;
305 case '\t': Result += "\\t"; break;
308 Result += toOctal(C >> 6);
309 Result += toOctal(C >> 3);
310 Result += toOctal(C >> 0);
319 // Print a constant value or values (it may be an aggregate).
320 // Uses printSingleConstantValue() to print each individual value.
322 Printer::printConstantValueOnly(const Constant* CV,
323 int numPadBytesAfter /* = 0 */)
325 const ConstantArray *CVA = dyn_cast<ConstantArray>(CV);
326 const TargetData &TD = TM.getTargetData();
328 if (CVA && isStringCompatible(CVA))
329 { // print the string alone and return
330 O << "\t.string\t" << getAsCString(CVA) << "\n";
333 { // Not a string. Print the values in successive locations
334 const std::vector<Use> &constValues = CVA->getValues();
335 for (unsigned i=0; i < constValues.size(); i++)
336 printConstantValueOnly(cast<Constant>(constValues[i].get()));
338 else if (const ConstantStruct *CVS = dyn_cast<ConstantStruct>(CV))
339 { // Print the fields in successive locations. Pad to align if needed!
340 const StructLayout *cvsLayout =
341 TD.getStructLayout(CVS->getType());
342 const std::vector<Use>& constValues = CVS->getValues();
343 unsigned sizeSoFar = 0;
344 for (unsigned i=0, N = constValues.size(); i < N; i++)
346 const Constant* field = cast<Constant>(constValues[i].get());
348 // Check if padding is needed and insert one or more 0s.
349 unsigned fieldSize = TD.getTypeSize(field->getType());
350 int padSize = ((i == N-1? cvsLayout->StructSize
351 : cvsLayout->MemberOffsets[i+1])
352 - cvsLayout->MemberOffsets[i]) - fieldSize;
353 sizeSoFar += (fieldSize + padSize);
355 // Now print the actual field value
356 printConstantValueOnly(field, padSize);
358 assert(sizeSoFar == cvsLayout->StructSize &&
359 "Layout of constant struct may be incorrect!");
362 printSingleConstantValue(CV);
364 if (numPadBytesAfter) O << "\t.zero\t " << numPadBytesAfter << "\n";
367 /// printConstantPool - Print to the current output stream assembly
368 /// representations of the constants in the constant pool MCP. This is
369 /// used to print out constants which have been "spilled to memory" by
370 /// the code generator.
372 void Printer::printConstantPool(MachineConstantPool *MCP) {
373 const std::vector<Constant*> &CP = MCP->getConstants();
374 const TargetData &TD = TM.getTargetData();
376 if (CP.empty()) return;
378 for (unsigned i = 0, e = CP.size(); i != e; ++i) {
379 O << "\t.section .rodata\n";
380 O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType())
382 O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t#"
384 printConstantValueOnly (CP[i]);
388 /// runOnMachineFunction - This uses the printMachineInstruction()
389 /// method to print assembly for each instruction.
391 bool Printer::runOnMachineFunction(MachineFunction &MF) {
392 // BBNumber is used here so that a given Printer will never give two
393 // BBs the same name. (If you have a better way, please let me know!)
394 static unsigned BBNumber = 0;
397 // What's my mangled name?
398 CurrentFnName = Mang->getValueName(MF.getFunction());
400 // Print out constants referenced by the function
401 printConstantPool(MF.getConstantPool());
403 // Print out labels for the function.
405 O << "\t.align 16\n";
406 O << "\t.globl\t" << CurrentFnName << "\n";
408 O << "\t.type\t" << CurrentFnName << ", @function\n";
409 O << CurrentFnName << ":\n";
411 // Number each basic block so that we can consistently refer to them
412 // in PC-relative references.
414 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
416 NumberForBB[I->getBasicBlock()] = BBNumber++;
419 // Print out code for the function.
420 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
422 // Print a label for the basic block.
423 O << ".LBB" << NumberForBB[I->getBasicBlock()] << ":\t# "
424 << I->getBasicBlock()->getName() << "\n";
425 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
427 // Print the assembly for the instruction.
429 printMachineInstruction(*II);
433 // We didn't modify anything.
437 static bool isScale(const MachineOperand &MO) {
438 return MO.isImmediate() &&
439 (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
440 MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
443 static bool isMem(const MachineInstr *MI, unsigned Op) {
444 if (MI->getOperand(Op).isFrameIndex()) return true;
445 if (MI->getOperand(Op).isConstantPoolIndex()) return true;
446 return Op+4 <= MI->getNumOperands() &&
447 MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
448 MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
453 void Printer::printOp(const MachineOperand &MO,
454 bool elideOffsetKeyword /* = false */) {
455 const MRegisterInfo &RI = *TM.getRegisterInfo();
456 switch (MO.getType()) {
457 case MachineOperand::MO_VirtualRegister:
458 if (Value *V = MO.getVRegValueOrNull()) {
459 O << "<" << V->getName() << ">";
463 case MachineOperand::MO_MachineRegister:
464 if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
465 // Bug Workaround: See note in Printer::doInitialization about %.
466 O << "%" << RI.get(MO.getReg()).Name;
468 O << "%reg" << MO.getReg();
471 case MachineOperand::MO_SignExtendedImmed:
472 case MachineOperand::MO_UnextendedImmed:
473 O << (int)MO.getImmedValue();
475 case MachineOperand::MO_PCRelativeDisp:
477 ValueMapTy::const_iterator i = NumberForBB.find(MO.getVRegValue());
478 assert (i != NumberForBB.end()
479 && "Could not find a BB I previously put in the NumberForBB map!");
480 O << ".LBB" << i->second << " # PC rel: " << MO.getVRegValue()->getName();
483 case MachineOperand::MO_GlobalAddress:
484 if (!elideOffsetKeyword)
486 O << Mang->getValueName(MO.getGlobal());
488 case MachineOperand::MO_ExternalSymbol:
489 O << MO.getSymbolName();
492 O << "<unknown operand type>"; return;
496 static const std::string sizePtr(const TargetInstrDescriptor &Desc) {
497 switch (Desc.TSFlags & X86II::ArgMask) {
498 default: assert(0 && "Unknown arg size!");
499 case X86II::Arg8: return "BYTE PTR";
500 case X86II::Arg16: return "WORD PTR";
501 case X86II::Arg32: return "DWORD PTR";
502 case X86II::Arg64: return "QWORD PTR";
503 case X86II::ArgF32: return "DWORD PTR";
504 case X86II::ArgF64: return "QWORD PTR";
505 case X86II::ArgF80: return "XWORD PTR";
509 void Printer::printMemReference(const MachineInstr *MI, unsigned Op) {
510 assert(isMem(MI, Op) && "Invalid memory reference!");
512 if (MI->getOperand(Op).isFrameIndex()) {
513 O << "[frame slot #" << MI->getOperand(Op).getFrameIndex();
514 if (MI->getOperand(Op+3).getImmedValue())
515 O << " + " << MI->getOperand(Op+3).getImmedValue();
518 } else if (MI->getOperand(Op).isConstantPoolIndex()) {
519 O << "[.CPI" << CurrentFnName << "_"
520 << MI->getOperand(Op).getConstantPoolIndex();
521 if (MI->getOperand(Op+3).getImmedValue())
522 O << " + " << MI->getOperand(Op+3).getImmedValue();
527 const MachineOperand &BaseReg = MI->getOperand(Op);
528 int ScaleVal = MI->getOperand(Op+1).getImmedValue();
529 const MachineOperand &IndexReg = MI->getOperand(Op+2);
530 int DispVal = MI->getOperand(Op+3).getImmedValue();
533 bool NeedPlus = false;
534 if (BaseReg.getReg()) {
539 if (IndexReg.getReg()) {
540 if (NeedPlus) O << " + ";
542 O << ScaleVal << "*";
560 /// checkImplUses - Emit the implicit-use registers for the
561 /// instruction described by DESC, if its PrintImplUses flag is set.
563 void Printer::checkImplUses (const TargetInstrDescriptor &Desc) {
564 const MRegisterInfo &RI = *TM.getRegisterInfo();
565 if (Desc.TSFlags & X86II::PrintImplUses) {
566 for (const unsigned *p = Desc.ImplicitUses; *p; ++p) {
567 // Bug Workaround: See note in Printer::doInitialization about %.
568 O << ", %" << RI.get(*p).Name;
573 /// printMachineInstruction -- Print out a single X86 LLVM instruction
574 /// MI in Intel syntax to the current output stream.
576 void Printer::printMachineInstruction(const MachineInstr *MI) {
577 unsigned Opcode = MI->getOpcode();
578 const TargetInstrInfo &TII = TM.getInstrInfo();
579 const TargetInstrDescriptor &Desc = TII.get(Opcode);
581 switch (Desc.TSFlags & X86II::FormMask) {
583 // Print pseudo-instructions as comments; either they should have been
584 // turned into real instructions by now, or they don't need to be
585 // seen by the assembler (e.g., IMPLICIT_USEs.)
587 if (Opcode == X86::PHI) {
588 printOp(MI->getOperand(0));
590 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
591 if (i != 1) O << ", ";
593 printOp(MI->getOperand(i));
595 printOp(MI->getOperand(i+1));
600 if (MI->getNumOperands() && (MI->getOperand(0).opIsDefOnly() ||
601 MI->getOperand(0).opIsDefAndUse())) {
602 printOp(MI->getOperand(0));
606 O << TII.getName(MI->getOpcode());
608 for (unsigned e = MI->getNumOperands(); i != e; ++i) {
610 if (MI->getOperand(i).opIsDefOnly() ||
611 MI->getOperand(i).opIsDefAndUse()) O << "*";
612 printOp(MI->getOperand(i));
613 if (MI->getOperand(i).opIsDefOnly() ||
614 MI->getOperand(i).opIsDefAndUse()) O << "*";
621 // The accepted forms of Raw instructions are:
622 // 1. nop - No operand required
623 // 2. jmp foo - PC relative displacement operand
624 // 3. call bar - GlobalAddress Operand or External Symbol Operand
626 assert(MI->getNumOperands() == 0 ||
627 (MI->getNumOperands() == 1 &&
628 (MI->getOperand(0).isPCRelativeDisp() ||
629 MI->getOperand(0).isGlobalAddress() ||
630 MI->getOperand(0).isExternalSymbol())) &&
631 "Illegal raw instruction!");
632 O << TII.getName(MI->getOpcode()) << " ";
634 if (MI->getNumOperands() == 1) {
635 printOp(MI->getOperand(0), true); // Don't print "OFFSET"...
640 case X86II::AddRegFrm: {
641 // There are currently two forms of acceptable AddRegFrm instructions.
642 // Either the instruction JUST takes a single register (like inc, dec, etc),
643 // or it takes a register and an immediate of the same size as the register
644 // (move immediate f.e.). Note that this immediate value might be stored as
645 // an LLVM value, to represent, for example, loading the address of a global
646 // into a register. The initial register might be duplicated if this is a
647 // M_2_ADDR_REG instruction
649 assert(MI->getOperand(0).isRegister() &&
650 (MI->getNumOperands() == 1 ||
651 (MI->getNumOperands() == 2 &&
652 (MI->getOperand(1).getVRegValueOrNull() ||
653 MI->getOperand(1).isImmediate() ||
654 MI->getOperand(1).isRegister() ||
655 MI->getOperand(1).isGlobalAddress() ||
656 MI->getOperand(1).isExternalSymbol()))) &&
657 "Illegal form for AddRegFrm instruction!");
659 unsigned Reg = MI->getOperand(0).getReg();
661 O << TII.getName(MI->getOpCode()) << " ";
662 printOp(MI->getOperand(0));
663 if (MI->getNumOperands() == 2 &&
664 (!MI->getOperand(1).isRegister() ||
665 MI->getOperand(1).getVRegValueOrNull() ||
666 MI->getOperand(1).isGlobalAddress() ||
667 MI->getOperand(1).isExternalSymbol())) {
669 printOp(MI->getOperand(1));
675 case X86II::MRMDestReg: {
676 // There are two acceptable forms of MRMDestReg instructions, those with 2,
679 // 2 Operands: this is for things like mov that do not read a second input
681 // 3 Operands: in this form, the first two registers (the destination, and
682 // the first operand) should be the same, post register allocation. The 3rd
683 // operand is an additional input. This should be for things like add
686 // 4 Operands: This form is for instructions which are 3 operands forms, but
687 // have a constant argument as well.
689 bool isTwoAddr = TII.isTwoAddrInstr(Opcode);
690 assert(MI->getOperand(0).isRegister() &&
691 (MI->getNumOperands() == 2 ||
692 (isTwoAddr && MI->getOperand(1).isRegister() &&
693 MI->getOperand(0).getReg() == MI->getOperand(1).getReg() &&
694 (MI->getNumOperands() == 3 ||
695 (MI->getNumOperands() == 4 && MI->getOperand(3).isImmediate()))))
696 && "Bad format for MRMDestReg!");
698 O << TII.getName(MI->getOpCode()) << " ";
699 printOp(MI->getOperand(0));
701 printOp(MI->getOperand(1+isTwoAddr));
702 if (MI->getNumOperands() == 4) {
704 printOp(MI->getOperand(3));
710 case X86II::MRMDestMem: {
711 // These instructions are the same as MRMDestReg, but instead of having a
712 // register reference for the mod/rm field, it's a memory reference.
714 assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
715 MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
717 O << TII.getName(MI->getOpCode()) << " " << sizePtr(Desc) << " ";
718 printMemReference(MI, 0);
720 printOp(MI->getOperand(4));
725 case X86II::MRMSrcReg: {
726 // There is a two forms that are acceptable for MRMSrcReg instructions,
727 // those with 3 and 2 operands:
729 // 3 Operands: in this form, the last register (the second input) is the
730 // ModR/M input. The first two operands should be the same, post register
731 // allocation. This is for things like: add r32, r/m32
733 // 2 Operands: this is for things like mov that do not read a second input
735 assert(MI->getOperand(0).isRegister() &&
736 MI->getOperand(1).isRegister() &&
737 (MI->getNumOperands() == 2 ||
738 (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
739 && "Bad format for MRMSrcReg!");
740 if (MI->getNumOperands() == 3 &&
741 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
744 O << TII.getName(MI->getOpCode()) << " ";
745 printOp(MI->getOperand(0));
747 printOp(MI->getOperand(MI->getNumOperands()-1));
752 case X86II::MRMSrcMem: {
753 // These instructions are the same as MRMSrcReg, but instead of having a
754 // register reference for the mod/rm field, it's a memory reference.
756 assert(MI->getOperand(0).isRegister() &&
757 (MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
758 (MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
760 && "Bad format for MRMDestReg!");
761 if (MI->getNumOperands() == 2+4 &&
762 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
765 O << TII.getName(MI->getOpCode()) << " ";
766 printOp(MI->getOperand(0));
767 O << ", " << sizePtr(Desc) << " ";
768 printMemReference(MI, MI->getNumOperands()-4);
773 case X86II::MRMS0r: case X86II::MRMS1r:
774 case X86II::MRMS2r: case X86II::MRMS3r:
775 case X86II::MRMS4r: case X86II::MRMS5r:
776 case X86II::MRMS6r: case X86II::MRMS7r: {
777 // In this form, the following are valid formats:
779 // 2. cmp reg, immediate
780 // 2. shl rdest, rinput <implicit CL or 1>
781 // 3. sbb rdest, rinput, immediate [rdest = rinput]
783 assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
784 MI->getOperand(0).isRegister() && "Bad MRMSxR format!");
785 assert((MI->getNumOperands() != 2 ||
786 MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&&
787 "Bad MRMSxR format!");
788 assert((MI->getNumOperands() < 3 ||
789 (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) &&
790 "Bad MRMSxR format!");
792 if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() &&
793 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
796 O << TII.getName(MI->getOpCode()) << " ";
797 printOp(MI->getOperand(0));
798 if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
800 printOp(MI->getOperand(MI->getNumOperands()-1));
808 case X86II::MRMS0m: case X86II::MRMS1m:
809 case X86II::MRMS2m: case X86II::MRMS3m:
810 case X86II::MRMS4m: case X86II::MRMS5m:
811 case X86II::MRMS6m: case X86II::MRMS7m: {
812 // In this form, the following are valid formats:
814 // 2. cmp [m], immediate
815 // 2. shl [m], rinput <implicit CL or 1>
816 // 3. sbb [m], immediate
818 assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 &&
819 isMem(MI, 0) && "Bad MRMSxM format!");
820 assert((MI->getNumOperands() != 5 || MI->getOperand(4).isImmediate()) &&
821 "Bad MRMSxM format!");
822 // Bug: The 80-bit FP store-pop instruction "fstp XWORD PTR [...]"
823 // is misassembled by gas in intel_syntax mode as its 32-bit
824 // equivalent "fstp DWORD PTR [...]". Workaround: Output the raw
825 // opcode bytes instead of the instruction.
826 if (MI->getOpCode() == X86::FSTPr80) {
827 if ((MI->getOperand(0).getReg() == X86::ESP)
828 && (MI->getOperand(1).getImmedValue() == 1)) {
829 int DispVal = MI->getOperand(3).getImmedValue();
830 if ((DispVal < -128) || (DispVal > 127)) { // 4 byte disp.
831 unsigned int val = (unsigned int) DispVal;
832 O << ".byte 0xdb, 0xbc, 0x24\n\t";
833 O << ".long 0x" << std::hex << (unsigned) val << std::dec << "\t# ";
834 } else { // 1 byte disp.
835 unsigned char val = (unsigned char) DispVal;
836 O << ".byte 0xdb, 0x7c, 0x24, 0x" << std::hex << (unsigned) val
837 << std::dec << "\t# ";
841 // Bug: The 80-bit FP load instruction "fld XWORD PTR [...]" is
842 // misassembled by gas in intel_syntax mode as its 32-bit
843 // equivalent "fld DWORD PTR [...]". Workaround: Output the raw
844 // opcode bytes instead of the instruction.
845 if (MI->getOpCode() == X86::FLDr80) {
846 if ((MI->getOperand(0).getReg() == X86::ESP)
847 && (MI->getOperand(1).getImmedValue() == 1)) {
848 int DispVal = MI->getOperand(3).getImmedValue();
849 if ((DispVal < -128) || (DispVal > 127)) { // 4 byte disp.
850 unsigned int val = (unsigned int) DispVal;
851 O << ".byte 0xdb, 0xac, 0x24\n\t";
852 O << ".long 0x" << std::hex << (unsigned) val << std::dec << "\t# ";
853 } else { // 1 byte disp.
854 unsigned char val = (unsigned char) DispVal;
855 O << ".byte 0xdb, 0x6c, 0x24, 0x" << std::hex << (unsigned) val
856 << std::dec << "\t# ";
860 // Bug: gas intel_syntax mode treats "fild QWORD PTR [...]" as an
861 // invalid opcode, saying "64 bit operations are only supported in
862 // 64 bit modes." libopcodes disassembles it as "fild DWORD PTR
863 // [...]", which is wrong. Workaround: Output the raw opcode bytes
864 // instead of the instruction.
865 if (MI->getOpCode() == X86::FILDr64) {
866 if ((MI->getOperand(0).getReg() == X86::ESP)
867 && (MI->getOperand(1).getImmedValue() == 1)) {
868 int DispVal = MI->getOperand(3).getImmedValue();
869 if ((DispVal < -128) || (DispVal > 127)) { // 4 byte disp.
870 unsigned int val = (unsigned int) DispVal;
871 O << ".byte 0xdf, 0xac, 0x24\n\t";
872 O << ".long 0x" << std::hex << (unsigned) val << std::dec << "\t# ";
873 } else { // 1 byte disp.
874 unsigned char val = (unsigned char) DispVal;
875 O << ".byte 0xdf, 0x6c, 0x24, 0x" << std::hex << (unsigned) val
876 << std::dec << "\t# ";
880 // Bug: gas intel_syntax mode treats "fistp QWORD PTR [...]" as
881 // an invalid opcode, saying "64 bit operations are only
882 // supported in 64 bit modes." libopcodes disassembles it as
883 // "fistpll DWORD PTR [...]", which is wrong. Workaround: Output
884 // "fistpll DWORD PTR " instead, which is what libopcodes is
886 if (MI->getOpCode() == X86::FISTPr64) {
887 O << "fistpll DWORD PTR ";
888 printMemReference(MI, 0);
889 if (MI->getNumOperands() == 5) {
891 printOp(MI->getOperand(4));
896 O << TII.getName(MI->getOpCode()) << " ";
897 O << sizePtr(Desc) << " ";
898 printMemReference(MI, 0);
899 if (MI->getNumOperands() == 5) {
901 printOp(MI->getOperand(4));
908 O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break;
912 bool Printer::doInitialization(Module &M) {
913 // Tell gas we are outputting Intel syntax (not AT&T syntax) assembly.
915 // Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an
916 // instruction as a reference to the register named sp, and if you try to
917 // reference a symbol `Sp' (e.g. `mov ECX, OFFSET Sp') then it gets lowercased
918 // before being looked up in the symbol table. This creates spurious
919 // `undefined symbol' errors when linking. Workaround: Do not use `noprefix'
920 // mode, and decorate all register names with percent signs.
921 O << "\t.intel_syntax\n";
922 Mang = new Mangler(M, EmitCygwin);
923 return false; // success
926 static const Function *isConstantFunctionPointerRef(const Constant *C) {
927 if (const ConstantPointerRef *R = dyn_cast<ConstantPointerRef>(C))
928 if (const Function *F = dyn_cast<Function>(R->getValue()))
933 bool Printer::doFinalization(Module &M)
935 const TargetData &TD = TM.getTargetData();
936 // Print out module-level global variables here.
937 for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I) {
938 std::string name(Mang->getValueName(I));
939 if (I->hasInitializer()) {
940 Constant *C = I->getInitializer();
941 if (C->isNullValue()) {
942 O << "\n\n\t.comm " << name << "," << TD.getTypeSize(C->getType())
943 << "," << (unsigned)TD.getTypeAlignment(C->getType());
945 WriteAsOperand(O, I, true, true, &M);
948 O << "\n\n\t.data\n";
949 O << "\t.globl " << name << "\n";
950 O << "\t.type " << name << ",@object\n";
951 O << "\t.size " << name << "," << TD.getTypeSize(C->getType()) << "\n";
952 O << "\t.align " << (unsigned)TD.getTypeAlignment(C->getType()) << "\n";
953 O << name << ":\t\t\t\t# ";
954 WriteAsOperand(O, I, true, true, &M);
956 WriteAsOperand(O, C, false, false, &M);
958 printConstantValueOnly(C);
961 O << "\t.globl " << name << "\n";
962 O << "\t.comm " << name << ", "
963 << (unsigned)TD.getTypeSize(I->getType()) << ", "
964 << (unsigned)TD.getTypeAlignment(I->getType()) << "\n";
968 return false; // success