1 //===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
3 // This file contains a printer that converts from our internal representation
4 // of LLVM code to a nice human readable form that is suitable for debuggging.
6 //===----------------------------------------------------------------------===//
9 #include "X86InstrInfo.h"
10 #include "llvm/Pass.h"
11 #include "llvm/Function.h"
12 #include "llvm/Target/TargetMachine.h"
13 #include "llvm/CodeGen/MachineFunction.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "Support/Statistic.h"
18 struct Printer : public FunctionPass {
22 Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {}
24 bool runOnFunction(Function &F);
28 /// createX86CodePrinterPass - Print out the specified machine code function to
29 /// the specified stream. This function should work regardless of whether or
30 /// not the function is in SSA form or not.
32 Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) {
33 return new Printer(TM, O);
37 /// runOnFunction - This uses the X86InstructionInfo::print method
38 /// to print assembly for each instruction.
39 bool Printer::runOnFunction (Function & F)
41 static unsigned bbnumber = 0;
42 MachineFunction & MF = MachineFunction::get (&F);
43 const MachineInstrInfo & MII = TM.getInstrInfo ();
45 O << "; x86 printing only sorta implemented so far!\n";
47 // Print out labels for the function.
48 O << "\t.globl\t" << F.getName () << "\n";
49 O << "\t.type\t" << F.getName () << ", @function\n";
50 O << F.getName () << ":\n";
52 // Print out code for the function.
53 for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end ();
56 // Print a label for the basic block.
57 O << ".BB" << bbnumber++ << ":\n";
58 for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e =
59 bb_i->end (); i_i != i_e; ++i_i)
61 // Print the assembly for the instruction.
63 MII.print(*i_i, O, TM);
67 // We didn't modify anything.
71 static bool isReg(const MachineOperand &MO) {
72 return MO.getType() == MachineOperand::MO_VirtualRegister ||
73 MO.getType() == MachineOperand::MO_MachineRegister;
76 static bool isImmediate(const MachineOperand &MO) {
77 return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
78 MO.getType() == MachineOperand::MO_UnextendedImmed;
81 static bool isScale(const MachineOperand &MO) {
82 return isImmediate(MO) &&
83 (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
84 MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
87 static bool isMem(const MachineInstr *MI, unsigned Op) {
88 return Op+4 <= MI->getNumOperands() &&
89 isReg(MI->getOperand(Op )) && isScale(MI->getOperand(Op+1)) &&
90 isReg(MI->getOperand(Op+2)) && isImmediate(MI->getOperand(Op+3));
93 static void printOp(std::ostream &O, const MachineOperand &MO,
94 const MRegisterInfo &RI) {
95 switch (MO.getType()) {
96 case MachineOperand::MO_VirtualRegister:
97 case MachineOperand::MO_MachineRegister:
98 if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
99 O << RI.get(MO.getReg()).Name;
101 O << "%reg" << MO.getReg();
104 case MachineOperand::MO_SignExtendedImmed:
105 case MachineOperand::MO_UnextendedImmed:
106 O << (int)MO.getImmedValue();
109 O << "<unknown op ty>"; return;
113 static void printMemReference(std::ostream &O, const MachineInstr *MI,
114 unsigned Op, const MRegisterInfo &RI) {
115 assert(isMem(MI, Op) && "Invalid memory reference!");
116 const MachineOperand &BaseReg = MI->getOperand(Op);
117 const MachineOperand &Scale = MI->getOperand(Op+1);
118 const MachineOperand &IndexReg = MI->getOperand(Op+2);
119 const MachineOperand &Disp = MI->getOperand(Op+3);
122 bool NeedPlus = false;
123 if (BaseReg.getReg()) {
124 printOp(O, BaseReg, RI);
128 if (IndexReg.getReg()) {
129 if (NeedPlus) O << " + ";
130 if (IndexReg.getImmedValue() != 1)
131 O << IndexReg.getImmedValue() << "*";
132 printOp(O, IndexReg, RI);
136 if (Disp.getImmedValue()) {
137 if (NeedPlus) O << " + ";
138 printOp(O, Disp, RI);
143 static inline void toHexDigit(std::ostream &O, unsigned char V) {
145 O << (char)('A'+V-10);
150 static std::ostream &toHex(std::ostream &O, unsigned char V) {
151 toHexDigit(O, V >> 4);
152 toHexDigit(O, V & 0xF);
156 static std::ostream &emitConstant(std::ostream &O, unsigned Val, unsigned Size){
157 // Output the constant in little endian byte order...
158 for (unsigned i = 0; i != Size; ++i) {
159 toHex(O, Val) << " ";
165 namespace N86 { // Native X86 Register numbers...
167 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
172 // getX86RegNum - This function maps LLVM register identifiers to their X86
173 // specific numbering, which is used in various places encoding instructions.
175 static unsigned getX86RegNum(unsigned RegNo) {
177 case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
178 case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
179 case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
180 case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
181 case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
182 case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
183 case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
184 case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
186 assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
187 "Unknown physical register!");
188 DEBUG(std::cerr << "Register allocator hasn't allocated " << RegNo
189 << " correctly yet!\n");
194 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
196 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
197 return RM | (RegOpcode << 3) | (Mod << 6);
200 static void emitRegModRMByte(std::ostream &O, unsigned ModRMReg,
201 unsigned RegOpcodeField) {
202 toHex(O, ModRMByte(3, RegOpcodeField, getX86RegNum(ModRMReg)));
205 inline static void emitSIBByte(std::ostream &O, unsigned SS, unsigned Index,
207 // SIB byte is in the same format as the ModRMByte...
208 toHex(O, ModRMByte(SS, Index, Base));
211 static bool isDisp8(int Value) {
212 return Value == (signed char)Value;
215 static void emitMemModRMByte(std::ostream &O, const MachineInstr *MI,
216 unsigned Op, unsigned RegOpcodeField) {
217 assert(isMem(MI, Op) && "Invalid memory reference!");
218 const MachineOperand &BaseReg = MI->getOperand(Op);
219 const MachineOperand &Scale = MI->getOperand(Op+1);
220 const MachineOperand &IndexReg = MI->getOperand(Op+2);
221 const MachineOperand &Disp = MI->getOperand(Op+3);
223 // Is a SIB byte needed?
224 if (IndexReg.getReg() == 0 && BaseReg.getReg() != X86::ESP) {
225 if (BaseReg.getReg() == 0) { // Just a displacement?
226 // Emit special case [disp32] encoding
227 toHex(O, ModRMByte(0, RegOpcodeField, 5));
228 emitConstant(O, Disp.getImmedValue(), 4);
230 unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
231 if (Disp.getImmedValue() == 0 && BaseRegNo != N86::EBP) {
232 // Emit simple indirect register encoding... [EAX] f.e.
233 toHex(O, ModRMByte(0, RegOpcodeField, BaseRegNo));
234 } else if (isDisp8(Disp.getImmedValue())) {
235 // Emit the disp8 encoding... [REG+disp8]
236 toHex(O, ModRMByte(1, RegOpcodeField, BaseRegNo));
237 emitConstant(O, Disp.getImmedValue(), 1);
239 // Emit the most general non-SIB encoding: [REG+disp32]
240 toHex(O, ModRMByte(1, RegOpcodeField, BaseRegNo));
241 emitConstant(O, Disp.getImmedValue(), 4);
245 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
246 assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
248 bool ForceDisp32 = false;
249 if (BaseReg.getReg() == 0) {
250 // If there is no base register, we emit the special case SIB byte with
251 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
252 toHex(O, ModRMByte(0, RegOpcodeField, 4));
254 } else if (Disp.getImmedValue() == 0) {
255 // Emit no displacement ModR/M byte
256 toHex(O, ModRMByte(0, RegOpcodeField, 4));
257 } else if (isDisp8(Disp.getImmedValue())) {
258 // Emit the disp8 encoding...
259 toHex(O, ModRMByte(1, RegOpcodeField, 4));
261 // Emit the normal disp32 encoding...
262 toHex(O, ModRMByte(2, RegOpcodeField, 4));
265 // Calculate what the SS field value should be...
266 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
267 unsigned SS = SSTable[Scale.getImmedValue()];
269 if (BaseReg.getReg() == 0) {
270 // Handle the SIB byte for the case where there is no base. The
271 // displacement has already been output.
272 assert(IndexReg.getReg() && "Index register must be specified!");
273 emitSIBByte(O, SS, getX86RegNum(IndexReg.getReg()), 5);
275 unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
276 unsigned IndexRegNo = getX86RegNum(IndexReg.getReg());
277 emitSIBByte(O, SS, IndexRegNo, BaseRegNo);
280 // Do we need to output a displacement?
281 if (Disp.getImmedValue() != 0 || ForceDisp32) {
282 if (!ForceDisp32 && isDisp8(Disp.getImmedValue()))
283 emitConstant(O, Disp.getImmedValue(), 1);
285 emitConstant(O, Disp.getImmedValue(), 4);
291 // print - Print out an x86 instruction in intel syntax
292 void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
293 const TargetMachine &TM) const {
294 unsigned Opcode = MI->getOpcode();
295 const MachineInstrDescriptor &Desc = get(Opcode);
297 // Print instruction prefixes if neccesary
298 if (Desc.TSFlags & X86II::OpSize) O << "66 "; // Operand size...
299 if (Desc.TSFlags & X86II::TB) O << "0F "; // Two-byte opcode prefix
301 switch (Desc.TSFlags & X86II::FormMask) {
302 case X86II::OtherFrm:
304 O << "-"; MI->print(O, TM);
308 toHex(O, getBaseOpcodeFor(Opcode));
310 O << getName(MI->getOpCode()) << " ";
312 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
314 printOp(O, MI->getOperand(i), RI);
319 case X86II::AddRegFrm: {
320 // There are currently two forms of acceptable AddRegFrm instructions.
321 // Either the instruction JUST takes a single register (like inc, dec, etc),
322 // or it takes a register and an immediate of the same size as the register
323 // (move immediate f.e.).
325 assert(isReg(MI->getOperand(0)) &&
326 (MI->getNumOperands() == 1 ||
327 (MI->getNumOperands() == 2 && isImmediate(MI->getOperand(1)))) &&
328 "Illegal form for AddRegFrm instruction!");
330 unsigned Reg = MI->getOperand(0).getReg();
331 toHex(O, getBaseOpcodeFor(Opcode) + getX86RegNum(Reg)) << " ";
333 if (MI->getNumOperands() == 2) {
335 emitConstant(O, MI->getOperand(1).getImmedValue(), Size);
339 O << getName(MI->getOpCode()) << " ";
340 printOp(O, MI->getOperand(0), RI);
341 if (MI->getNumOperands() == 2) {
343 printOp(O, MI->getOperand(1), RI);
348 case X86II::MRMDestReg: {
349 // There are two acceptable forms of MRMDestReg instructions, those with 3
352 // 3 Operands: in this form, the first two registers (the destination, and
353 // the first operand) should be the same, post register allocation. The 3rd
354 // operand is an additional input. This should be for things like add
357 // 2 Operands: this is for things like mov that do not read a second input
359 assert(isReg(MI->getOperand(0)) &&
360 (MI->getNumOperands() == 2 ||
361 (MI->getNumOperands() == 3 && isReg(MI->getOperand(1)))) &&
362 isReg(MI->getOperand(MI->getNumOperands()-1))
363 && "Bad format for MRMDestReg!");
364 if (MI->getNumOperands() == 3 &&
365 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
368 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
369 unsigned ModRMReg = MI->getOperand(0).getReg();
370 unsigned ExtraReg = MI->getOperand(MI->getNumOperands()-1).getReg();
371 emitRegModRMByte(O, ModRMReg, getX86RegNum(ExtraReg));
374 O << getName(MI->getOpCode()) << " ";
375 printOp(O, MI->getOperand(0), RI);
377 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
382 case X86II::MRMDestMem: {
383 // These instructions are the same as MRMDestReg, but instead of having a
384 // register reference for the mod/rm field, it's a memory reference.
386 assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
387 isReg(MI->getOperand(4)) && "Bad format for MRMDestMem!");
388 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
389 emitMemModRMByte(O, MI, 0, getX86RegNum(MI->getOperand(4).getReg()));
392 O << getName(MI->getOpCode()) << " <SIZE> PTR ";
393 printMemReference(O, MI, 0, RI);
395 printOp(O, MI->getOperand(4), RI);
400 case X86II::MRMSrcReg: {
401 // There is a two forms that are acceptable for MRMSrcReg instructions,
402 // those with 3 and 2 operands:
404 // 3 Operands: in this form, the last register (the second input) is the
405 // ModR/M input. The first two operands should be the same, post register
406 // allocation. This is for things like: add r32, r/m32
408 // 2 Operands: this is for things like mov that do not read a second input
410 assert(isReg(MI->getOperand(0)) &&
411 isReg(MI->getOperand(1)) &&
412 (MI->getNumOperands() == 2 ||
413 (MI->getNumOperands() == 3 && isReg(MI->getOperand(2))))
414 && "Bad format for MRMDestReg!");
415 if (MI->getNumOperands() == 3 &&
416 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
419 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
420 unsigned ModRMReg = MI->getOperand(MI->getNumOperands()-1).getReg();
421 unsigned ExtraReg = MI->getOperand(0).getReg();
422 emitRegModRMByte(O, ModRMReg, getX86RegNum(ExtraReg));
425 O << getName(MI->getOpCode()) << " ";
426 printOp(O, MI->getOperand(0), RI);
428 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
433 case X86II::MRMSrcMem: {
434 // These instructions are the same as MRMSrcReg, but instead of having a
435 // register reference for the mod/rm field, it's a memory reference.
437 assert(isReg(MI->getOperand(0)) &&
438 (MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
439 (MI->getNumOperands() == 2+4 && isReg(MI->getOperand(1)) &&
441 && "Bad format for MRMDestReg!");
442 if (MI->getNumOperands() == 2+4 &&
443 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
446 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
447 unsigned ExtraReg = MI->getOperand(0).getReg();
448 emitMemModRMByte(O, MI, MI->getNumOperands()-4, getX86RegNum(ExtraReg));
451 O << getName(MI->getOpCode()) << " ";
452 printOp(O, MI->getOperand(0), RI);
453 O << ", <SIZE> PTR ";
454 printMemReference(O, MI, MI->getNumOperands()-4, RI);
459 case X86II::MRMS0r: case X86II::MRMS1r:
460 case X86II::MRMS2r: case X86II::MRMS3r:
461 case X86II::MRMS4r: case X86II::MRMS5r:
462 case X86II::MRMS6r: case X86II::MRMS7r: {
463 unsigned ExtraField = (Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r;
465 // In this form, the following are valid formats:
467 // 2. shl rdest, rinput <implicit CL or 1>
468 // 3. sbb rdest, rinput, immediate [rdest = rinput]
470 assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
471 isReg(MI->getOperand(0)) && "Bad MRMSxR format!");
472 assert((MI->getNumOperands() < 2 || isReg(MI->getOperand(1))) &&
473 "Bad MRMSxR format!");
474 assert((MI->getNumOperands() < 3 || isImmediate(MI->getOperand(2))) &&
475 "Bad MRMSxR format!");
477 if (MI->getNumOperands() > 1 &&
478 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
481 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
482 emitRegModRMByte(O, MI->getOperand(0).getReg(), ExtraField);
484 if (MI->getNumOperands() == 3) {
486 emitConstant(O, MI->getOperand(2).getImmedValue(), Size);
490 O << getName(MI->getOpCode()) << " ";
491 printOp(O, MI->getOperand(0), RI);
492 if (MI->getNumOperands() == 3) {
494 printOp(O, MI->getOperand(2), RI);
502 O << "\t\t\t-"; MI->print(O, TM); break;