1 //===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
3 // This file contains a printer that converts from our internal representation
4 // of LLVM code to a nice human readable form that is suitable for debuggging.
6 //===----------------------------------------------------------------------===//
9 #include "X86InstrInfo.h"
10 #include "llvm/Function.h"
11 #include "llvm/Constant.h"
12 #include "llvm/Target/TargetMachine.h"
13 #include "llvm/CodeGen/MachineFunctionPass.h"
14 #include "llvm/CodeGen/MachineConstantPool.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "Support/Statistic.h"
19 struct Printer : public MachineFunctionPass {
22 Printer(std::ostream &o) : O(o), ConstIdx(0) {}
24 virtual const char *getPassName() const {
25 return "X86 Assembly Printer";
28 void printConstantPool(MachineConstantPool *MCP, const TargetData &TD);
29 bool runOnMachineFunction(MachineFunction &F);
33 /// createX86CodePrinterPass - Print out the specified machine code function to
34 /// the specified stream. This function should work regardless of whether or
35 /// not the function is in SSA form or not.
37 Pass *createX86CodePrinterPass(std::ostream &O) {
38 return new Printer(O);
42 // printConstantPool - Print out any constants which have been spilled to
44 void Printer::printConstantPool(MachineConstantPool *MCP, const TargetData &TD){
45 const std::vector<Constant*> &CP = MCP->getConstants();
46 if (CP.empty()) return;
48 for (unsigned i = 0, e = CP.size(); i != e; ++i) {
49 O << "\t.section .rodata\n";
50 O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) << "\n";
51 O << ".CPI" << i+ConstIdx << ":\t\t\t\t\t;" << *CP[i] << "\n";
52 O << "\t*Constant output not implemented yet!*\n\n";
54 ConstIdx += CP.size(); // Don't recycle constant pool index numbers
57 /// runOnFunction - This uses the X86InstructionInfo::print method
58 /// to print assembly for each instruction.
59 bool Printer::runOnMachineFunction(MachineFunction &MF) {
60 static unsigned BBNumber = 0;
61 const TargetMachine &TM = MF.getTarget();
62 const TargetInstrInfo &TII = TM.getInstrInfo();
64 // Print out constants referenced by the function
65 printConstantPool(MF.getConstantPool(), TM.getTargetData());
67 // Print out labels for the function.
70 O << "\t.globl\t" << MF.getFunction()->getName() << "\n";
71 O << "\t.type\t" << MF.getFunction()->getName() << ", @function\n";
72 O << MF.getFunction()->getName() << ":\n";
74 // Print out code for the function.
75 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
77 // Print a label for the basic block.
78 O << ".BB" << BBNumber++ << ":\n";
79 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
81 // Print the assembly for the instruction.
83 TII.print(*II, O, TM);
87 // We didn't modify anything.
91 static bool isScale(const MachineOperand &MO) {
92 return MO.isImmediate() &&
93 (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
94 MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
97 static bool isMem(const MachineInstr *MI, unsigned Op) {
98 if (MI->getOperand(Op).isFrameIndex()) return true;
99 if (MI->getOperand(Op).isConstantPoolIndex()) return true;
100 return Op+4 <= MI->getNumOperands() &&
101 MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
102 MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
105 static void printOp(std::ostream &O, const MachineOperand &MO,
106 const MRegisterInfo &RI) {
107 switch (MO.getType()) {
108 case MachineOperand::MO_VirtualRegister:
109 if (Value *V = MO.getVRegValueOrNull()) {
110 O << "<" << V->getName() << ">";
114 case MachineOperand::MO_MachineRegister:
115 if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
116 O << RI.get(MO.getReg()).Name;
118 O << "%reg" << MO.getReg();
121 case MachineOperand::MO_SignExtendedImmed:
122 case MachineOperand::MO_UnextendedImmed:
123 O << (int)MO.getImmedValue();
125 case MachineOperand::MO_PCRelativeDisp:
126 O << "<" << MO.getVRegValue()->getName() << ">";
128 case MachineOperand::MO_GlobalAddress:
129 O << "<" << MO.getGlobal()->getName() << ">";
131 case MachineOperand::MO_ExternalSymbol:
132 O << "<" << MO.getSymbolName() << ">";
135 O << "<unknown op ty>"; return;
139 static const std::string sizePtr(const TargetInstrDescriptor &Desc) {
140 switch (Desc.TSFlags & X86II::ArgMask) {
141 default: assert(0 && "Unknown arg size!");
142 case X86II::Arg8: return "BYTE PTR";
143 case X86II::Arg16: return "WORD PTR";
144 case X86II::Arg32: return "DWORD PTR";
145 case X86II::Arg64: return "QWORD PTR";
146 case X86II::ArgF32: return "DWORD PTR";
147 case X86II::ArgF64: return "QWORD PTR";
148 case X86II::ArgF80: return "XWORD PTR";
152 static void printMemReference(std::ostream &O, const MachineInstr *MI,
153 unsigned Op, const MRegisterInfo &RI) {
154 assert(isMem(MI, Op) && "Invalid memory reference!");
156 if (MI->getOperand(Op).isFrameIndex()) {
157 O << "[frame slot #" << MI->getOperand(Op).getFrameIndex();
158 if (MI->getOperand(Op+3).getImmedValue())
159 O << " + " << MI->getOperand(Op+3).getImmedValue();
162 } else if (MI->getOperand(Op).isConstantPoolIndex()) {
163 O << "[.CPI" << MI->getOperand(Op).getConstantPoolIndex();
164 if (MI->getOperand(Op+3).getImmedValue())
165 O << " + " << MI->getOperand(Op+3).getImmedValue();
170 const MachineOperand &BaseReg = MI->getOperand(Op);
171 int ScaleVal = MI->getOperand(Op+1).getImmedValue();
172 const MachineOperand &IndexReg = MI->getOperand(Op+2);
173 int DispVal = MI->getOperand(Op+3).getImmedValue();
176 bool NeedPlus = false;
177 if (BaseReg.getReg()) {
178 printOp(O, BaseReg, RI);
182 if (IndexReg.getReg()) {
183 if (NeedPlus) O << " + ";
185 O << ScaleVal << "*";
186 printOp(O, IndexReg, RI);
203 // print - Print out an x86 instruction in intel syntax
204 void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
205 const TargetMachine &TM) const {
206 unsigned Opcode = MI->getOpcode();
207 const TargetInstrDescriptor &Desc = get(Opcode);
209 switch (Desc.TSFlags & X86II::FormMask) {
211 if (Opcode == X86::PHI) {
212 printOp(O, MI->getOperand(0), RI);
214 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
215 if (i != 1) O << ", ";
217 printOp(O, MI->getOperand(i), RI);
219 printOp(O, MI->getOperand(i+1), RI);
224 if (MI->getNumOperands() && (MI->getOperand(0).opIsDefOnly() ||
225 MI->getOperand(0).opIsDefAndUse())) {
226 printOp(O, MI->getOperand(0), RI);
230 O << getName(MI->getOpcode());
232 for (unsigned e = MI->getNumOperands(); i != e; ++i) {
234 if (MI->getOperand(i).opIsDefOnly() ||
235 MI->getOperand(i).opIsDefAndUse()) O << "*";
236 printOp(O, MI->getOperand(i), RI);
237 if (MI->getOperand(i).opIsDefOnly() ||
238 MI->getOperand(i).opIsDefAndUse()) O << "*";
245 // The accepted forms of Raw instructions are:
246 // 1. nop - No operand required
247 // 2. jmp foo - PC relative displacement operand
248 // 3. call bar - GlobalAddress Operand or External Symbol Operand
250 assert(MI->getNumOperands() == 0 ||
251 (MI->getNumOperands() == 1 &&
252 (MI->getOperand(0).isPCRelativeDisp() ||
253 MI->getOperand(0).isGlobalAddress() ||
254 MI->getOperand(0).isExternalSymbol())) &&
255 "Illegal raw instruction!");
256 O << getName(MI->getOpcode()) << " ";
258 if (MI->getNumOperands() == 1) {
259 printOp(O, MI->getOperand(0), RI);
264 case X86II::AddRegFrm: {
265 // There are currently two forms of acceptable AddRegFrm instructions.
266 // Either the instruction JUST takes a single register (like inc, dec, etc),
267 // or it takes a register and an immediate of the same size as the register
268 // (move immediate f.e.). Note that this immediate value might be stored as
269 // an LLVM value, to represent, for example, loading the address of a global
270 // into a register. The initial register might be duplicated if this is a
271 // M_2_ADDR_REG instruction
273 assert(MI->getOperand(0).isRegister() &&
274 (MI->getNumOperands() == 1 ||
275 (MI->getNumOperands() == 2 &&
276 (MI->getOperand(1).getVRegValueOrNull() ||
277 MI->getOperand(1).isImmediate() ||
278 MI->getOperand(1).isRegister() ||
279 MI->getOperand(1).isGlobalAddress() ||
280 MI->getOperand(1).isExternalSymbol()))) &&
281 "Illegal form for AddRegFrm instruction!");
283 unsigned Reg = MI->getOperand(0).getReg();
285 O << getName(MI->getOpCode()) << " ";
286 printOp(O, MI->getOperand(0), RI);
287 if (MI->getNumOperands() == 2 &&
288 (!MI->getOperand(1).isRegister() ||
289 MI->getOperand(1).getVRegValueOrNull() ||
290 MI->getOperand(1).isGlobalAddress() ||
291 MI->getOperand(1).isExternalSymbol())) {
293 printOp(O, MI->getOperand(1), RI);
298 case X86II::MRMDestReg: {
299 // There are two acceptable forms of MRMDestReg instructions, those with 2,
302 // 2 Operands: this is for things like mov that do not read a second input
304 // 3 Operands: in this form, the first two registers (the destination, and
305 // the first operand) should be the same, post register allocation. The 3rd
306 // operand is an additional input. This should be for things like add
309 // 4 Operands: This form is for instructions which are 3 operands forms, but
310 // have a constant argument as well.
312 bool isTwoAddr = isTwoAddrInstr(Opcode);
313 assert(MI->getOperand(0).isRegister() &&
314 (MI->getNumOperands() == 2 ||
315 (isTwoAddr && MI->getOperand(1).isRegister() &&
316 MI->getOperand(0).getReg() == MI->getOperand(1).getReg() &&
317 (MI->getNumOperands() == 3 ||
318 (MI->getNumOperands() == 4 && MI->getOperand(3).isImmediate()))))
319 && "Bad format for MRMDestReg!");
321 O << getName(MI->getOpCode()) << " ";
322 printOp(O, MI->getOperand(0), RI);
324 printOp(O, MI->getOperand(1+isTwoAddr), RI);
325 if (MI->getNumOperands() == 4) {
327 printOp(O, MI->getOperand(3), RI);
333 case X86II::MRMDestMem: {
334 // These instructions are the same as MRMDestReg, but instead of having a
335 // register reference for the mod/rm field, it's a memory reference.
337 assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
338 MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
340 O << getName(MI->getOpCode()) << " " << sizePtr(Desc) << " ";
341 printMemReference(O, MI, 0, RI);
343 printOp(O, MI->getOperand(4), RI);
348 case X86II::MRMSrcReg: {
349 // There is a two forms that are acceptable for MRMSrcReg instructions,
350 // those with 3 and 2 operands:
352 // 3 Operands: in this form, the last register (the second input) is the
353 // ModR/M input. The first two operands should be the same, post register
354 // allocation. This is for things like: add r32, r/m32
356 // 2 Operands: this is for things like mov that do not read a second input
358 assert(MI->getOperand(0).isRegister() &&
359 MI->getOperand(1).isRegister() &&
360 (MI->getNumOperands() == 2 ||
361 (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
362 && "Bad format for MRMSrcReg!");
363 if (MI->getNumOperands() == 3 &&
364 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
367 O << getName(MI->getOpCode()) << " ";
368 printOp(O, MI->getOperand(0), RI);
370 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
375 case X86II::MRMSrcMem: {
376 // These instructions are the same as MRMSrcReg, but instead of having a
377 // register reference for the mod/rm field, it's a memory reference.
379 assert(MI->getOperand(0).isRegister() &&
380 (MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
381 (MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
383 && "Bad format for MRMDestReg!");
384 if (MI->getNumOperands() == 2+4 &&
385 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
388 O << getName(MI->getOpCode()) << " ";
389 printOp(O, MI->getOperand(0), RI);
390 O << ", " << sizePtr(Desc) << " ";
391 printMemReference(O, MI, MI->getNumOperands()-4, RI);
396 case X86II::MRMS0r: case X86II::MRMS1r:
397 case X86II::MRMS2r: case X86II::MRMS3r:
398 case X86II::MRMS4r: case X86II::MRMS5r:
399 case X86II::MRMS6r: case X86II::MRMS7r: {
400 // In this form, the following are valid formats:
402 // 2. cmp reg, immediate
403 // 2. shl rdest, rinput <implicit CL or 1>
404 // 3. sbb rdest, rinput, immediate [rdest = rinput]
406 assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
407 MI->getOperand(0).isRegister() && "Bad MRMSxR format!");
408 assert((MI->getNumOperands() != 2 ||
409 MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&&
410 "Bad MRMSxR format!");
411 assert((MI->getNumOperands() < 3 ||
412 (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) &&
413 "Bad MRMSxR format!");
415 if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() &&
416 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
419 O << getName(MI->getOpCode()) << " ";
420 printOp(O, MI->getOperand(0), RI);
421 if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
423 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
430 case X86II::MRMS0m: case X86II::MRMS1m:
431 case X86II::MRMS2m: case X86II::MRMS3m:
432 case X86II::MRMS4m: case X86II::MRMS5m:
433 case X86II::MRMS6m: case X86II::MRMS7m: {
434 // In this form, the following are valid formats:
436 // 2. cmp [m], immediate
437 // 2. shl [m], rinput <implicit CL or 1>
438 // 3. sbb [m], immediate
440 assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 &&
441 isMem(MI, 0) && "Bad MRMSxM format!");
442 assert((MI->getNumOperands() != 5 || MI->getOperand(4).isImmediate()) &&
443 "Bad MRMSxM format!");
445 O << getName(MI->getOpCode()) << " ";
446 O << sizePtr(Desc) << " ";
447 printMemReference(O, MI, 0, RI);
448 if (MI->getNumOperands() == 5) {
450 printOp(O, MI->getOperand(4), RI);
457 O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break;