1 //===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
3 // This file contains a printer that converts from our internal representation
4 // of LLVM code to a nice human readable form that is suitable for debuggging.
6 //===----------------------------------------------------------------------===//
9 #include "X86InstrInfo.h"
10 #include "llvm/Pass.h"
11 #include "llvm/Function.h"
12 #include "llvm/Target/TargetMachine.h"
13 #include "llvm/CodeGen/MachineFunction.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "Support/Statistic.h"
18 struct Printer : public FunctionPass {
22 Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {}
24 bool runOnFunction(Function &F);
28 /// createX86CodePrinterPass - Print out the specified machine code function to
29 /// the specified stream. This function should work regardless of whether or
30 /// not the function is in SSA form or not.
32 Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) {
33 return new Printer(TM, O);
37 /// runOnFunction - This uses the X86InstructionInfo::print method
38 /// to print assembly for each instruction.
39 bool Printer::runOnFunction (Function & F)
41 static unsigned bbnumber = 0;
42 MachineFunction & MF = MachineFunction::get (&F);
43 const MachineInstrInfo & MII = TM.getInstrInfo ();
45 // Print out labels for the function.
46 O << "\t.globl\t" << F.getName () << "\n";
47 O << "\t.type\t" << F.getName () << ", @function\n";
48 O << F.getName () << ":\n";
50 // Print out code for the function.
51 for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end ();
54 // Print a label for the basic block.
55 O << ".BB" << bbnumber++ << ":\n";
56 for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e =
57 bb_i->end (); i_i != i_e; ++i_i)
59 // Print the assembly for the instruction.
61 MII.print(*i_i, O, TM);
65 // We didn't modify anything.
69 static bool isScale(const MachineOperand &MO) {
70 return MO.isImmediate() &&
71 (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
72 MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
75 static bool isMem(const MachineInstr *MI, unsigned Op) {
76 return Op+4 <= MI->getNumOperands() &&
77 MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
78 MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
81 static void printOp(std::ostream &O, const MachineOperand &MO,
82 const MRegisterInfo &RI) {
83 switch (MO.getType()) {
84 case MachineOperand::MO_VirtualRegister:
85 if (Value *V = MO.getVRegValueOrNull()) {
86 O << "<" << V->getName() << ">";
89 case MachineOperand::MO_MachineRegister:
90 if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
91 O << RI.get(MO.getReg()).Name;
93 O << "%reg" << MO.getReg();
96 case MachineOperand::MO_SignExtendedImmed:
97 case MachineOperand::MO_UnextendedImmed:
98 O << (int)MO.getImmedValue();
100 case MachineOperand::MO_PCRelativeDisp:
101 O << "<" << MO.getVRegValue()->getName() << ">";
104 O << "<unknown op ty>"; return;
108 static const std::string sizePtr (const MachineInstrDescriptor &Desc) {
109 switch (Desc.TSFlags & X86II::ArgMask) {
110 case X86II::Arg8: return "BYTE PTR";
111 case X86II::Arg16: return "WORD PTR";
112 case X86II::Arg32: return "DWORD PTR";
113 case X86II::Arg64: return "QWORD PTR";
114 case X86II::Arg80: return "XWORD PTR";
115 case X86II::Arg128: return "128BIT PTR"; // dunno what the real one is
116 default: return "<SIZE?> PTR"; // crack being smoked
120 static void printMemReference(std::ostream &O, const MachineInstr *MI,
121 unsigned Op, const MRegisterInfo &RI) {
122 assert(isMem(MI, Op) && "Invalid memory reference!");
123 const MachineOperand &BaseReg = MI->getOperand(Op);
124 const MachineOperand &Scale = MI->getOperand(Op+1);
125 const MachineOperand &IndexReg = MI->getOperand(Op+2);
126 const MachineOperand &Disp = MI->getOperand(Op+3);
129 bool NeedPlus = false;
130 if (BaseReg.getReg()) {
131 printOp(O, BaseReg, RI);
135 if (IndexReg.getReg()) {
136 if (NeedPlus) O << " + ";
137 if (Scale.getImmedValue() != 1)
138 O << Scale.getImmedValue() << "*";
139 printOp(O, IndexReg, RI);
143 if (Disp.getImmedValue()) {
144 if (NeedPlus) O << " + ";
145 printOp(O, Disp, RI);
150 // print - Print out an x86 instruction in intel syntax
151 void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
152 const TargetMachine &TM) const {
153 unsigned Opcode = MI->getOpcode();
154 const MachineInstrDescriptor &Desc = get(Opcode);
156 if (Opcode == X86::PHI) {
157 printOp(O, MI->getOperand(0), RI);
159 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
160 if (i != 1) O << ", ";
162 printOp(O, MI->getOperand(i), RI);
164 printOp(O, MI->getOperand(i+1), RI);
172 switch (Desc.TSFlags & X86II::FormMask) {
174 // The accepted forms of Raw instructions are:
175 // 1. nop - No operand required
176 // 2. jmp foo - PC relative displacement operand
178 assert(MI->getNumOperands() == 0 ||
179 (MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&&
180 "Illegal raw instruction!");
181 O << getName(MI->getOpCode()) << " ";
183 if (MI->getNumOperands() == 1) {
184 printOp(O, MI->getOperand(0), RI);
189 case X86II::AddRegFrm: {
190 // There are currently two forms of acceptable AddRegFrm instructions.
191 // Either the instruction JUST takes a single register (like inc, dec, etc),
192 // or it takes a register and an immediate of the same size as the register
193 // (move immediate f.e.). Note that this immediate value might be stored as
194 // an LLVM value, to represent, for example, loading the address of a global
197 assert(MI->getOperand(0).isRegister() &&
198 (MI->getNumOperands() == 1 ||
199 (MI->getNumOperands() == 2 &&
200 (MI->getOperand(1).getVRegValueOrNull() ||
201 MI->getOperand(1).isImmediate()))) &&
202 "Illegal form for AddRegFrm instruction!");
204 unsigned Reg = MI->getOperand(0).getReg();
206 O << getName(MI->getOpCode()) << " ";
207 printOp(O, MI->getOperand(0), RI);
208 if (MI->getNumOperands() == 2) {
210 printOp(O, MI->getOperand(1), RI);
215 case X86II::MRMDestReg: {
216 // There are two acceptable forms of MRMDestReg instructions, those with 3
219 // 3 Operands: in this form, the first two registers (the destination, and
220 // the first operand) should be the same, post register allocation. The 3rd
221 // operand is an additional input. This should be for things like add
224 // 2 Operands: this is for things like mov that do not read a second input
226 assert(MI->getOperand(0).isRegister() &&
227 (MI->getNumOperands() == 2 ||
228 (MI->getNumOperands() == 3 && MI->getOperand(1).isRegister())) &&
229 MI->getOperand(MI->getNumOperands()-1).isRegister()
230 && "Bad format for MRMDestReg!");
231 if (MI->getNumOperands() == 3 &&
232 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
235 O << getName(MI->getOpCode()) << " ";
236 printOp(O, MI->getOperand(0), RI);
238 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
243 case X86II::MRMDestMem: {
244 // These instructions are the same as MRMDestReg, but instead of having a
245 // register reference for the mod/rm field, it's a memory reference.
247 assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
248 MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
250 O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " ";
251 printMemReference(O, MI, 0, RI);
253 printOp(O, MI->getOperand(4), RI);
258 case X86II::MRMSrcReg: {
259 // There is a two forms that are acceptable for MRMSrcReg instructions,
260 // those with 3 and 2 operands:
262 // 3 Operands: in this form, the last register (the second input) is the
263 // ModR/M input. The first two operands should be the same, post register
264 // allocation. This is for things like: add r32, r/m32
266 // 2 Operands: this is for things like mov that do not read a second input
268 assert(MI->getOperand(0).isRegister() &&
269 MI->getOperand(1).isRegister() &&
270 (MI->getNumOperands() == 2 ||
271 (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
272 && "Bad format for MRMDestReg!");
273 if (MI->getNumOperands() == 3 &&
274 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
277 O << getName(MI->getOpCode()) << " ";
278 printOp(O, MI->getOperand(0), RI);
280 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
285 case X86II::MRMSrcMem: {
286 // These instructions are the same as MRMSrcReg, but instead of having a
287 // register reference for the mod/rm field, it's a memory reference.
289 assert(MI->getOperand(0).isRegister() &&
290 (MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
291 (MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
293 && "Bad format for MRMDestReg!");
294 if (MI->getNumOperands() == 2+4 &&
295 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
298 O << getName(MI->getOpCode()) << " ";
299 printOp(O, MI->getOperand(0), RI);
300 O << ", " << sizePtr (Desc) << " ";
301 printMemReference(O, MI, MI->getNumOperands()-4, RI);
306 case X86II::MRMS0r: case X86II::MRMS1r:
307 case X86II::MRMS2r: case X86II::MRMS3r:
308 case X86II::MRMS4r: case X86II::MRMS5r:
309 case X86II::MRMS6r: case X86II::MRMS7r: {
310 // In this form, the following are valid formats:
312 // 2. cmp reg, immediate
313 // 2. shl rdest, rinput <implicit CL or 1>
314 // 3. sbb rdest, rinput, immediate [rdest = rinput]
316 assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
317 MI->getOperand(0).isRegister() && "Bad MRMSxR format!");
318 assert((MI->getNumOperands() != 2 ||
319 MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&&
320 "Bad MRMSxR format!");
321 assert((MI->getNumOperands() < 3 ||
322 (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) &&
323 "Bad MRMSxR format!");
325 if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() &&
326 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
329 O << getName(MI->getOpCode()) << " ";
330 printOp(O, MI->getOperand(0), RI);
331 if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
333 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
341 O << "\t\t\t-"; MI->print(O, TM); break;