1 //===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
3 // This file contains a printer that converts from our internal representation
4 // of LLVM code to a nice human readable form that is suitable for debuggging.
6 //===----------------------------------------------------------------------===//
9 #include "X86InstrInfo.h"
10 #include "llvm/Pass.h"
11 #include "llvm/Function.h"
12 #include "llvm/Target/TargetMachine.h"
13 #include "llvm/CodeGen/MachineFunction.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "Support/Statistic.h"
18 struct Printer : public FunctionPass {
22 Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {}
24 bool runOnFunction(Function &F);
28 /// createX86CodePrinterPass - Print out the specified machine code function to
29 /// the specified stream. This function should work regardless of whether or
30 /// not the function is in SSA form or not.
32 Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) {
33 return new Printer(TM, O);
37 /// runOnFunction - This uses the X86InstructionInfo::print method
38 /// to print assembly for each instruction.
39 bool Printer::runOnFunction (Function & F)
41 static unsigned bbnumber = 0;
42 MachineFunction & MF = MachineFunction::get (&F);
43 const MachineInstrInfo & MII = TM.getInstrInfo ();
45 // Print out labels for the function.
46 O << "\t.globl\t" << F.getName () << "\n";
47 O << "\t.type\t" << F.getName () << ", @function\n";
48 O << F.getName () << ":\n";
50 // Print out code for the function.
51 for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end ();
54 // Print a label for the basic block.
55 O << ".BB" << bbnumber++ << ":\n";
56 for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e =
57 bb_i->end (); i_i != i_e; ++i_i)
59 // Print the assembly for the instruction.
61 MII.print(*i_i, O, TM);
65 // We didn't modify anything.
69 static bool isReg(const MachineOperand &MO) {
70 return MO.getType() == MachineOperand::MO_VirtualRegister ||
71 MO.getType() == MachineOperand::MO_MachineRegister;
74 static bool isImmediate(const MachineOperand &MO) {
75 return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
76 MO.getType() == MachineOperand::MO_UnextendedImmed;
79 static bool isPCRelativeDisp(const MachineOperand &MO) {
80 return MO.getType() == MachineOperand::MO_PCRelativeDisp;
83 static bool isScale(const MachineOperand &MO) {
84 return isImmediate(MO) &&
85 (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
86 MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
89 static bool isMem(const MachineInstr *MI, unsigned Op) {
90 return Op+4 <= MI->getNumOperands() &&
91 isReg(MI->getOperand(Op )) && isScale(MI->getOperand(Op+1)) &&
92 isReg(MI->getOperand(Op+2)) && isImmediate(MI->getOperand(Op+3));
95 static void printOp(std::ostream &O, const MachineOperand &MO,
96 const MRegisterInfo &RI) {
97 switch (MO.getType()) {
98 case MachineOperand::MO_VirtualRegister:
99 if (Value *V = MO.getVRegValueOrNull()) {
100 O << "<" << V->getName() << ">";
103 case MachineOperand::MO_MachineRegister:
104 if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
105 O << RI.get(MO.getReg()).Name;
107 O << "%reg" << MO.getReg();
110 case MachineOperand::MO_SignExtendedImmed:
111 case MachineOperand::MO_UnextendedImmed:
112 O << (int)MO.getImmedValue();
114 case MachineOperand::MO_PCRelativeDisp:
115 O << "<" << MO.getVRegValue()->getName() << ">";
118 O << "<unknown op ty>"; return;
122 static const std::string sizePtr (const MachineInstrDescriptor &Desc) {
123 switch (Desc.TSFlags & X86II::MemArgMask) {
124 case X86II::MemArg8: return "BYTE PTR";
125 case X86II::MemArg16: return "WORD PTR";
126 case X86II::MemArg32: return "DWORD PTR";
127 case X86II::MemArg64: return "QWORD PTR";
128 case X86II::MemArg80: return "XWORD PTR";
129 case X86II::MemArg128: return "128BIT PTR"; // dunno what the real one is
130 default: return "<SIZE?> PTR"; // crack being smoked
134 static void printMemReference(std::ostream &O, const MachineInstr *MI,
135 unsigned Op, const MRegisterInfo &RI) {
136 assert(isMem(MI, Op) && "Invalid memory reference!");
137 const MachineOperand &BaseReg = MI->getOperand(Op);
138 const MachineOperand &Scale = MI->getOperand(Op+1);
139 const MachineOperand &IndexReg = MI->getOperand(Op+2);
140 const MachineOperand &Disp = MI->getOperand(Op+3);
143 bool NeedPlus = false;
144 if (BaseReg.getReg()) {
145 printOp(O, BaseReg, RI);
149 if (IndexReg.getReg()) {
150 if (NeedPlus) O << " + ";
151 if (IndexReg.getImmedValue() != 1)
152 O << IndexReg.getImmedValue() << "*";
153 printOp(O, IndexReg, RI);
157 if (Disp.getImmedValue()) {
158 if (NeedPlus) O << " + ";
159 printOp(O, Disp, RI);
164 // print - Print out an x86 instruction in intel syntax
165 void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
166 const TargetMachine &TM) const {
167 unsigned Opcode = MI->getOpcode();
168 const MachineInstrDescriptor &Desc = get(Opcode);
170 switch (Desc.TSFlags & X86II::FormMask) {
172 // The accepted forms of Raw instructions are:
173 // 1. nop - No operand required
174 // 2. jmp foo - PC relative displacement operand
176 assert(MI->getNumOperands() == 0 ||
177 (MI->getNumOperands() == 1 && isPCRelativeDisp(MI->getOperand(0))) &&
178 "Illegal raw instruction!");
179 O << getName(MI->getOpCode()) << " ";
181 if (MI->getNumOperands() == 1) {
182 printOp(O, MI->getOperand(0), RI);
187 case X86II::AddRegFrm: {
188 // There are currently two forms of acceptable AddRegFrm instructions.
189 // Either the instruction JUST takes a single register (like inc, dec, etc),
190 // or it takes a register and an immediate of the same size as the register
191 // (move immediate f.e.). Note that this immediate value might be stored as
192 // an LLVM value, to represent, for example, loading the address of a global
195 assert(isReg(MI->getOperand(0)) &&
196 (MI->getNumOperands() == 1 ||
197 (MI->getNumOperands() == 2 &&
198 (MI->getOperand(1).getVRegValueOrNull() ||
199 isImmediate(MI->getOperand(1))))) &&
200 "Illegal form for AddRegFrm instruction!");
202 unsigned Reg = MI->getOperand(0).getReg();
204 O << getName(MI->getOpCode()) << " ";
205 printOp(O, MI->getOperand(0), RI);
206 if (MI->getNumOperands() == 2) {
208 printOp(O, MI->getOperand(1), RI);
213 case X86II::MRMDestReg: {
214 // There are two acceptable forms of MRMDestReg instructions, those with 3
217 // 3 Operands: in this form, the first two registers (the destination, and
218 // the first operand) should be the same, post register allocation. The 3rd
219 // operand is an additional input. This should be for things like add
222 // 2 Operands: this is for things like mov that do not read a second input
224 assert(isReg(MI->getOperand(0)) &&
225 (MI->getNumOperands() == 2 ||
226 (MI->getNumOperands() == 3 && isReg(MI->getOperand(1)))) &&
227 isReg(MI->getOperand(MI->getNumOperands()-1))
228 && "Bad format for MRMDestReg!");
229 if (MI->getNumOperands() == 3 &&
230 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
233 O << getName(MI->getOpCode()) << " ";
234 printOp(O, MI->getOperand(0), RI);
236 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
241 case X86II::MRMDestMem: {
242 // These instructions are the same as MRMDestReg, but instead of having a
243 // register reference for the mod/rm field, it's a memory reference.
245 assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
246 isReg(MI->getOperand(4)) && "Bad format for MRMDestMem!");
248 O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " ";
249 printMemReference(O, MI, 0, RI);
251 printOp(O, MI->getOperand(4), RI);
256 case X86II::MRMSrcReg: {
257 // There is a two forms that are acceptable for MRMSrcReg instructions,
258 // those with 3 and 2 operands:
260 // 3 Operands: in this form, the last register (the second input) is the
261 // ModR/M input. The first two operands should be the same, post register
262 // allocation. This is for things like: add r32, r/m32
264 // 2 Operands: this is for things like mov that do not read a second input
266 assert(isReg(MI->getOperand(0)) &&
267 isReg(MI->getOperand(1)) &&
268 (MI->getNumOperands() == 2 ||
269 (MI->getNumOperands() == 3 && isReg(MI->getOperand(2))))
270 && "Bad format for MRMDestReg!");
271 if (MI->getNumOperands() == 3 &&
272 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
275 O << getName(MI->getOpCode()) << " ";
276 printOp(O, MI->getOperand(0), RI);
278 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
283 case X86II::MRMSrcMem: {
284 // These instructions are the same as MRMSrcReg, but instead of having a
285 // register reference for the mod/rm field, it's a memory reference.
287 assert(isReg(MI->getOperand(0)) &&
288 (MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
289 (MI->getNumOperands() == 2+4 && isReg(MI->getOperand(1)) &&
291 && "Bad format for MRMDestReg!");
292 if (MI->getNumOperands() == 2+4 &&
293 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
296 O << getName(MI->getOpCode()) << " ";
297 printOp(O, MI->getOperand(0), RI);
298 O << ", " << sizePtr (Desc) << " ";
299 printMemReference(O, MI, MI->getNumOperands()-4, RI);
304 case X86II::MRMS0r: case X86II::MRMS1r:
305 case X86II::MRMS2r: case X86II::MRMS3r:
306 case X86II::MRMS4r: case X86II::MRMS5r:
307 case X86II::MRMS6r: case X86II::MRMS7r: {
308 // In this form, the following are valid formats:
310 // 2. cmp reg, immediate
311 // 2. shl rdest, rinput <implicit CL or 1>
312 // 3. sbb rdest, rinput, immediate [rdest = rinput]
314 assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
315 isReg(MI->getOperand(0)) && "Bad MRMSxR format!");
316 assert((MI->getNumOperands() != 2 ||
317 isReg(MI->getOperand(1)) || isImmediate(MI->getOperand(1))) &&
318 "Bad MRMSxR format!");
319 assert((MI->getNumOperands() < 3 ||
320 (isReg(MI->getOperand(1)) && isImmediate(MI->getOperand(2)))) &&
321 "Bad MRMSxR format!");
323 if (MI->getNumOperands() > 1 && isReg(MI->getOperand(1)) &&
324 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
327 O << getName(MI->getOpCode()) << " ";
328 printOp(O, MI->getOperand(0), RI);
329 if (isImmediate(MI->getOperand(MI->getNumOperands()-1))) {
331 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
339 O << "\t\t\t-"; MI->print(O, TM); break;