1 //===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
3 // This file contains a printer that converts from our internal representation
4 // of LLVM code to a nice human readable form that is suitable for debuggging.
6 //===----------------------------------------------------------------------===//
9 #include "X86InstrInfo.h"
10 #include "llvm/Function.h"
11 #include "llvm/Target/TargetMachine.h"
12 #include "llvm/CodeGen/MachineFunctionPass.h"
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "Support/Statistic.h"
17 struct Printer : public MachineFunctionPass {
20 Printer(std::ostream &o) : O(o) {}
22 virtual const char *getPassName() const {
23 return "X86 Assembly Printer";
26 bool runOnMachineFunction(MachineFunction &F);
30 /// createX86CodePrinterPass - Print out the specified machine code function to
31 /// the specified stream. This function should work regardless of whether or
32 /// not the function is in SSA form or not.
34 Pass *createX86CodePrinterPass(std::ostream &O) {
35 return new Printer(O);
39 /// runOnFunction - This uses the X86InstructionInfo::print method
40 /// to print assembly for each instruction.
41 bool Printer::runOnMachineFunction(MachineFunction &MF) {
42 static unsigned BBNumber = 0;
43 const TargetMachine &TM = MF.getTarget();
44 const MachineInstrInfo &MII = TM.getInstrInfo();
46 // Print out labels for the function.
47 O << "\t.globl\t" << MF.getFunction()->getName() << "\n";
48 O << "\t.type\t" << MF.getFunction()->getName() << ", @function\n";
49 O << MF.getFunction()->getName() << ":\n";
51 // Print out code for the function.
52 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
54 // Print a label for the basic block.
55 O << ".BB" << BBNumber++ << ":\n";
56 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
58 // Print the assembly for the instruction.
60 MII.print(*II, O, TM);
64 // We didn't modify anything.
68 static bool isScale(const MachineOperand &MO) {
69 return MO.isImmediate() &&
70 (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
71 MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
74 static bool isMem(const MachineInstr *MI, unsigned Op) {
75 return Op+4 <= MI->getNumOperands() &&
76 MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
77 MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
80 static void printOp(std::ostream &O, const MachineOperand &MO,
81 const MRegisterInfo &RI) {
82 switch (MO.getType()) {
83 case MachineOperand::MO_VirtualRegister:
84 if (Value *V = MO.getVRegValueOrNull()) {
85 O << "<" << V->getName() << ">";
88 case MachineOperand::MO_MachineRegister:
89 if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
90 O << RI.get(MO.getReg()).Name;
92 O << "%reg" << MO.getReg();
95 case MachineOperand::MO_SignExtendedImmed:
96 case MachineOperand::MO_UnextendedImmed:
97 O << (int)MO.getImmedValue();
99 case MachineOperand::MO_PCRelativeDisp:
100 O << "<" << MO.getVRegValue()->getName() << ">";
103 O << "<unknown op ty>"; return;
107 static const std::string sizePtr(const MachineInstrDescriptor &Desc) {
108 switch (Desc.TSFlags & X86II::ArgMask) {
109 default: assert(0 && "Unknown arg size!");
110 case X86II::Arg8: return "BYTE PTR";
111 case X86II::Arg16: return "WORD PTR";
112 case X86II::Arg32: return "DWORD PTR";
113 case X86II::ArgF32: return "DWORD PTR";
114 case X86II::ArgF64: return "QWORD PTR";
115 case X86II::ArgF80: return "XWORD PTR";
119 static void printMemReference(std::ostream &O, const MachineInstr *MI,
120 unsigned Op, const MRegisterInfo &RI) {
121 assert(isMem(MI, Op) && "Invalid memory reference!");
122 const MachineOperand &BaseReg = MI->getOperand(Op);
123 int ScaleVal = MI->getOperand(Op+1).getImmedValue();
124 const MachineOperand &IndexReg = MI->getOperand(Op+2);
125 int DispVal = MI->getOperand(Op+3).getImmedValue();
128 bool NeedPlus = false;
129 if (BaseReg.getReg()) {
130 printOp(O, BaseReg, RI);
134 if (IndexReg.getReg()) {
135 if (NeedPlus) O << " + ";
137 O << ScaleVal << "*";
138 printOp(O, IndexReg, RI);
155 // print - Print out an x86 instruction in intel syntax
156 void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
157 const TargetMachine &TM) const {
158 unsigned Opcode = MI->getOpcode();
159 const MachineInstrDescriptor &Desc = get(Opcode);
161 switch (Desc.TSFlags & X86II::FormMask) {
163 if (Opcode == X86::PHI) {
164 printOp(O, MI->getOperand(0), RI);
166 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
167 if (i != 1) O << ", ";
169 printOp(O, MI->getOperand(i), RI);
171 printOp(O, MI->getOperand(i+1), RI);
176 if (MI->getNumOperands() && MI->getOperand(0).opIsDef()) {
177 printOp(O, MI->getOperand(0), RI);
181 O << getName(MI->getOpcode());
183 for (unsigned e = MI->getNumOperands(); i != e; ++i) {
185 if (MI->getOperand(i).opIsDef()) O << "*";
186 printOp(O, MI->getOperand(i), RI);
187 if (MI->getOperand(i).opIsDef()) O << "*";
194 // The accepted forms of Raw instructions are:
195 // 1. nop - No operand required
196 // 2. jmp foo - PC relative displacement operand
198 assert(MI->getNumOperands() == 0 ||
199 (MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&&
200 "Illegal raw instruction!");
201 O << getName(MI->getOpcode()) << " ";
203 if (MI->getNumOperands() == 1) {
204 printOp(O, MI->getOperand(0), RI);
209 case X86II::AddRegFrm: {
210 // There are currently two forms of acceptable AddRegFrm instructions.
211 // Either the instruction JUST takes a single register (like inc, dec, etc),
212 // or it takes a register and an immediate of the same size as the register
213 // (move immediate f.e.). Note that this immediate value might be stored as
214 // an LLVM value, to represent, for example, loading the address of a global
215 // into a register. The initial register might be duplicated if this is a
216 // M_2_ADDR_REG instruction
218 assert(MI->getOperand(0).isRegister() &&
219 (MI->getNumOperands() == 1 ||
220 (MI->getNumOperands() == 2 &&
221 (MI->getOperand(1).getVRegValueOrNull() ||
222 MI->getOperand(1).isImmediate() ||
223 MI->getOperand(1).isRegister()))) &&
224 "Illegal form for AddRegFrm instruction!");
226 unsigned Reg = MI->getOperand(0).getReg();
228 O << getName(MI->getOpCode()) << " ";
229 printOp(O, MI->getOperand(0), RI);
230 if (MI->getNumOperands() == 2 && !MI->getOperand(1).isRegister()) {
232 printOp(O, MI->getOperand(1), RI);
237 case X86II::MRMDestReg: {
238 // There are two acceptable forms of MRMDestReg instructions, those with 3
241 // 3 Operands: in this form, the first two registers (the destination, and
242 // the first operand) should be the same, post register allocation. The 3rd
243 // operand is an additional input. This should be for things like add
246 // 2 Operands: this is for things like mov that do not read a second input
248 assert(MI->getOperand(0).isRegister() &&
249 (MI->getNumOperands() == 2 ||
250 (MI->getNumOperands() == 3 && MI->getOperand(1).isRegister())) &&
251 MI->getOperand(MI->getNumOperands()-1).isRegister()
252 && "Bad format for MRMDestReg!");
253 if (MI->getNumOperands() == 3 &&
254 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
257 O << getName(MI->getOpCode()) << " ";
258 printOp(O, MI->getOperand(0), RI);
260 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
265 case X86II::MRMDestMem: {
266 // These instructions are the same as MRMDestReg, but instead of having a
267 // register reference for the mod/rm field, it's a memory reference.
269 assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
270 MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
272 O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " ";
273 printMemReference(O, MI, 0, RI);
275 printOp(O, MI->getOperand(4), RI);
280 case X86II::MRMSrcReg: {
281 // There is a two forms that are acceptable for MRMSrcReg instructions,
282 // those with 3 and 2 operands:
284 // 3 Operands: in this form, the last register (the second input) is the
285 // ModR/M input. The first two operands should be the same, post register
286 // allocation. This is for things like: add r32, r/m32
288 // 2 Operands: this is for things like mov that do not read a second input
290 assert(MI->getOperand(0).isRegister() &&
291 MI->getOperand(1).isRegister() &&
292 (MI->getNumOperands() == 2 ||
293 (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
294 && "Bad format for MRMDestReg!");
295 if (MI->getNumOperands() == 3 &&
296 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
299 O << getName(MI->getOpCode()) << " ";
300 printOp(O, MI->getOperand(0), RI);
302 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
307 case X86II::MRMSrcMem: {
308 // These instructions are the same as MRMSrcReg, but instead of having a
309 // register reference for the mod/rm field, it's a memory reference.
311 assert(MI->getOperand(0).isRegister() &&
312 (MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
313 (MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
315 && "Bad format for MRMDestReg!");
316 if (MI->getNumOperands() == 2+4 &&
317 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
320 O << getName(MI->getOpCode()) << " ";
321 printOp(O, MI->getOperand(0), RI);
322 O << ", " << sizePtr (Desc) << " ";
323 printMemReference(O, MI, MI->getNumOperands()-4, RI);
328 case X86II::MRMS0r: case X86II::MRMS1r:
329 case X86II::MRMS2r: case X86II::MRMS3r:
330 case X86II::MRMS4r: case X86II::MRMS5r:
331 case X86II::MRMS6r: case X86II::MRMS7r: {
332 // In this form, the following are valid formats:
334 // 2. cmp reg, immediate
335 // 2. shl rdest, rinput <implicit CL or 1>
336 // 3. sbb rdest, rinput, immediate [rdest = rinput]
338 assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
339 MI->getOperand(0).isRegister() && "Bad MRMSxR format!");
340 assert((MI->getNumOperands() != 2 ||
341 MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&&
342 "Bad MRMSxR format!");
343 assert((MI->getNumOperands() < 3 ||
344 (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) &&
345 "Bad MRMSxR format!");
347 if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() &&
348 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
351 O << getName(MI->getOpCode()) << " ";
352 printOp(O, MI->getOperand(0), RI);
353 if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
355 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
363 O << "\t\t\t-"; MI->print(O, TM); break;