1 //===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
3 // This file contains a printer that converts from our internal representation
4 // of LLVM code to a nice human readable form that is suitable for debuggging.
6 //===----------------------------------------------------------------------===//
9 #include "X86InstrInfo.h"
10 #include "llvm/Pass.h"
11 #include "llvm/Function.h"
12 #include "llvm/Target/TargetMachine.h"
13 #include "llvm/CodeGen/MachineFunction.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "Support/Statistic.h"
18 struct Printer : public FunctionPass {
22 Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {}
24 bool runOnFunction(Function &F);
28 /// createX86CodePrinterPass - Print out the specified machine code function to
29 /// the specified stream. This function should work regardless of whether or
30 /// not the function is in SSA form or not.
32 Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) {
33 return new Printer(TM, O);
37 /// runOnFunction - This uses the X86InstructionInfo::print method
38 /// to print assembly for each instruction.
39 bool Printer::runOnFunction (Function & F)
41 static unsigned bbnumber = 0;
42 MachineFunction & MF = MachineFunction::get (&F);
43 const MachineInstrInfo & MII = TM.getInstrInfo ();
45 O << "; x86 printing only sorta implemented so far!\n";
47 // Print out labels for the function.
48 O << "\t.globl\t" << F.getName () << "\n";
49 O << "\t.type\t" << F.getName () << ", @function\n";
50 O << F.getName () << ":\n";
52 // Print out code for the function.
53 for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end ();
56 // Print a label for the basic block.
57 O << ".BB" << bbnumber++ << ":\n";
58 for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e =
59 bb_i->end (); i_i != i_e; ++i_i)
61 // Print the assembly for the instruction.
63 MII.print(*i_i, O, TM);
67 // We didn't modify anything.
71 static void printOp(std::ostream &O, const MachineOperand &MO,
72 const MRegisterInfo &RI) {
73 switch (MO.getType()) {
74 case MachineOperand::MO_VirtualRegister:
75 case MachineOperand::MO_MachineRegister:
76 if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
77 O << RI.get(MO.getReg()).Name;
79 O << "%reg" << MO.getReg();
82 case MachineOperand::MO_SignExtendedImmed:
83 case MachineOperand::MO_UnextendedImmed:
84 O << (int)MO.getImmedValue();
87 O << "<unknown op ty>"; return;
91 static inline void toHexDigit(std::ostream &O, unsigned char V) {
93 O << (char)('A'+V-10);
98 static std::ostream &toHex(std::ostream &O, unsigned char V) {
99 toHexDigit(O, V >> 4);
100 toHexDigit(O, V & 0xF);
104 static std::ostream &emitConstant(std::ostream &O, unsigned Val, unsigned Size){
105 // Output the constant in little endian byte order...
106 for (unsigned i = 0; i != Size; ++i) {
107 toHex(O, Val) << " ";
114 static bool isReg(const MachineOperand &MO) {
115 return MO.getType() == MachineOperand::MO_VirtualRegister ||
116 MO.getType() == MachineOperand::MO_MachineRegister;
119 static bool isImmediate(const MachineOperand &MO) {
120 return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
121 MO.getType() == MachineOperand::MO_UnextendedImmed;
125 // getX86RegNum - This function maps LLVM register identifiers to their X86
126 // specific numbering, which is used in various places encoding instructions.
128 static unsigned getX86RegNum(unsigned RegNo) {
130 case X86::EAX: case X86::AX: case X86::AL: return 0;
131 case X86::ECX: case X86::CX: case X86::CL: return 1;
132 case X86::EDX: case X86::DX: case X86::DL: return 2;
133 case X86::EBX: case X86::BX: case X86::BL: return 3;
134 case X86::ESP: case X86::SP: case X86::AH: return 4;
135 case X86::EBP: case X86::BP: case X86::CH: return 5;
136 case X86::ESI: case X86::SI: case X86::DH: return 6;
137 case X86::EDI: case X86::DI: case X86::BH: return 7;
139 assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
140 "Unknown physical register!");
141 DEBUG(std::cerr << "Register allocator hasn't allocated " << RegNo
142 << " correctly yet!\n");
147 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
149 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
150 return RM | (RegOpcode << 3) | (Mod << 6);
153 static unsigned char regModRMByte(unsigned ModRMReg, unsigned RegOpcodeField) {
154 return ModRMByte(3, RegOpcodeField, getX86RegNum(ModRMReg));
158 // print - Print out an x86 instruction in intel syntax
159 void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
160 const TargetMachine &TM) const {
161 unsigned Opcode = MI->getOpcode();
162 const MachineInstrDescriptor &Desc = get(Opcode);
164 // Print instruction prefixes if neccesary
166 if (Desc.TSFlags & X86II::OpSize) O << "66 "; // Operand size...
167 if (Desc.TSFlags & X86II::TB) O << "0F "; // Two-byte opcode prefix
169 switch (Desc.TSFlags & X86II::FormMask) {
170 case X86II::OtherFrm:
172 O << "-"; MI->print(O, TM);
175 toHex(O, getBaseOpcodeFor(Opcode));
177 O << getName(MI->getOpCode()) << " ";
179 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
181 printOp(O, MI->getOperand(i), RI);
187 case X86II::AddRegFrm: {
188 // There are currently two forms of acceptable AddRegFrm instructions.
189 // Either the instruction JUST takes a single register (like inc, dec, etc),
190 // or it takes a register and an immediate of the same size as the register
191 // (move immediate f.e.).
193 assert(isReg(MI->getOperand(0)) &&
194 (MI->getNumOperands() == 1 ||
195 (MI->getNumOperands() == 2 && isImmediate(MI->getOperand(1)))) &&
196 "Illegal form for AddRegFrm instruction!");
198 unsigned Reg = MI->getOperand(0).getReg();
199 toHex(O, getBaseOpcodeFor(Opcode) + getX86RegNum(Reg)) << " ";
201 if (MI->getNumOperands() == 2) {
203 emitConstant(O, MI->getOperand(1).getImmedValue(), Size);
207 O << getName(MI->getOpCode()) << " ";
208 printOp(O, MI->getOperand(0), RI);
209 if (MI->getNumOperands() == 2) {
211 printOp(O, MI->getOperand(1), RI);
216 case X86II::MRMDestReg: {
217 // There are two acceptable forms of MRMDestReg instructions, those with 3
220 // 3 Operands: in this form, the first two registers (the destination, and
221 // the first operand) should be the same, post register allocation. The 3rd
222 // operand is an additional input. This should be for things like add
225 // 2 Operands: this is for things like mov that do not read a second input
227 assert(isReg(MI->getOperand(0)) &&
228 (MI->getNumOperands() == 2 ||
229 (MI->getNumOperands() == 3 && isReg(MI->getOperand(1)))) &&
230 isReg(MI->getOperand(MI->getNumOperands()-1))
231 && "Bad format for MRMDestReg!");
232 if (MI->getNumOperands() == 3 &&
233 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
236 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
237 unsigned ModRMReg = MI->getOperand(0).getReg();
238 unsigned ExtraReg = MI->getOperand(MI->getNumOperands()-1).getReg();
239 toHex(O, regModRMByte(ModRMReg, getX86RegNum(ExtraReg)));
242 O << getName(MI->getOpCode()) << " ";
243 printOp(O, MI->getOperand(0), RI);
245 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
249 case X86II::MRMSrcReg: {
250 // There is a two forms that are acceptable for MRMSrcReg instructions,
251 // those with 3 and 2 operands:
253 // 3 Operands: in this form, the last register (the second input) is the
254 // ModR/M input. The first two operands should be the same, post register
255 // allocation. This is for things like: add r32, r/m32
257 // 2 Operands: this is for things like mov that do not read a second input
259 assert(isReg(MI->getOperand(0)) &&
260 isReg(MI->getOperand(1)) &&
261 (MI->getNumOperands() == 2 ||
262 (MI->getNumOperands() == 3 && isReg(MI->getOperand(2))))
263 && "Bad format for MRMDestReg!");
264 if (MI->getNumOperands() == 3 &&
265 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
268 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
269 unsigned ModRMReg = MI->getOperand(MI->getNumOperands()-1).getReg();
270 unsigned ExtraReg = MI->getOperand(0).getReg();
271 toHex(O, regModRMByte(ModRMReg, getX86RegNum(ExtraReg)));
274 O << getName(MI->getOpCode()) << " ";
275 printOp(O, MI->getOperand(0), RI);
277 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
282 case X86II::MRMS0r: case X86II::MRMS1r:
283 case X86II::MRMS2r: case X86II::MRMS3r:
284 case X86II::MRMS4r: case X86II::MRMS5r:
285 case X86II::MRMS6r: case X86II::MRMS7r: {
286 unsigned ExtraField = (Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r;
288 // In this form, the following are valid formats:
290 // 2. shl rdest, rinput <implicit CL or 1>
291 // 3. sbb rdest, rinput, immediate [rdest = rinput]
293 assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
294 isReg(MI->getOperand(0)) && "Bad MRMSxR format!");
295 assert((MI->getNumOperands() < 2 || isReg(MI->getOperand(1))) &&
296 "Bad MRMSxR format!");
297 assert((MI->getNumOperands() < 3 || isImmediate(MI->getOperand(2))) &&
298 "Bad MRMSxR format!");
300 if (MI->getNumOperands() > 1 &&
301 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
304 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
305 toHex(O, regModRMByte(MI->getOperand(0).getReg(), ExtraField));
307 if (MI->getNumOperands() == 3) {
309 emitConstant(O, MI->getOperand(1).getImmedValue(), Size);
313 O << getName(MI->getOpCode()) << " ";
314 printOp(O, MI->getOperand(0), RI);
315 if (MI->getNumOperands() == 3) {
317 printOp(O, MI->getOperand(2), RI);
324 case X86II::MRMDestMem:
325 case X86II::MRMSrcMem:
327 O << "\t\t\t-"; MI->print(O, TM); break;