1 //===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
3 // This file contains a printer that converts from our internal representation
4 // of LLVM code to a nice human readable form that is suitable for debuggging.
6 //===----------------------------------------------------------------------===//
9 #include "X86InstrInfo.h"
10 #include "llvm/Pass.h"
11 #include "llvm/Function.h"
12 #include "llvm/Target/TargetMachine.h"
13 #include "llvm/CodeGen/MachineFunction.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "Support/Statistic.h"
18 struct Printer : public FunctionPass {
22 Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {}
24 bool runOnFunction(Function &F);
28 /// createX86CodePrinterPass - Print out the specified machine code function to
29 /// the specified stream. This function should work regardless of whether or
30 /// not the function is in SSA form or not.
32 Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) {
33 return new Printer(TM, O);
37 /// runOnFunction - This uses the X86InstructionInfo::print method
38 /// to print assembly for each instruction.
39 bool Printer::runOnFunction (Function & F)
41 static unsigned bbnumber = 0;
42 MachineFunction & MF = MachineFunction::get (&F);
43 const MachineInstrInfo & MII = TM.getInstrInfo ();
45 // Print out labels for the function.
46 O << "\t.globl\t" << F.getName () << "\n";
47 O << "\t.type\t" << F.getName () << ", @function\n";
48 O << F.getName () << ":\n";
50 // Print out code for the function.
51 for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end ();
54 // Print a label for the basic block.
55 O << ".BB" << bbnumber++ << ":\n";
56 for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e =
57 bb_i->end (); i_i != i_e; ++i_i)
59 // Print the assembly for the instruction.
61 MII.print(*i_i, O, TM);
65 // We didn't modify anything.
69 static bool isReg(const MachineOperand &MO) {
70 return MO.getType() == MachineOperand::MO_VirtualRegister ||
71 MO.getType() == MachineOperand::MO_MachineRegister;
74 static bool isImmediate(const MachineOperand &MO) {
75 return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
76 MO.getType() == MachineOperand::MO_UnextendedImmed;
79 static bool isPCRelativeDisp(const MachineOperand &MO) {
80 return MO.getType() == MachineOperand::MO_PCRelativeDisp;
83 static bool isScale(const MachineOperand &MO) {
84 return isImmediate(MO) &&
85 (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
86 MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
89 static bool isMem(const MachineInstr *MI, unsigned Op) {
90 return Op+4 <= MI->getNumOperands() &&
91 isReg(MI->getOperand(Op )) && isScale(MI->getOperand(Op+1)) &&
92 isReg(MI->getOperand(Op+2)) && isImmediate(MI->getOperand(Op+3));
95 static void printOp(std::ostream &O, const MachineOperand &MO,
96 const MRegisterInfo &RI) {
97 switch (MO.getType()) {
98 case MachineOperand::MO_VirtualRegister:
99 case MachineOperand::MO_MachineRegister:
100 if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
101 O << RI.get(MO.getReg()).Name;
103 O << "%reg" << MO.getReg();
106 case MachineOperand::MO_SignExtendedImmed:
107 case MachineOperand::MO_UnextendedImmed:
108 O << (int)MO.getImmedValue();
110 case MachineOperand::MO_PCRelativeDisp:
111 O << "< " << MO.getVRegValue()->getName() << ">";
114 O << "<unknown op ty>"; return;
118 static void printMemReference(std::ostream &O, const MachineInstr *MI,
119 unsigned Op, const MRegisterInfo &RI) {
120 assert(isMem(MI, Op) && "Invalid memory reference!");
121 const MachineOperand &BaseReg = MI->getOperand(Op);
122 const MachineOperand &Scale = MI->getOperand(Op+1);
123 const MachineOperand &IndexReg = MI->getOperand(Op+2);
124 const MachineOperand &Disp = MI->getOperand(Op+3);
127 bool NeedPlus = false;
128 if (BaseReg.getReg()) {
129 printOp(O, BaseReg, RI);
133 if (IndexReg.getReg()) {
134 if (NeedPlus) O << " + ";
135 if (IndexReg.getImmedValue() != 1)
136 O << IndexReg.getImmedValue() << "*";
137 printOp(O, IndexReg, RI);
141 if (Disp.getImmedValue()) {
142 if (NeedPlus) O << " + ";
143 printOp(O, Disp, RI);
148 static inline void toHexDigit(std::ostream &O, unsigned char V) {
150 O << (char)('A'+V-10);
155 static std::ostream &toHex(std::ostream &O, unsigned char V) {
156 toHexDigit(O, V >> 4);
157 toHexDigit(O, V & 0xF);
161 static std::ostream &emitConstant(std::ostream &O, unsigned Val, unsigned Size){
162 // Output the constant in little endian byte order...
163 for (unsigned i = 0; i != Size; ++i) {
164 toHex(O, Val) << " ";
170 namespace N86 { // Native X86 Register numbers...
172 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
177 // getX86RegNum - This function maps LLVM register identifiers to their X86
178 // specific numbering, which is used in various places encoding instructions.
180 static unsigned getX86RegNum(unsigned RegNo) {
182 case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
183 case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
184 case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
185 case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
186 case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
187 case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
188 case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
189 case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
191 assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
192 "Unknown physical register!");
193 DEBUG(std::cerr << "Register allocator hasn't allocated " << RegNo
194 << " correctly yet!\n");
199 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
201 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
202 return RM | (RegOpcode << 3) | (Mod << 6);
205 static void emitRegModRMByte(std::ostream &O, unsigned ModRMReg,
206 unsigned RegOpcodeField) {
207 toHex(O, ModRMByte(3, RegOpcodeField, getX86RegNum(ModRMReg))) << " ";
210 inline static void emitSIBByte(std::ostream &O, unsigned SS, unsigned Index,
212 // SIB byte is in the same format as the ModRMByte...
213 toHex(O, ModRMByte(SS, Index, Base));
216 static bool isDisp8(int Value) {
217 return Value == (signed char)Value;
220 static void emitMemModRMByte(std::ostream &O, const MachineInstr *MI,
221 unsigned Op, unsigned RegOpcodeField) {
222 assert(isMem(MI, Op) && "Invalid memory reference!");
223 const MachineOperand &BaseReg = MI->getOperand(Op);
224 const MachineOperand &Scale = MI->getOperand(Op+1);
225 const MachineOperand &IndexReg = MI->getOperand(Op+2);
226 const MachineOperand &Disp = MI->getOperand(Op+3);
228 // Is a SIB byte needed?
229 if (IndexReg.getReg() == 0 && BaseReg.getReg() != X86::ESP) {
230 if (BaseReg.getReg() == 0) { // Just a displacement?
231 // Emit special case [disp32] encoding
232 toHex(O, ModRMByte(0, RegOpcodeField, 5));
233 emitConstant(O, Disp.getImmedValue(), 4);
235 unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
236 if (Disp.getImmedValue() == 0 && BaseRegNo != N86::EBP) {
237 // Emit simple indirect register encoding... [EAX] f.e.
238 toHex(O, ModRMByte(0, RegOpcodeField, BaseRegNo));
239 } else if (isDisp8(Disp.getImmedValue())) {
240 // Emit the disp8 encoding... [REG+disp8]
241 toHex(O, ModRMByte(1, RegOpcodeField, BaseRegNo));
242 emitConstant(O, Disp.getImmedValue(), 1);
244 // Emit the most general non-SIB encoding: [REG+disp32]
245 toHex(O, ModRMByte(1, RegOpcodeField, BaseRegNo));
246 emitConstant(O, Disp.getImmedValue(), 4);
250 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
251 assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
253 bool ForceDisp32 = false;
254 if (BaseReg.getReg() == 0) {
255 // If there is no base register, we emit the special case SIB byte with
256 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
257 toHex(O, ModRMByte(0, RegOpcodeField, 4));
259 } else if (Disp.getImmedValue() == 0) {
260 // Emit no displacement ModR/M byte
261 toHex(O, ModRMByte(0, RegOpcodeField, 4));
262 } else if (isDisp8(Disp.getImmedValue())) {
263 // Emit the disp8 encoding...
264 toHex(O, ModRMByte(1, RegOpcodeField, 4));
266 // Emit the normal disp32 encoding...
267 toHex(O, ModRMByte(2, RegOpcodeField, 4));
270 // Calculate what the SS field value should be...
271 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
272 unsigned SS = SSTable[Scale.getImmedValue()];
274 if (BaseReg.getReg() == 0) {
275 // Handle the SIB byte for the case where there is no base. The
276 // displacement has already been output.
277 assert(IndexReg.getReg() && "Index register must be specified!");
278 emitSIBByte(O, SS, getX86RegNum(IndexReg.getReg()), 5);
280 unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
281 unsigned IndexRegNo = getX86RegNum(IndexReg.getReg());
282 emitSIBByte(O, SS, IndexRegNo, BaseRegNo);
285 // Do we need to output a displacement?
286 if (Disp.getImmedValue() != 0 || ForceDisp32) {
287 if (!ForceDisp32 && isDisp8(Disp.getImmedValue()))
288 emitConstant(O, Disp.getImmedValue(), 1);
290 emitConstant(O, Disp.getImmedValue(), 4);
296 // print - Print out an x86 instruction in intel syntax
297 void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
298 const TargetMachine &TM) const {
299 unsigned Opcode = MI->getOpcode();
300 const MachineInstrDescriptor &Desc = get(Opcode);
302 // Print instruction prefixes if neccesary
303 if (Desc.TSFlags & X86II::OpSize) O << "66 "; // Operand size...
304 if (Desc.TSFlags & X86II::TB) O << "0F "; // Two-byte opcode prefix
306 switch (Desc.TSFlags & X86II::FormMask) {
308 // The accepted forms of Raw instructions are:
309 // 1. nop - No operand required
310 // 2. jmp foo - PC relative displacement operand
312 assert(MI->getNumOperands() == 0 ||
313 (MI->getNumOperands() == 1 && isPCRelativeDisp(MI->getOperand(0))) &&
314 "Illegal raw instruction!");
315 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
317 if (MI->getNumOperands() == 1) {
318 Value *V = MI->getOperand(0).getVRegValue();
319 emitConstant(O, 0, 4);
323 O << getName(MI->getOpCode()) << " ";
325 if (MI->getNumOperands() == 1) {
326 printOp(O, MI->getOperand(0), RI);
331 case X86II::AddRegFrm: {
332 // There are currently two forms of acceptable AddRegFrm instructions.
333 // Either the instruction JUST takes a single register (like inc, dec, etc),
334 // or it takes a register and an immediate of the same size as the register
335 // (move immediate f.e.).
337 assert(isReg(MI->getOperand(0)) &&
338 (MI->getNumOperands() == 1 ||
339 (MI->getNumOperands() == 2 && isImmediate(MI->getOperand(1)))) &&
340 "Illegal form for AddRegFrm instruction!");
342 unsigned Reg = MI->getOperand(0).getReg();
343 toHex(O, getBaseOpcodeFor(Opcode) + getX86RegNum(Reg)) << " ";
345 if (MI->getNumOperands() == 2) {
347 emitConstant(O, MI->getOperand(1).getImmedValue(), Size);
351 O << getName(MI->getOpCode()) << " ";
352 printOp(O, MI->getOperand(0), RI);
353 if (MI->getNumOperands() == 2) {
355 printOp(O, MI->getOperand(1), RI);
360 case X86II::MRMDestReg: {
361 // There are two acceptable forms of MRMDestReg instructions, those with 3
364 // 3 Operands: in this form, the first two registers (the destination, and
365 // the first operand) should be the same, post register allocation. The 3rd
366 // operand is an additional input. This should be for things like add
369 // 2 Operands: this is for things like mov that do not read a second input
371 assert(isReg(MI->getOperand(0)) &&
372 (MI->getNumOperands() == 2 ||
373 (MI->getNumOperands() == 3 && isReg(MI->getOperand(1)))) &&
374 isReg(MI->getOperand(MI->getNumOperands()-1))
375 && "Bad format for MRMDestReg!");
376 if (MI->getNumOperands() == 3 &&
377 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
380 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
381 unsigned ModRMReg = MI->getOperand(0).getReg();
382 unsigned ExtraReg = MI->getOperand(MI->getNumOperands()-1).getReg();
383 emitRegModRMByte(O, ModRMReg, getX86RegNum(ExtraReg));
386 O << getName(MI->getOpCode()) << " ";
387 printOp(O, MI->getOperand(0), RI);
389 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
394 case X86II::MRMDestMem: {
395 // These instructions are the same as MRMDestReg, but instead of having a
396 // register reference for the mod/rm field, it's a memory reference.
398 assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
399 isReg(MI->getOperand(4)) && "Bad format for MRMDestMem!");
400 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
401 emitMemModRMByte(O, MI, 0, getX86RegNum(MI->getOperand(4).getReg()));
404 O << getName(MI->getOpCode()) << " <SIZE> PTR ";
405 printMemReference(O, MI, 0, RI);
407 printOp(O, MI->getOperand(4), RI);
412 case X86II::MRMSrcReg: {
413 // There is a two forms that are acceptable for MRMSrcReg instructions,
414 // those with 3 and 2 operands:
416 // 3 Operands: in this form, the last register (the second input) is the
417 // ModR/M input. The first two operands should be the same, post register
418 // allocation. This is for things like: add r32, r/m32
420 // 2 Operands: this is for things like mov that do not read a second input
422 assert(isReg(MI->getOperand(0)) &&
423 isReg(MI->getOperand(1)) &&
424 (MI->getNumOperands() == 2 ||
425 (MI->getNumOperands() == 3 && isReg(MI->getOperand(2))))
426 && "Bad format for MRMDestReg!");
427 if (MI->getNumOperands() == 3 &&
428 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
431 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
432 unsigned ModRMReg = MI->getOperand(MI->getNumOperands()-1).getReg();
433 unsigned ExtraReg = MI->getOperand(0).getReg();
434 emitRegModRMByte(O, ModRMReg, getX86RegNum(ExtraReg));
437 O << getName(MI->getOpCode()) << " ";
438 printOp(O, MI->getOperand(0), RI);
440 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
445 case X86II::MRMSrcMem: {
446 // These instructions are the same as MRMSrcReg, but instead of having a
447 // register reference for the mod/rm field, it's a memory reference.
449 assert(isReg(MI->getOperand(0)) &&
450 (MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
451 (MI->getNumOperands() == 2+4 && isReg(MI->getOperand(1)) &&
453 && "Bad format for MRMDestReg!");
454 if (MI->getNumOperands() == 2+4 &&
455 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
458 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
459 unsigned ExtraReg = MI->getOperand(0).getReg();
460 emitMemModRMByte(O, MI, MI->getNumOperands()-4, getX86RegNum(ExtraReg));
463 O << getName(MI->getOpCode()) << " ";
464 printOp(O, MI->getOperand(0), RI);
465 O << ", <SIZE> PTR ";
466 printMemReference(O, MI, MI->getNumOperands()-4, RI);
471 case X86II::MRMS0r: case X86II::MRMS1r:
472 case X86II::MRMS2r: case X86II::MRMS3r:
473 case X86II::MRMS4r: case X86II::MRMS5r:
474 case X86II::MRMS6r: case X86II::MRMS7r: {
475 // In this form, the following are valid formats:
477 // 2. cmp reg, immediate
478 // 2. shl rdest, rinput <implicit CL or 1>
479 // 3. sbb rdest, rinput, immediate [rdest = rinput]
481 assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
482 isReg(MI->getOperand(0)) && "Bad MRMSxR format!");
483 assert((MI->getNumOperands() != 2 ||
484 isReg(MI->getOperand(1)) || isImmediate(MI->getOperand(1))) &&
485 "Bad MRMSxR format!");
486 assert((MI->getNumOperands() < 3 ||
487 (isReg(MI->getOperand(1)) && isImmediate(MI->getOperand(2)))) &&
488 "Bad MRMSxR format!");
490 if (MI->getNumOperands() > 1 && isReg(MI->getOperand(1)) &&
491 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
494 toHex(O, getBaseOpcodeFor(Opcode)) << " ";
495 unsigned ExtraField = (Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r;
496 emitRegModRMByte(O, MI->getOperand(0).getReg(), ExtraField);
498 if (isImmediate(MI->getOperand(MI->getNumOperands()-1))) {
500 emitConstant(O, MI->getOperand(MI->getNumOperands()-1).getImmedValue(),
505 O << getName(MI->getOpCode()) << " ";
506 printOp(O, MI->getOperand(0), RI);
507 if (isImmediate(MI->getOperand(MI->getNumOperands()-1))) {
509 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
517 O << "\t\t\t-"; MI->print(O, TM); break;