1 //===- README_X86_64.txt - Notes for X86-64 code gen ----------------------===//
3 AMD64 Optimization Manual 8.2 has some nice information about optimizing integer
4 multiplication by a constant. How much of it applies to Intel's X86-64
5 implementation? There are definite trade-offs to consider: latency vs. register
6 pressure vs. code size.
8 //===---------------------------------------------------------------------===//
10 Are we better off using branches instead of cmove to implement FP to
14 ucomiss LC0(%rip), %xmm0
15 cvttss2siq %xmm0, %rdx
17 subss LC0(%rip), %xmm0
18 movabsq $-9223372036854775808, %rax
19 cvttss2siq %xmm0, %rdx
28 movss LCPI1_0(%rip), %xmm1
29 cvttss2siq %xmm0, %rcx
32 cvttss2siq %xmm2, %rax
33 movabsq $-9223372036854775808, %rdx
39 Seems like the jb branch has high likelyhood of being taken. It would have
40 saved a few instructions.
42 //===---------------------------------------------------------------------===//
49 memset(X, b, 2*sizeof(X[0]));
53 movq _b@GOTPCREL(%rip), %rax
63 movq _X@GOTPCREL(%rip), %rdx
69 movq _b@GOTPCREL(%rip), %rax
70 movabsq $72340172838076673, %rdx
73 movq _X@GOTPCREL(%rip), %rdx
77 //===---------------------------------------------------------------------===//
79 It's not possible to reference AH, BH, CH, and DH registers in an instruction
80 requiring REX prefix. However, divb and mulb both produce results in AH. If isel
81 emits a CopyFromReg which gets turned into a movb and that can be allocated a
84 To get around this, isel emits a CopyFromReg from AX and then right shift it
85 down by 8 and truncate it. It's not pretty but it works. We need some register
86 allocation magic to make the hack go away (e.g. putting additional constraints
87 on the result of the movb).
89 //===---------------------------------------------------------------------===//
91 The x86-64 ABI for hidden-argument struct returns requires that the
92 incoming value of %rdi be copied into %rax by the callee upon return.
94 The idea is that it saves callers from having to remember this value,
95 which would often require a callee-saved register. Callees usually
96 need to keep this value live for most of their body anyway, so it
97 doesn't add a significant burden on them.
99 We currently implement this in codegen, however this is suboptimal
100 because it means that it would be quite awkward to implement the
101 optimization for callers.
103 A better implementation would be to relax the LLVM IR rules for sret
104 arguments to allow a function with an sret argument to have a non-void
105 return type, and to have the front-end to set up the sret argument value
106 as the return value of the function. The front-end could more easily
107 emit uses of the returned struct value to be in terms of the function's
108 lowered return value, and it would free non-C frontends from a
109 complication only required by a C-based ABI.
111 //===---------------------------------------------------------------------===//
113 We get a redundant zero extension for code like this:
116 int foo(unsigned x) {
129 imull $78, %edi, %eax
131 movl %eax, %eax <----
132 movq _mask@GOTPCREL(%rip), %rcx
133 movl (%rcx,%rax,4), %eax
136 imull $45, %edi, %eax
139 Before regalloc, we have:
141 %reg1025<def> = IMUL32rri8 %reg1024, 45, %EFLAGS<imp-def>
142 JMP mbb<bb2,0x203afb0>
143 Successors according to CFG: 0x203afb0 (#3)
145 bb1: 0x203af60, LLVM BB @0x1e02310, ID#2:
146 Predecessors according to CFG: 0x203aec0 (#0)
147 %reg1026<def> = IMUL32rri8 %reg1024, 78, %EFLAGS<imp-def>
148 Successors according to CFG: 0x203afb0 (#3)
150 bb2: 0x203afb0, LLVM BB @0x1e02340, ID#3:
151 Predecessors according to CFG: 0x203af10 (#1) 0x203af60 (#2)
152 %reg1027<def> = PHI %reg1025, mbb<bb,0x203af10>,
153 %reg1026, mbb<bb1,0x203af60>
154 %reg1029<def> = MOVZX64rr32 %reg1027
156 so we'd have to know that IMUL32rri8 leaves the high word zero extended and to
157 be able to recognize the zero extend. This could also presumably be implemented
158 if we have whole-function selectiondags.
160 //===---------------------------------------------------------------------===//