1 //===---------------------------------------------------------------------===//
2 // Random ideas for the X86 backend.
3 //===---------------------------------------------------------------------===//
5 We should add support for the "movbe" instruction, which does a byte-swapping
6 copy (3-addr bswap + memory support?) This is available on Atom processors.
8 //===---------------------------------------------------------------------===//
10 CodeGen/X86/lea-3.ll:test3 should be a single LEA, not a shift/move. The X86
11 backend knows how to three-addressify this shift, but it appears the register
12 allocator isn't even asking it to do so in this case. We should investigate
13 why this isn't happening, it could have significant impact on other important
14 cases for X86 as well.
16 //===---------------------------------------------------------------------===//
18 This should be one DIV/IDIV instruction, not a libcall:
20 unsigned test(unsigned long long X, unsigned Y) {
24 This can be done trivially with a custom legalizer. What about overflow
25 though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
27 //===---------------------------------------------------------------------===//
29 Improvements to the multiply -> shift/add algorithm:
30 http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
32 //===---------------------------------------------------------------------===//
34 Improve code like this (occurs fairly frequently, e.g. in LLVM):
35 long long foo(int x) { return 1LL << x; }
37 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
38 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
39 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html
41 Another useful one would be ~0ULL >> X and ~0ULL << X.
43 One better solution for 1LL << x is:
52 But that requires good 8-bit subreg support.
54 Also, this might be better. It's an extra shift, but it's one instruction
55 shorter, and doesn't stress 8-bit subreg support.
56 (From http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01148.html,
57 but without the unnecessary and.)
65 64-bit shifts (in general) expand to really bad code. Instead of using
66 cmovs, we should expand to a conditional branch like GCC produces.
68 //===---------------------------------------------------------------------===//
71 _Bool f(_Bool a) { return a!=1; }
78 (Although note that this isn't a legal way to express the code that llvm-gcc
79 currently generates for that function.)
81 //===---------------------------------------------------------------------===//
85 1. Dynamic programming based approach when compile time if not an
87 2. Code duplication (addressing mode) during isel.
88 3. Other ideas from "Register-Sensitive Selection, Duplication, and
89 Sequencing of Instructions".
90 4. Scheduling for reduced register pressure. E.g. "Minimum Register
91 Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs"
92 and other related papers.
93 http://citeseer.ist.psu.edu/govindarajan01minimum.html
95 //===---------------------------------------------------------------------===//
97 Should we promote i16 to i32 to avoid partial register update stalls?
99 //===---------------------------------------------------------------------===//
101 Leave any_extend as pseudo instruction and hint to register
102 allocator. Delay codegen until post register allocation.
103 Note. any_extend is now turned into an INSERT_SUBREG. We still need to teach
104 the coalescer how to deal with it though.
106 //===---------------------------------------------------------------------===//
108 It appears icc use push for parameter passing. Need to investigate.
110 //===---------------------------------------------------------------------===//
112 Only use inc/neg/not instructions on processors where they are faster than
113 add/sub/xor. They are slower on the P4 due to only updating some processor
116 //===---------------------------------------------------------------------===//
118 The instruction selector sometimes misses folding a load into a compare. The
119 pattern is written as (cmp reg, (load p)). Because the compare isn't
120 commutative, it is not matched with the load on both sides. The dag combiner
121 should be made smart enough to cannonicalize the load into the RHS of a compare
122 when it can invert the result of the compare for free.
124 //===---------------------------------------------------------------------===//
126 In many cases, LLVM generates code like this:
135 on some processors (which ones?), it is more efficient to do this:
144 Doing this correctly is tricky though, as the xor clobbers the flags.
146 //===---------------------------------------------------------------------===//
148 We should generate bts/btr/etc instructions on targets where they are cheap or
149 when codesize is important. e.g., for:
151 void setbit(int *target, int bit) {
152 *target |= (1 << bit);
154 void clearbit(int *target, int bit) {
155 *target &= ~(1 << bit);
158 //===---------------------------------------------------------------------===//
160 Instead of the following for memset char*, 1, 10:
162 movl $16843009, 4(%edx)
163 movl $16843009, (%edx)
166 It might be better to generate
173 when we can spare a register. It reduces code size.
175 //===---------------------------------------------------------------------===//
177 Evaluate what the best way to codegen sdiv X, (2^C) is. For X/8, we currently
180 define i32 @test1(i32 %X) {
194 GCC knows several different ways to codegen it, one of which is this:
204 which is probably slower, but it's interesting at least :)
206 //===---------------------------------------------------------------------===//
208 We are currently lowering large (1MB+) memmove/memcpy to rep/stosl and rep/movsl
209 We should leave these as libcalls for everything over a much lower threshold,
210 since libc is hand tuned for medium and large mem ops (avoiding RFO for large
211 stores, TLB preheating, etc)
213 //===---------------------------------------------------------------------===//
215 Optimize this into something reasonable:
216 x * copysign(1.0, y) * copysign(1.0, z)
218 //===---------------------------------------------------------------------===//
220 Optimize copysign(x, *y) to use an integer load from y.
222 //===---------------------------------------------------------------------===//
224 The following tests perform worse with LSR:
226 lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
228 //===---------------------------------------------------------------------===//
230 Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 /
233 //===---------------------------------------------------------------------===//
235 Adding to the list of cmp / test poor codegen issues:
237 int test(__m128 *A, __m128 *B) {
238 if (_mm_comige_ss(*A, *B))
258 Note the setae, movzbl, cmpl, cmove can be replaced with a single cmovae. There
259 are a number of issues. 1) We are introducing a setcc between the result of the
260 intrisic call and select. 2) The intrinsic is expected to produce a i32 value
261 so a any extend (which becomes a zero extend) is added.
263 We probably need some kind of target DAG combine hook to fix this.
265 //===---------------------------------------------------------------------===//
267 We generate significantly worse code for this than GCC:
268 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=21150
269 http://gcc.gnu.org/bugzilla/attachment.cgi?id=8701
271 There is also one case we do worse on PPC.
273 //===---------------------------------------------------------------------===//
283 imull $3, 4(%esp), %eax
285 Perhaps this is what we really should generate is? Is imull three or four
286 cycles? Note: ICC generates this:
288 leal (%eax,%eax,2), %eax
290 The current instruction priority is based on pattern complexity. The former is
291 more "complex" because it folds a load so the latter will not be emitted.
293 Perhaps we should use AddedComplexity to give LEA32r a higher priority? We
294 should always try to match LEA first since the LEA matching code does some
295 estimate to determine whether the match is profitable.
297 However, if we care more about code size, then imull is better. It's two bytes
298 shorter than movl + leal.
300 On a Pentium M, both variants have the same characteristics with regard
301 to throughput; however, the multiplication has a latency of four cycles, as
302 opposed to two cycles for the movl+lea variant.
304 //===---------------------------------------------------------------------===//
306 __builtin_ffs codegen is messy.
308 int ffs_(unsigned X) { return __builtin_ffs(X); }
331 Another example of __builtin_ffs (use predsimplify to eliminate a select):
333 int foo (unsigned long j) {
335 return __builtin_ffs (j) - 1;
340 //===---------------------------------------------------------------------===//
342 It appears gcc place string data with linkonce linkage in
343 .section __TEXT,__const_coal,coalesced instead of
344 .section __DATA,__const_coal,coalesced.
345 Take a look at darwin.h, there are other Darwin assembler directives that we
348 //===---------------------------------------------------------------------===//
350 define i32 @foo(i32* %a, i32 %t) {
354 cond_true: ; preds = %cond_true, %entry
355 %x.0.0 = phi i32 [ 0, %entry ], [ %tmp9, %cond_true ] ; <i32> [#uses=3]
356 %t_addr.0.0 = phi i32 [ %t, %entry ], [ %tmp7, %cond_true ] ; <i32> [#uses=1]
357 %tmp2 = getelementptr i32* %a, i32 %x.0.0 ; <i32*> [#uses=1]
358 %tmp3 = load i32* %tmp2 ; <i32> [#uses=1]
359 %tmp5 = add i32 %t_addr.0.0, %x.0.0 ; <i32> [#uses=1]
360 %tmp7 = add i32 %tmp5, %tmp3 ; <i32> [#uses=2]
361 %tmp9 = add i32 %x.0.0, 1 ; <i32> [#uses=2]
362 %tmp = icmp sgt i32 %tmp9, 39 ; <i1> [#uses=1]
363 br i1 %tmp, label %bb12, label %cond_true
365 bb12: ; preds = %cond_true
368 is pessimized by -loop-reduce and -indvars
370 //===---------------------------------------------------------------------===//
372 u32 to float conversion improvement:
374 float uint32_2_float( unsigned u ) {
375 float fl = (int) (u & 0xffff);
376 float fh = (int) (u >> 16);
381 00000000 subl $0x04,%esp
382 00000003 movl 0x08(%esp,1),%eax
383 00000007 movl %eax,%ecx
384 00000009 shrl $0x10,%ecx
385 0000000c cvtsi2ss %ecx,%xmm0
386 00000010 andl $0x0000ffff,%eax
387 00000015 cvtsi2ss %eax,%xmm1
388 00000019 mulss 0x00000078,%xmm0
389 00000021 addss %xmm1,%xmm0
390 00000025 movss %xmm0,(%esp,1)
391 0000002a flds (%esp,1)
392 0000002d addl $0x04,%esp
395 //===---------------------------------------------------------------------===//
397 When using fastcc abi, align stack slot of argument of type double on 8 byte
398 boundary to improve performance.
400 //===---------------------------------------------------------------------===//
404 int f(int a, int b) {
405 if (a == 4 || a == 6)
417 //===---------------------------------------------------------------------===//
419 GCC's ix86_expand_int_movcc function (in i386.c) has a ton of interesting
420 simplifications for integer "x cmp y ? a : b". For example, instead of:
423 void f(int X, int Y) {
450 int usesbb(unsigned int a, unsigned int b) {
451 return (a < b ? -1 : 0);
465 movl $4294967295, %ecx
469 //===---------------------------------------------------------------------===//
471 Consider the expansion of:
473 define i32 @test3(i32 %X) {
474 %tmp1 = urem i32 %X, 255
478 Currently it compiles to:
481 movl $2155905153, %ecx
487 This could be "reassociated" into:
489 movl $2155905153, %eax
493 to avoid the copy. In fact, the existing two-address stuff would do this
494 except that mul isn't a commutative 2-addr instruction. I guess this has
495 to be done at isel time based on the #uses to mul?
497 //===---------------------------------------------------------------------===//
499 Make sure the instruction which starts a loop does not cross a cacheline
500 boundary. This requires knowning the exact length of each machine instruction.
501 That is somewhat complicated, but doable. Example 256.bzip2:
503 In the new trace, the hot loop has an instruction which crosses a cacheline
504 boundary. In addition to potential cache misses, this can't help decoding as I
505 imagine there has to be some kind of complicated decoder reset and realignment
506 to grab the bytes from the next cacheline.
508 532 532 0x3cfc movb (1809(%esp, %esi), %bl <<<--- spans 2 64 byte lines
509 942 942 0x3d03 movl %dh, (1809(%esp, %esi)
510 937 937 0x3d0a incl %esi
511 3 3 0x3d0b cmpb %bl, %dl
512 27 27 0x3d0d jnz 0x000062db <main+11707>
514 //===---------------------------------------------------------------------===//
516 In c99 mode, the preprocessor doesn't like assembly comments like #TRUNCATE.
518 //===---------------------------------------------------------------------===//
520 This could be a single 16-bit load.
523 if ((p[0] == 1) & (p[1] == 2)) return 1;
527 //===---------------------------------------------------------------------===//
529 We should inline lrintf and probably other libc functions.
531 //===---------------------------------------------------------------------===//
533 Use the FLAGS values from arithmetic instructions more. For example, compile:
535 int add_zf(int *x, int y, int a, int b) {
557 As another example, compile function f2 in test/CodeGen/X86/cmp-test.ll
558 without a test instruction.
560 //===---------------------------------------------------------------------===//
562 These two functions have identical effects:
564 unsigned int f(unsigned int i, unsigned int n) {++i; if (i == n) ++i; return i;}
565 unsigned int f2(unsigned int i, unsigned int n) {++i; i += i == n; return i;}
567 We currently compile them to:
575 jne LBB1_2 #UnifiedReturnBlock
579 LBB1_2: #UnifiedReturnBlock
589 leal 1(%ecx,%eax), %eax
592 both of which are inferior to GCC's:
610 //===---------------------------------------------------------------------===//
618 is currently compiled to:
629 It would be better to produce:
638 This can be applied to any no-return function call that takes no arguments etc.
639 Alternatively, the stack save/restore logic could be shrink-wrapped, producing
650 Both are useful in different situations. Finally, it could be shrink-wrapped
651 and tail called, like this:
658 pop %eax # realign stack.
661 Though this probably isn't worth it.
663 //===---------------------------------------------------------------------===//
665 Sometimes it is better to codegen subtractions from a constant (e.g. 7-x) with
666 a neg instead of a sub instruction. Consider:
668 int test(char X) { return 7-X; }
670 we currently produce:
677 We would use one fewer register if codegen'd as:
684 Note that this isn't beneficial if the load can be folded into the sub. In
685 this case, we want a sub:
687 int test(int X) { return 7-X; }
693 //===---------------------------------------------------------------------===//
695 Leaf functions that require one 4-byte spill slot have a prolog like this:
701 and an epilog like this:
706 It would be smaller, and potentially faster, to push eax on entry and to
707 pop into a dummy register instead of using addl/subl of esp. Just don't pop
708 into any return registers :)
710 //===---------------------------------------------------------------------===//
712 The X86 backend should fold (branch (or (setcc, setcc))) into multiple
713 branches. We generate really poor code for:
715 double testf(double a) {
716 return a == 0.0 ? 0.0 : (a > 0.0 ? 1.0 : -1.0);
719 For example, the entry BB is:
724 movsd 24(%esp), %xmm1
729 jne LBB1_5 # UnifiedReturnBlock
733 it would be better to replace the last four instructions with:
739 We also codegen the inner ?: into a diamond:
741 cvtss2sd LCPI1_0(%rip), %xmm2
742 cvtss2sd LCPI1_1(%rip), %xmm3
744 ja LBB1_3 # cond_true
751 We should sink the load into xmm3 into the LBB1_2 block. This should
752 be pretty easy, and will nuke all the copies.
754 //===---------------------------------------------------------------------===//
758 inline std::pair<unsigned, bool> full_add(unsigned a, unsigned b)
759 { return std::make_pair(a + b, a + b < a); }
760 bool no_overflow(unsigned a, unsigned b)
761 { return !full_add(a, b).second; }
771 FIXME: That code looks wrong; bool return is normally defined as zext.
783 //===---------------------------------------------------------------------===//
787 bb114.preheader: ; preds = %cond_next94
788 %tmp231232 = sext i16 %tmp62 to i32 ; <i32> [#uses=1]
789 %tmp233 = sub i32 32, %tmp231232 ; <i32> [#uses=1]
790 %tmp245246 = sext i16 %tmp65 to i32 ; <i32> [#uses=1]
791 %tmp252253 = sext i16 %tmp68 to i32 ; <i32> [#uses=1]
792 %tmp254 = sub i32 32, %tmp252253 ; <i32> [#uses=1]
793 %tmp553554 = bitcast i16* %tmp37 to i8* ; <i8*> [#uses=2]
794 %tmp583584 = sext i16 %tmp98 to i32 ; <i32> [#uses=1]
795 %tmp585 = sub i32 32, %tmp583584 ; <i32> [#uses=1]
796 %tmp614615 = sext i16 %tmp101 to i32 ; <i32> [#uses=1]
797 %tmp621622 = sext i16 %tmp104 to i32 ; <i32> [#uses=1]
798 %tmp623 = sub i32 32, %tmp621622 ; <i32> [#uses=1]
803 LBB3_5: # bb114.preheader
804 movswl -68(%ebp), %eax
808 movswl -52(%ebp), %eax
811 movswl -70(%ebp), %eax
814 movswl -50(%ebp), %eax
817 movswl -42(%ebp), %eax
819 movswl -66(%ebp), %eax
823 This appears to be bad because the RA is not folding the store to the stack
824 slot into the movl. The above instructions could be:
829 This seems like a cross between remat and spill folding.
831 This has redundant subtractions of %eax from a stack slot. However, %ecx doesn't
832 change, so we could simply subtract %eax from %ecx first and then use %ecx (or
835 //===---------------------------------------------------------------------===//
839 %tmp659 = icmp slt i16 %tmp654, 0 ; <i1> [#uses=1]
840 br i1 %tmp659, label %cond_true662, label %cond_next715
846 jns LBB4_109 # cond_next715
848 Shark tells us that using %cx in the testw instruction is sub-optimal. It
849 suggests using the 32-bit register (which is what ICC uses).
851 //===---------------------------------------------------------------------===//
855 void compare (long long foo) {
856 if (foo < 4294967297LL)
872 jne .LBB1_2 # UnifiedReturnBlock
875 .LBB1_2: # UnifiedReturnBlock
879 (also really horrible code on ppc). This is due to the expand code for 64-bit
880 compares. GCC produces multiple branches, which is much nicer:
901 //===---------------------------------------------------------------------===//
903 Tail call optimization improvements: Tail call optimization currently
904 pushes all arguments on the top of the stack (their normal place for
905 non-tail call optimized calls) that source from the callers arguments
906 or that source from a virtual register (also possibly sourcing from
908 This is done to prevent overwriting of parameters (see example
909 below) that might be used later.
913 int callee(int32, int64);
914 int caller(int32 arg1, int32 arg2) {
915 int64 local = arg2 * 2;
916 return callee(arg2, (int64)local);
919 [arg1] [!arg2 no longer valid since we moved local onto it]
923 Moving arg1 onto the stack slot of callee function would overwrite
926 Possible optimizations:
929 - Analyse the actual parameters of the callee to see which would
930 overwrite a caller parameter which is used by the callee and only
931 push them onto the top of the stack.
933 int callee (int32 arg1, int32 arg2);
934 int caller (int32 arg1, int32 arg2) {
935 return callee(arg1,arg2);
938 Here we don't need to write any variables to the top of the stack
939 since they don't overwrite each other.
941 int callee (int32 arg1, int32 arg2);
942 int caller (int32 arg1, int32 arg2) {
943 return callee(arg2,arg1);
946 Here we need to push the arguments because they overwrite each
949 //===---------------------------------------------------------------------===//
954 unsigned long int z = 0;
965 gcc compiles this to:
991 jge LBB1_4 # cond_true
994 addl $4294950912, %ecx
1004 1. LSR should rewrite the first cmp with induction variable %ecx.
1005 2. DAG combiner should fold
1011 //===---------------------------------------------------------------------===//
1013 define i64 @test(double %X) {
1014 %Y = fptosi double %X to i64
1022 movsd 24(%esp), %xmm0
1023 movsd %xmm0, 8(%esp)
1032 This should just fldl directly from the input stack slot.
1034 //===---------------------------------------------------------------------===//
1037 int foo (int x) { return (x & 65535) | 255; }
1039 Should compile into:
1042 movzwl 4(%esp), %eax
1053 //===---------------------------------------------------------------------===//
1055 We're codegen'ing multiply of long longs inefficiently:
1057 unsigned long long LLM(unsigned long long arg1, unsigned long long arg2) {
1061 We compile to (fomit-frame-pointer):
1069 imull 12(%esp), %esi
1071 imull 20(%esp), %ecx
1077 This looks like a scheduling deficiency and lack of remat of the load from
1078 the argument area. ICC apparently produces:
1081 imull 12(%esp), %ecx
1090 Note that it remat'd loads from 4(esp) and 12(esp). See this GCC PR:
1091 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=17236
1093 //===---------------------------------------------------------------------===//
1095 We can fold a store into "zeroing a reg". Instead of:
1098 movl %eax, 124(%esp)
1104 if the flags of the xor are dead.
1106 Likewise, we isel "x<<1" into "add reg,reg". If reg is spilled, this should
1107 be folded into: shl [mem], 1
1109 //===---------------------------------------------------------------------===//
1111 This testcase misses a read/modify/write opportunity (from PR1425):
1113 void vertical_decompose97iH1(int *b0, int *b1, int *b2, int width){
1115 for(i=0; i<width; i++)
1116 b1[i] += (1*(b0[i] + b2[i])+0)>>0;
1119 We compile it down to:
1122 movl (%esi,%edi,4), %ebx
1123 addl (%ecx,%edi,4), %ebx
1124 addl (%edx,%edi,4), %ebx
1125 movl %ebx, (%ecx,%edi,4)
1130 the inner loop should add to the memory location (%ecx,%edi,4), saving
1131 a mov. Something like:
1133 movl (%esi,%edi,4), %ebx
1134 addl (%edx,%edi,4), %ebx
1135 addl %ebx, (%ecx,%edi,4)
1137 Here is another interesting example:
1139 void vertical_compose97iH1(int *b0, int *b1, int *b2, int width){
1141 for(i=0; i<width; i++)
1142 b1[i] -= (1*(b0[i] + b2[i])+0)>>0;
1145 We miss the r/m/w opportunity here by using 2 subs instead of an add+sub[mem]:
1148 movl (%ecx,%edi,4), %ebx
1149 subl (%esi,%edi,4), %ebx
1150 subl (%edx,%edi,4), %ebx
1151 movl %ebx, (%ecx,%edi,4)
1156 Additionally, LSR should rewrite the exit condition of these loops to use
1157 a stride-4 IV, would would allow all the scales in the loop to go away.
1158 This would result in smaller code and more efficient microops.
1160 //===---------------------------------------------------------------------===//
1162 In SSE mode, we turn abs and neg into a load from the constant pool plus a xor
1163 or and instruction, for example:
1165 xorpd LCPI1_0, %xmm2
1167 However, if xmm2 gets spilled, we end up with really ugly code like this:
1170 xorpd LCPI1_0, %xmm0
1173 Since we 'know' that this is a 'neg', we can actually "fold" the spill into
1174 the neg/abs instruction, turning it into an *integer* operation, like this:
1176 xorl 2147483648, [mem+4] ## 2147483648 = (1 << 31)
1178 you could also use xorb, but xorl is less likely to lead to a partial register
1179 stall. Here is a contrived testcase:
1182 void test(double *P) {
1192 //===---------------------------------------------------------------------===//
1194 handling llvm.memory.barrier on pre SSE2 cpus
1197 lock ; mov %esp, %esp
1199 //===---------------------------------------------------------------------===//
1201 The generated code on x86 for checking for signed overflow on a multiply the
1202 obvious way is much longer than it needs to be.
1204 int x(int a, int b) {
1205 long long prod = (long long)a*b;
1206 return prod > 0x7FFFFFFF || prod < (-0x7FFFFFFF-1);
1209 See PR2053 for more details.
1211 //===---------------------------------------------------------------------===//
1213 We should investigate using cdq/ctld (effect: edx = sar eax, 31)
1214 more aggressively; it should cost the same as a move+shift on any modern
1215 processor, but it's a lot shorter. Downside is that it puts more
1216 pressure on register allocation because it has fixed operands.
1219 int abs(int x) {return x < 0 ? -x : x;}
1221 gcc compiles this to the following when using march/mtune=pentium2/3/4/m/etc.:
1229 //===---------------------------------------------------------------------===//
1232 int test(unsigned long a, unsigned long b) { return -(a < b); }
1234 We currently compile this to:
1236 define i32 @test(i32 %a, i32 %b) nounwind {
1237 %tmp3 = icmp ult i32 %a, %b ; <i1> [#uses=1]
1238 %tmp34 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
1239 %tmp5 = sub i32 0, %tmp34 ; <i32> [#uses=1]
1253 Several deficiencies here. First, we should instcombine zext+neg into sext:
1255 define i32 @test2(i32 %a, i32 %b) nounwind {
1256 %tmp3 = icmp ult i32 %a, %b ; <i1> [#uses=1]
1257 %tmp34 = sext i1 %tmp3 to i32 ; <i32> [#uses=1]
1261 However, before we can do that, we have to fix the bad codegen that we get for
1273 This code should be at least as good as the code above. Once this is fixed, we
1274 can optimize this specific case even more to:
1281 //===---------------------------------------------------------------------===//
1283 Take the following code (from
1284 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=16541):
1286 extern unsigned char first_one[65536];
1287 int FirstOnet(unsigned long long arg1)
1290 return (first_one[arg1 >> 48]);
1295 The following code is currently generated:
1300 jb .LBB1_2 # UnifiedReturnBlock
1303 movzbl first_one(%eax), %eax
1305 .LBB1_2: # UnifiedReturnBlock
1309 There are a few possible improvements here:
1310 1. We should be able to eliminate the dead load into %ecx
1311 2. We could change the "movl 8(%esp), %eax" into
1312 "movzwl 10(%esp), %eax"; this lets us change the cmpl
1313 into a testl, which is shorter, and eliminate the shift.
1315 We could also in theory eliminate the branch by using a conditional
1316 for the address of the load, but that seems unlikely to be worthwhile
1319 //===---------------------------------------------------------------------===//
1321 We compile this function:
1323 define i32 @foo(i32 %a, i32 %b, i32 %c, i8 zeroext %d) nounwind {
1325 %tmp2 = icmp eq i8 %d, 0 ; <i1> [#uses=1]
1326 br i1 %tmp2, label %bb7, label %bb
1328 bb: ; preds = %entry
1329 %tmp6 = add i32 %b, %a ; <i32> [#uses=1]
1332 bb7: ; preds = %entry
1333 %tmp10 = sub i32 %a, %c ; <i32> [#uses=1]
1353 The coalescer could coalesce "edx" with "eax" to avoid the movl in LBB1_2
1354 if it commuted the addl in LBB1_1.
1356 //===---------------------------------------------------------------------===//
1363 cvtss2sd LCPI1_0, %xmm1
1365 movsd 176(%esp), %xmm2
1370 mulsd LCPI1_23, %xmm4
1371 addsd LCPI1_24, %xmm4
1373 addsd LCPI1_25, %xmm4
1375 addsd LCPI1_26, %xmm4
1377 addsd LCPI1_27, %xmm4
1379 addsd LCPI1_28, %xmm4
1383 movsd 152(%esp), %xmm1
1385 movsd %xmm1, 152(%esp)
1389 LBB1_16: # bb358.loopexit
1390 movsd 152(%esp), %xmm0
1392 addsd LCPI1_22, %xmm0
1393 movsd %xmm0, 152(%esp)
1395 Rather than spilling the result of the last addsd in the loop, we should have
1396 insert a copy to split the interval (one for the duration of the loop, one
1397 extending to the fall through). The register pressure in the loop isn't high
1398 enough to warrant the spill.
1400 Also check why xmm7 is not used at all in the function.
1402 //===---------------------------------------------------------------------===//
1404 Legalize loses track of the fact that bools are always zero extended when in
1405 memory. This causes us to compile abort_gzip (from 164.gzip) from:
1407 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
1408 target triple = "i386-apple-darwin8"
1409 @in_exit.4870.b = internal global i1 false ; <i1*> [#uses=2]
1410 define fastcc void @abort_gzip() noreturn nounwind {
1412 %tmp.b.i = load i1* @in_exit.4870.b ; <i1> [#uses=1]
1413 br i1 %tmp.b.i, label %bb.i, label %bb4.i
1414 bb.i: ; preds = %entry
1415 tail call void @exit( i32 1 ) noreturn nounwind
1417 bb4.i: ; preds = %entry
1418 store i1 true, i1* @in_exit.4870.b
1419 tail call void @exit( i32 1 ) noreturn nounwind
1422 declare void @exit(i32) noreturn nounwind
1428 movb _in_exit.4870.b, %al
1435 //===---------------------------------------------------------------------===//
1439 int test(int x, int y) {
1451 it would be better to codegen as: x+~y (notl+addl)
1453 //===---------------------------------------------------------------------===//
1457 int foo(const char *str,...)
1459 __builtin_va_list a; int x;
1460 __builtin_va_start(a,str); x = __builtin_va_arg(a,int); __builtin_va_end(a);
1464 gets compiled into this on x86-64:
1466 movaps %xmm7, 160(%rsp)
1467 movaps %xmm6, 144(%rsp)
1468 movaps %xmm5, 128(%rsp)
1469 movaps %xmm4, 112(%rsp)
1470 movaps %xmm3, 96(%rsp)
1471 movaps %xmm2, 80(%rsp)
1472 movaps %xmm1, 64(%rsp)
1473 movaps %xmm0, 48(%rsp)
1480 movq %rax, 192(%rsp)
1481 leaq 208(%rsp), %rax
1482 movq %rax, 184(%rsp)
1485 movl 176(%rsp), %eax
1489 movq 184(%rsp), %rcx
1491 movq %rax, 184(%rsp)
1499 addq 192(%rsp), %rcx
1500 movl %eax, 176(%rsp)
1506 leaq 104(%rsp), %rax
1507 movq %rsi, -80(%rsp)
1509 movq %rax, -112(%rsp)
1510 leaq -88(%rsp), %rax
1511 movq %rax, -104(%rsp)
1515 movq -112(%rsp), %rdx
1523 addq -104(%rsp), %rdx
1525 movl %eax, -120(%rsp)
1530 and it gets compiled into this on x86:
1550 //===---------------------------------------------------------------------===//
1552 Teach tblgen not to check bitconvert source type in some cases. This allows us
1553 to consolidate the following patterns in X86InstrMMX.td:
1555 def : Pat<(v2i32 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
1557 (v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
1558 def : Pat<(v4i16 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
1560 (v4i16 (MMX_MOVDQ2Qrr VR128:$src))>;
1561 def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
1563 (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;
1565 There are other cases in various td files.
1567 //===---------------------------------------------------------------------===//
1569 Take something like the following on x86-32:
1570 unsigned a(unsigned long long x, unsigned y) {return x % y;}
1572 We currently generate a libcall, but we really shouldn't: the expansion is
1573 shorter and likely faster than the libcall. The expected code is something
1585 A similar code sequence works for division.
1587 //===---------------------------------------------------------------------===//
1589 These should compile to the same code, but the later codegen's to useless
1590 instructions on X86. This may be a trivial dag combine (GCC PR7061):
1592 struct s1 { unsigned char a, b; };
1593 unsigned long f1(struct s1 x) {
1596 struct s2 { unsigned a: 8, b: 8; };
1597 unsigned long f2(struct s2 x) {
1601 //===---------------------------------------------------------------------===//
1603 We currently compile this:
1605 define i32 @func1(i32 %v1, i32 %v2) nounwind {
1607 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
1608 %sum = extractvalue {i32, i1} %t, 0
1609 %obit = extractvalue {i32, i1} %t, 1
1610 br i1 %obit, label %overflow, label %normal
1614 call void @llvm.trap()
1617 declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32)
1618 declare void @llvm.trap()
1625 jo LBB1_2 ## overflow
1631 it would be nice to produce "into" someday.
1633 //===---------------------------------------------------------------------===//
1637 void vec_mpys1(int y[], const int x[], int scaler) {
1639 for (i = 0; i < 150; i++)
1640 y[i] += (((long long)scaler * (long long)x[i]) >> 31);
1643 Compiles to this loop with GCC 3.x:
1648 shrdl $31, %edx, %eax
1649 addl %eax, (%esi,%ecx,4)
1654 llvm-gcc compiles it to the much uglier:
1658 movl (%eax,%edi,4), %ebx
1667 shldl $1, %eax, %ebx
1669 addl %ebx, (%eax,%edi,4)
1674 The issue is that we hoist the cast of "scaler" to long long outside of the
1675 loop, the value comes into the loop as two values, and
1676 RegsForValue::getCopyFromRegs doesn't know how to put an AssertSext on the
1677 constructed BUILD_PAIR which represents the cast value.
1679 //===---------------------------------------------------------------------===//
1681 Test instructions can be eliminated by using EFLAGS values from arithmetic
1682 instructions. This is currently not done for mul, and, or, xor, neg, shl,
1683 sra, srl, shld, shrd, atomic ops, and others. It is also currently not done
1684 for read-modify-write instructions. It is also current not done if the
1685 OF or CF flags are needed.
1687 The shift operators have the complication that when the shift count is
1688 zero, EFLAGS is not set, so they can only subsume a test instruction if
1689 the shift count is known to be non-zero. Also, using the EFLAGS value
1690 from a shift is apparently very slow on some x86 implementations.
1692 In read-modify-write instructions, the root node in the isel match is
1693 the store, and isel has no way for the use of the EFLAGS result of the
1694 arithmetic to be remapped to the new node.
1696 Add and subtract instructions set OF on signed overflow and CF on unsiged
1697 overflow, while test instructions always clear OF and CF. In order to
1698 replace a test with an add or subtract in a situation where OF or CF is
1699 needed, codegen must be able to prove that the operation cannot see
1700 signed or unsigned overflow, respectively.
1702 //===---------------------------------------------------------------------===//
1704 memcpy/memmove do not lower to SSE copies when possible. A silly example is:
1705 define <16 x float> @foo(<16 x float> %A) nounwind {
1706 %tmp = alloca <16 x float>, align 16
1707 %tmp2 = alloca <16 x float>, align 16
1708 store <16 x float> %A, <16 x float>* %tmp
1709 %s = bitcast <16 x float>* %tmp to i8*
1710 %s2 = bitcast <16 x float>* %tmp2 to i8*
1711 call void @llvm.memcpy.i64(i8* %s, i8* %s2, i64 64, i32 16)
1712 %R = load <16 x float>* %tmp2
1716 declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind
1722 movaps %xmm3, 112(%esp)
1723 movaps %xmm2, 96(%esp)
1724 movaps %xmm1, 80(%esp)
1725 movaps %xmm0, 64(%esp)
1727 movl %eax, 124(%esp)
1729 movl %eax, 120(%esp)
1731 <many many more 32-bit copies>
1732 movaps (%esp), %xmm0
1733 movaps 16(%esp), %xmm1
1734 movaps 32(%esp), %xmm2
1735 movaps 48(%esp), %xmm3
1739 On Nehalem, it may even be cheaper to just use movups when unaligned than to
1740 fall back to lower-granularity chunks.
1742 //===---------------------------------------------------------------------===//
1744 Implement processor-specific optimizations for parity with GCC on these
1745 processors. GCC does two optimizations:
1747 1. ix86_pad_returns inserts a noop before ret instructions if immediately
1748 preceeded by a conditional branch or is the target of a jump.
1749 2. ix86_avoid_jump_misspredicts inserts noops in cases where a 16-byte block of
1750 code contains more than 3 branches.
1752 The first one is done for all AMDs, Core2, and "Generic"
1753 The second one is done for: Atom, Pentium Pro, all AMDs, Pentium 4, Nocona,
1754 Core 2, and "Generic"
1756 //===---------------------------------------------------------------------===//
1759 int a(int x) { return (x & 127) > 31; }
1775 This should definitely be done in instcombine, canonicalizing the range
1776 condition into a != condition. We get this IR:
1778 define i32 @a(i32 %x) nounwind readnone {
1780 %0 = and i32 %x, 127 ; <i32> [#uses=1]
1781 %1 = icmp ugt i32 %0, 31 ; <i1> [#uses=1]
1782 %2 = zext i1 %1 to i32 ; <i32> [#uses=1]
1786 Instcombine prefers to strength reduce relational comparisons to equality
1787 comparisons when possible, this should be another case of that. This could
1788 be handled pretty easily in InstCombiner::visitICmpInstWithInstAndIntCst, but it
1789 looks like InstCombiner::visitICmpInstWithInstAndIntCst should really already
1790 be redesigned to use ComputeMaskedBits and friends.
1793 //===---------------------------------------------------------------------===//
1795 int x(int a) { return (a&0xf0)>>4; }
1804 movzbl 4(%esp), %eax
1808 //===---------------------------------------------------------------------===//
1811 int x(int a) { return (a & 0x80) ? 0x100 : 0; }
1812 int y(int a) { return (a & 0x80) *2; }
1827 This is another general instcombine transformation that is profitable on all
1828 targets. In LLVM IR, these functions look like this:
1830 define i32 @x(i32 %a) nounwind readnone {
1832 %0 = and i32 %a, 128
1833 %1 = icmp eq i32 %0, 0
1834 %iftmp.0.0 = select i1 %1, i32 0, i32 256
1838 define i32 @y(i32 %a) nounwind readnone {
1841 %1 = and i32 %0, 256
1845 Replacing an icmp+select with a shift should always be considered profitable in
1848 //===---------------------------------------------------------------------===//
1850 Re-implement atomic builtins __sync_add_and_fetch() and __sync_sub_and_fetch
1853 When the return value is not used (i.e. only care about the value in the
1854 memory), x86 does not have to use add to implement these. Instead, it can use
1855 add, sub, inc, dec instructions with the "lock" prefix.
1857 This is currently implemented using a bit of instruction selection trick. The
1858 issue is the target independent pattern produces one output and a chain and we
1859 want to map it into one that just output a chain. The current trick is to select
1860 it into a MERGE_VALUES with the first definition being an implicit_def. The
1861 proper solution is to add new ISD opcodes for the no-output variant. DAG
1862 combiner can then transform the node before it gets to target node selection.
1864 Problem #2 is we are adding a whole bunch of x86 atomic instructions when in
1865 fact these instructions are identical to the non-lock versions. We need a way to
1866 add target specific information to target nodes and have this information
1867 carried over to machine instructions. Asm printer (or JIT) can use this
1868 information to add the "lock" prefix.
1870 //===---------------------------------------------------------------------===//
1872 _Bool bar(int *x) { return *x & 1; }
1874 define zeroext i1 @bar(i32* nocapture %x) nounwind readonly {
1876 %tmp1 = load i32* %x ; <i32> [#uses=1]
1877 %and = and i32 %tmp1, 1 ; <i32> [#uses=1]
1878 %tobool = icmp ne i32 %and, 0 ; <i1> [#uses=1]
1890 Missed optimization: should be movl+andl.
1892 //===---------------------------------------------------------------------===//
1894 Consider the following two functions compiled with clang:
1895 _Bool foo(int *x) { return !(*x & 4); }
1896 unsigned bar(int *x) { return !(*x & 4); }
1913 The second function generates more code even though the two functions are
1914 are functionally identical.
1916 //===---------------------------------------------------------------------===//
1918 Take the following C code:
1919 int x(int y) { return (y & 63) << 14; }
1921 Code produced by gcc:
1927 Code produced by clang:
1933 The code produced by gcc is 3 bytes shorter. This sort of construct often
1934 shows up with bitfields.
1936 //===---------------------------------------------------------------------===//